source: PlatformSupport/Deprecated/pcores/user_io_board_controller_plbw_v1_01_a/data/user_io_board_controller_plbw_v2_1_0.pao

Last change on this file was 1051, checked in by murphpo, 16 years ago

Updated LCD controller with line/character offsets
File size: 1.1 KB
Line 
1#############################################################
2# Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
3#
4# You may copy and modify these files for your own internal
5# use solely with Xilinx programmable logic devices and
6# Xilinx EDK system or create IP modules solely for Xilinx
7# programmable logic devices and Xilinx EDK system.
8# No rights are granted to distribute any files unless they
9# are distributed in Xilinx programmable logic devices.
10#
11# Peripheral Analyze Order (PAO) file
12# created by System Generator
13# Aug 6, 2008 5:23:41 PM
14#############################################################
15
16lib user_io_board_controller_plbw_v1_01_a user_io_board_controller vhdl
17lib user_io_board_controller_plbw_v1_01_a dual_port_block_memory_virtex2p_6_3_e98c3706f2ec2c76 vhdl
18lib user_io_board_controller_plbw_v1_01_a dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 vhdl
19lib user_io_board_controller_plbw_v1_01_a dual_port_block_memory_virtex2p_6_3_25371f622c89ba44 vhdl
20lib user_io_board_controller_plbw_v1_01_a user_io_board_controller_plbw vhdl
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