source: PlatformSupport/Deprecated/pcores/user_io_board_controller_plbw_v1_01_a/hdl/vhdl/dual_port_block_memory_virtex2p_6_3_25371f622c89ba44.vhd

Last change on this file was 1051, checked in by murphpo, 16 years ago

Updated LCD controller with line/character offsets
File size: 6.0 KB
Line 
1--------------------------------------------------------------------------------
2--     This file is owned and controlled by Xilinx and must be used           --
3--     solely for design, simulation, implementation and creation of          --
4--     design files limited to Xilinx devices or technologies. Use            --
5--     with non-Xilinx devices or technologies is expressly prohibited        --
6--     and immediately terminates your license.                               --
7--                                                                            --
8--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
9--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                --
10--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
11--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
12--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS              --
13--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                --
14--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE       --
15--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY               --
16--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                --
17--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR         --
18--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF        --
19--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS        --
20--     FOR A PARTICULAR PURPOSE.                                              --
21--                                                                            --
22--     Xilinx products are not intended for use in life support               --
23--     appliances, devices, or systems. Use in such applications are          --
24--     expressly prohibited.                                                  --
25--                                                                            --
26--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
27--     All rights reserved.                                                   --
28--------------------------------------------------------------------------------
29-- You must compile the wrapper file dual_port_block_memory_virtex2p_6_3_25371f622c89ba44.vhd when simulating
30-- the core, dual_port_block_memory_virtex2p_6_3_25371f622c89ba44. When compiling the wrapper file, be sure to
31-- reference the XilinxCoreLib VHDL simulation library. For detailed
32-- instructions, please refer to the "CORE Generator Help".
33
34-- The synthesis directives "translate_off/translate_on" specified
35-- below are supported by Xilinx, Mentor Graphics and Synplicity
36-- synthesis tools. Ensure they are correct for your synthesis tool(s).
37
38LIBRARY ieee;
39USE ieee.std_logic_1164.ALL;
40-- synthesis translate_off
41Library XilinxCoreLib;
42-- synthesis translate_on
43ENTITY dual_port_block_memory_virtex2p_6_3_25371f622c89ba44 IS
44    port (
45    addra: IN std_logic_VECTOR(8 downto 0);
46    addrb: IN std_logic_VECTOR(8 downto 0);
47    clka: IN std_logic;
48    clkb: IN std_logic;
49    dina: IN std_logic_VECTOR(31 downto 0);
50    dinb: IN std_logic_VECTOR(31 downto 0);
51    douta: OUT std_logic_VECTOR(31 downto 0);
52    doutb: OUT std_logic_VECTOR(31 downto 0);
53    ena: IN std_logic;
54    enb: IN std_logic;
55    wea: IN std_logic;
56    web: IN std_logic);
57END dual_port_block_memory_virtex2p_6_3_25371f622c89ba44;
58
59ARCHITECTURE dual_port_block_memory_virtex2p_6_3_25371f622c89ba44_a OF dual_port_block_memory_virtex2p_6_3_25371f622c89ba44 IS
60-- synthesis translate_off
61component wrapped_dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
62    port (
63    addra: IN std_logic_VECTOR(8 downto 0);
64    addrb: IN std_logic_VECTOR(8 downto 0);
65    clka: IN std_logic;
66    clkb: IN std_logic;
67    dina: IN std_logic_VECTOR(31 downto 0);
68    dinb: IN std_logic_VECTOR(31 downto 0);
69    douta: OUT std_logic_VECTOR(31 downto 0);
70    doutb: OUT std_logic_VECTOR(31 downto 0);
71    ena: IN std_logic;
72    enb: IN std_logic;
73    wea: IN std_logic;
74    web: IN std_logic);
75end component;
76
77-- Configuration specification
78    for all : wrapped_dual_port_block_memory_virtex2p_6_3_25371f622c89ba44 use entity XilinxCoreLib.blkmemdp_v6_3(behavioral)
79        generic map(
80            c_reg_inputsb => 0,
81            c_reg_inputsa => 0,
82            c_has_ndb => 0,
83            c_has_nda => 0,
84            c_ytop_addr => "1024",
85            c_has_rfdb => 0,
86            c_has_rfda => 0,
87            c_ywea_is_high => 1,
88            c_yena_is_high => 1,
89            c_yclka_is_rising => 1,
90            c_yhierarchy => "hierarchy1",
91            c_ysinita_is_high => 1,
92            c_ybottom_addr => "0",
93            c_width_b => 32,
94            c_width_a => 32,
95            c_sinita_value => "0",
96            c_sinitb_value => "0",
97            c_limit_data_pitch => 18,
98            c_write_modeb => 0,
99            c_write_modea => 0,
100            c_has_rdyb => 0,
101            c_yuse_single_primitive => 0,
102            c_has_rdya => 0,
103            c_addra_width => 9,
104            c_addrb_width => 9,
105            c_has_limit_data_pitch => 0,
106            c_default_data => "0",
107            c_pipe_stages_b => 0,
108            c_yweb_is_high => 1,
109            c_yenb_is_high => 1,
110            c_pipe_stages_a => 0,
111            c_yclkb_is_rising => 1,
112            c_yydisable_warnings => 1,
113            c_enable_rlocs => 0,
114            c_ysinitb_is_high => 1,
115            c_has_web => 1,
116            c_has_default_data => 0,
117            c_has_sinitb => 0,
118            c_has_wea => 1,
119            c_has_sinita => 0,
120            c_has_dinb => 1,
121            c_has_dina => 1,
122            c_ymake_bmm => 0,
123            c_sim_collision_check => "NONE",
124            c_has_enb => 1,
125            c_has_ena => 1,
126            c_mem_init_file => "dual_port_block_memory_virtex2p_6_3_25371f622c89ba44.mif",
127            c_depth_b => 512,
128            c_depth_a => 512,
129            c_has_doutb => 1,
130            c_has_douta => 1,
131            c_yprimitive_type => "16kx1");
132-- synthesis translate_on
133BEGIN
134-- synthesis translate_off
135U0 : wrapped_dual_port_block_memory_virtex2p_6_3_25371f622c89ba44
136        port map (
137            addra => addra,
138            addrb => addrb,
139            clka => clka,
140            clkb => clkb,
141            dina => dina,
142            dinb => dinb,
143            douta => douta,
144            doutb => doutb,
145            ena => ena,
146            enb => enb,
147            wea => wea,
148            web => web);
149-- synthesis translate_on
150
151END dual_port_block_memory_virtex2p_6_3_25371f622c89ba44_a;
152
Note: See TracBrowser for help on using the repository browser.