1 | -------------------------------------------------------------------------------- |
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2 | -- This file is owned and controlled by Xilinx and must be used -- |
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3 | -- solely for design, simulation, implementation and creation of -- |
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4 | -- design files limited to Xilinx devices or technologies. Use -- |
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5 | -- with non-Xilinx devices or technologies is expressly prohibited -- |
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6 | -- and immediately terminates your license. -- |
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7 | -- -- |
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8 | -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- |
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9 | -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- |
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10 | -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- |
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11 | -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- |
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12 | -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- |
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13 | -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- |
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14 | -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- |
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15 | -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- |
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16 | -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- |
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17 | -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- |
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18 | -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- |
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19 | -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- |
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20 | -- FOR A PARTICULAR PURPOSE. -- |
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21 | -- -- |
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22 | -- Xilinx products are not intended for use in life support -- |
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23 | -- appliances, devices, or systems. Use in such applications are -- |
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24 | -- expressly prohibited. -- |
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25 | -- -- |
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26 | -- (c) Copyright 1995-2007 Xilinx, Inc. -- |
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27 | -- All rights reserved. -- |
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28 | -------------------------------------------------------------------------------- |
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29 | -- You must compile the wrapper file dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8.vhd when simulating |
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30 | -- the core, dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8. When compiling the wrapper file, be sure to |
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31 | -- reference the XilinxCoreLib VHDL simulation library. For detailed |
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32 | -- instructions, please refer to the "CORE Generator Help". |
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33 | |
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34 | -- The synthesis directives "translate_off/translate_on" specified |
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35 | -- below are supported by Xilinx, Mentor Graphics and Synplicity |
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36 | -- synthesis tools. Ensure they are correct for your synthesis tool(s). |
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37 | |
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38 | LIBRARY ieee; |
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39 | USE ieee.std_logic_1164.ALL; |
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40 | -- synthesis translate_off |
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41 | Library XilinxCoreLib; |
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42 | -- synthesis translate_on |
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43 | ENTITY dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 IS |
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44 | port ( |
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45 | addra: IN std_logic_VECTOR(7 downto 0); |
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46 | addrb: IN std_logic_VECTOR(7 downto 0); |
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47 | clka: IN std_logic; |
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48 | clkb: IN std_logic; |
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49 | dina: IN std_logic_VECTOR(31 downto 0); |
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50 | dinb: IN std_logic_VECTOR(31 downto 0); |
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51 | douta: OUT std_logic_VECTOR(31 downto 0); |
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52 | doutb: OUT std_logic_VECTOR(31 downto 0); |
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53 | ena: IN std_logic; |
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54 | enb: IN std_logic; |
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55 | wea: IN std_logic; |
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56 | web: IN std_logic); |
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57 | END dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8; |
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58 | |
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59 | ARCHITECTURE dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8_a OF dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 IS |
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60 | -- synthesis translate_off |
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61 | component wrapped_dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 |
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62 | port ( |
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63 | addra: IN std_logic_VECTOR(7 downto 0); |
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64 | addrb: IN std_logic_VECTOR(7 downto 0); |
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65 | clka: IN std_logic; |
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66 | clkb: IN std_logic; |
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67 | dina: IN std_logic_VECTOR(31 downto 0); |
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68 | dinb: IN std_logic_VECTOR(31 downto 0); |
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69 | douta: OUT std_logic_VECTOR(31 downto 0); |
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70 | doutb: OUT std_logic_VECTOR(31 downto 0); |
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71 | ena: IN std_logic; |
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72 | enb: IN std_logic; |
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73 | wea: IN std_logic; |
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74 | web: IN std_logic); |
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75 | end component; |
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76 | |
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77 | -- Configuration specification |
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78 | for all : wrapped_dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 use entity XilinxCoreLib.blkmemdp_v6_3(behavioral) |
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79 | generic map( |
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80 | c_reg_inputsb => 0, |
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81 | c_reg_inputsa => 0, |
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82 | c_has_ndb => 0, |
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83 | c_has_nda => 0, |
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84 | c_ytop_addr => "1024", |
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85 | c_has_rfdb => 0, |
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86 | c_has_rfda => 0, |
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87 | c_ywea_is_high => 1, |
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88 | c_yena_is_high => 1, |
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89 | c_yclka_is_rising => 1, |
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90 | c_yhierarchy => "hierarchy1", |
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91 | c_ysinita_is_high => 1, |
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92 | c_ybottom_addr => "0", |
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93 | c_width_b => 32, |
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94 | c_width_a => 32, |
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95 | c_sinita_value => "0", |
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96 | c_sinitb_value => "0", |
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97 | c_limit_data_pitch => 18, |
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98 | c_write_modeb => 0, |
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99 | c_write_modea => 0, |
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100 | c_has_rdyb => 0, |
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101 | c_yuse_single_primitive => 0, |
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102 | c_has_rdya => 0, |
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103 | c_addra_width => 8, |
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104 | c_addrb_width => 8, |
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105 | c_has_limit_data_pitch => 0, |
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106 | c_default_data => "0", |
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107 | c_pipe_stages_b => 0, |
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108 | c_yweb_is_high => 1, |
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109 | c_yenb_is_high => 1, |
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110 | c_pipe_stages_a => 0, |
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111 | c_yclkb_is_rising => 1, |
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112 | c_yydisable_warnings => 1, |
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113 | c_enable_rlocs => 0, |
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114 | c_ysinitb_is_high => 1, |
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115 | c_has_web => 1, |
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116 | c_has_default_data => 0, |
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117 | c_has_sinitb => 0, |
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118 | c_has_wea => 1, |
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119 | c_has_sinita => 0, |
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120 | c_has_dinb => 1, |
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121 | c_has_dina => 1, |
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122 | c_ymake_bmm => 0, |
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123 | c_sim_collision_check => "NONE", |
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124 | c_has_enb => 1, |
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125 | c_has_ena => 1, |
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126 | c_mem_init_file => "dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8.mif", |
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127 | c_depth_b => 256, |
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128 | c_depth_a => 256, |
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129 | c_has_doutb => 1, |
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130 | c_has_douta => 1, |
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131 | c_yprimitive_type => "16kx1"); |
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132 | -- synthesis translate_on |
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133 | BEGIN |
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134 | -- synthesis translate_off |
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135 | U0 : wrapped_dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8 |
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136 | port map ( |
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137 | addra => addra, |
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138 | addrb => addrb, |
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139 | clka => clka, |
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140 | clkb => clkb, |
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141 | dina => dina, |
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142 | dinb => dinb, |
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143 | douta => douta, |
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144 | doutb => doutb, |
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145 | ena => ena, |
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146 | enb => enb, |
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147 | wea => wea, |
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148 | web => web); |
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149 | -- synthesis translate_on |
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150 | |
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151 | END dual_port_block_memory_virtex2p_6_3_fb7cc8c2a7e578f8_a; |
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152 | |
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