source: PlatformSupport/Deprecated/pcores/user_io_board_controller_plbw_v1_01_a/hdl/vhdl/user_io_board_controller_plbw.vhd

Last change on this file was 1051, checked in by murphpo, 16 years ago

Updated LCD controller with line/character offsets
File size: 14.5 KB
Line 
1-------------------------------------------------------------------
2-- System Generator version 10.1.00 VHDL source file.
3--
4-- Copyright(C) 2007 by Xilinx, Inc.  All rights reserved.  This
5-- text/file contains proprietary, confidential information of Xilinx,
6-- Inc., is distributed under license from Xilinx, Inc., and may be used,
7-- copied and/or disclosed only pursuant to the terms of a valid license
8-- agreement with Xilinx, Inc.  Xilinx hereby grants you a license to use
9-- this text/file solely for design, simulation, implementation and
10-- creation of design files limited to Xilinx devices or technologies.
11-- Use with non-Xilinx devices or technologies is expressly prohibited
12-- and immediately terminates your license unless covered by a separate
13-- agreement.
14--
15-- Xilinx is providing this design, code, or information "as is" solely
16-- for use in developing programs and solutions for Xilinx devices.  By
17-- providing this design, code, or information as one possible
18-- implementation of this feature, application or standard, Xilinx is
19-- making no representation that this implementation is free from any
20-- claims of infringement.  You are responsible for obtaining any rights
21-- you may require for your implementation.  Xilinx expressly disclaims
22-- any warranty whatsoever with respect to the adequacy of the
23-- implementation, including but not limited to warranties of
24-- merchantability or fitness for a particular purpose.
25--
26-- Xilinx products are not intended for use in life support appliances,
27-- devices, or systems.  Use in such applications is expressly prohibited.
28--
29-- Any modifications that are made to the source code are done at the user's
30-- sole risk and will be unsupported.
31--
32-- This copyright and support notice must be retained as part of this
33-- text at all times.  (c) Copyright 1995-2007 Xilinx, Inc.  All rights
34-- reserved.
35-------------------------------------------------------------------
36library IEEE;
37use IEEE.std_logic_1164.all;
38
39entity plbaddrpref is
40    generic (
41        C_BASEADDR : std_logic_vector(31 downto 0) := X"80000000";
42        C_HIGHADDR : std_logic_vector(31 downto 0) := X"8000FFFF";
43        C_SPLB_DWIDTH         : integer range 32 to 128   := 32;
44        C_SPLB_NATIVE_DWIDTH  : integer range 32 to 32    := 32
45    );
46    port (
47        addrpref           : out std_logic_vector(15-1 downto 0);
48        sl_rddbus          : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
49        plb_wrdbus         : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);
50        sgsl_rddbus        : in  std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
51        sgplb_wrdbus       : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
52    );
53end plbaddrpref;
54
55architecture behavior of plbaddrpref is
56
57signal sl_rddbus_i            : std_logic_vector(0 to C_SPLB_DWIDTH-1);
58
59begin
60    addrpref <= C_BASEADDR(32-1 downto 17);
61
62-------------------------------------------------------------------------------
63-- Mux/Steer data/be's correctly for connect 32-bit slave to 128-bit plb
64-------------------------------------------------------------------------------
65GEN_128_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 128 generate
66begin
67    -----------------------------------------------------------------------
68    -- Map lower rd data to each quarter of the plb slave read bus
69    -----------------------------------------------------------------------
70    sl_rddbus_i(0 to 31)      <=  sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
71    sl_rddbus_i(32 to 63)     <=  sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
72    sl_rddbus_i(64 to 95)     <=  sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
73    sl_rddbus_i(96 to 127)    <=  sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
74end generate GEN_128_TO_32_SLAVE;
75
76-------------------------------------------------------------------------------
77-- Mux/Steer data/be's correctly for connect 32-bit slave to 64-bit plb
78-------------------------------------------------------------------------------
79GEN_64_TO_32_SLAVE : if C_SPLB_NATIVE_DWIDTH = 32 and C_SPLB_DWIDTH = 64 generate
80begin
81    ---------------------------------------------------------------------------       
82    -- Map lower rd data to upper and lower halves of plb slave read bus
83    ---------------------------------------------------------------------------       
84    sl_rddbus_i(0 to 31)      <=  sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
85    sl_rddbus_i(32 to 63)     <=  sgsl_rddbus(0 to C_SPLB_NATIVE_DWIDTH-1);
86end generate GEN_64_TO_32_SLAVE;
87
88-------------------------------------------------------------------------------
89-- IPIF DWidth = PLB DWidth
90-- If IPIF Slave Data width is equal to the PLB Bus Data Width
91-- Then BE and Read Data Bus map directly to eachother.
92-------------------------------------------------------------------------------
93GEN_FOR_EQUAL_SLAVE : if C_SPLB_NATIVE_DWIDTH = C_SPLB_DWIDTH generate
94    sl_rddbus_i    <= sgsl_rddbus;
95end generate GEN_FOR_EQUAL_SLAVE;
96
97    sl_rddbus       <= sl_rddbus_i;
98    sgplb_wrdbus    <= plb_wrdbus(0 to C_SPLB_NATIVE_DWIDTH-1);
99
100end behavior;
101library IEEE;
102use IEEE.std_logic_1164.all;
103use work.conv_pkg.all;
104
105entity user_io_board_controller_plbw is
106  generic (
107    C_BASEADDR: std_logic_vector(31 downto 0) := X"80000000";
108    C_HIGHADDR: std_logic_vector(31 downto 0) := X"80000FFF";
109    C_SPLB_DWIDTH: integer range 32 to 128 := 32;
110    C_SPLB_NATIVE_DWIDTH: integer range 32 to 32 := 32;
111    C_SPLB_AWIDTH: integer := 0;
112    C_SPLB_P2P: integer := 0;
113    C_SPLB_MID_WIDTH: integer := 0;
114    C_SPLB_NUM_MASTERS: integer := 0;
115    C_SPLB_SUPPORT_BURSTS: integer := 0;
116    C_MEMMAP_BUTTONS_BIG: integer := 0;
117    C_MEMMAP_BUTTONS_BIG_N_BITS: integer := 0;
118    C_MEMMAP_BUTTONS_BIG_BIN_PT: integer := 0;
119    C_MEMMAP_BUTTONS_SMALL: integer := 0;
120    C_MEMMAP_BUTTONS_SMALL_N_BITS: integer := 0;
121    C_MEMMAP_BUTTONS_SMALL_BIN_PT: integer := 0;
122    C_MEMMAP_DIP_SWITCH: integer := 0;
123    C_MEMMAP_DIP_SWITCH_N_BITS: integer := 0;
124    C_MEMMAP_DIP_SWITCH_BIN_PT: integer := 0;
125    C_MEMMAP_TRACKBALL: integer := 0;
126    C_MEMMAP_TRACKBALL_N_BITS: integer := 0;
127    C_MEMMAP_TRACKBALL_BIN_PT: integer := 0;
128    C_MEMMAP_BUZZER_DUTYCYCLE: integer := 0;
129    C_MEMMAP_BUZZER_DUTYCYCLE_N_BITS: integer := 0;
130    C_MEMMAP_BUZZER_DUTYCYCLE_BIN_PT: integer := 0;
131    C_MEMMAP_BUZZER_ENABLE: integer := 0;
132    C_MEMMAP_BUZZER_ENABLE_N_BITS: integer := 0;
133    C_MEMMAP_BUZZER_ENABLE_BIN_PT: integer := 0;
134    C_MEMMAP_BUZZER_PERIOD: integer := 0;
135    C_MEMMAP_BUZZER_PERIOD_N_BITS: integer := 0;
136    C_MEMMAP_BUZZER_PERIOD_BIN_PT: integer := 0;
137    C_MEMMAP_LCD_BACKGROUNDCOLOR: integer := 0;
138    C_MEMMAP_LCD_BACKGROUNDCOLOR_N_BITS: integer := 0;
139    C_MEMMAP_LCD_BACKGROUNDCOLOR_BIN_PT: integer := 0;
140    C_MEMMAP_LCD_CHARACTEROFFSET: integer := 0;
141    C_MEMMAP_LCD_CHARACTEROFFSET_N_BITS: integer := 0;
142    C_MEMMAP_LCD_CHARACTEROFFSET_BIN_PT: integer := 0;
143    C_MEMMAP_LCD_CHARACTERSSELECT: integer := 0;
144    C_MEMMAP_LCD_CHARACTERSSELECT_N_BITS: integer := 0;
145    C_MEMMAP_LCD_CHARACTERSSELECT_BIN_PT: integer := 0;
146    C_MEMMAP_LCD_COLSET: integer := 0;
147    C_MEMMAP_LCD_COLSET_N_BITS: integer := 0;
148    C_MEMMAP_LCD_COLSET_BIN_PT: integer := 0;
149    C_MEMMAP_LCD_CONFIGLOCATION: integer := 0;
150    C_MEMMAP_LCD_CONFIGLOCATION_N_BITS: integer := 0;
151    C_MEMMAP_LCD_CONFIGLOCATION_BIN_PT: integer := 0;
152    C_MEMMAP_LCD_DIVIDERSELECT: integer := 0;
153    C_MEMMAP_LCD_DIVIDERSELECT_N_BITS: integer := 0;
154    C_MEMMAP_LCD_DIVIDERSELECT_BIN_PT: integer := 0;
155    C_MEMMAP_LCD_FIRSTEND: integer := 0;
156    C_MEMMAP_LCD_FIRSTEND_N_BITS: integer := 0;
157    C_MEMMAP_LCD_FIRSTEND_BIN_PT: integer := 0;
158    C_MEMMAP_LCD_FIRSTSTART: integer := 0;
159    C_MEMMAP_LCD_FIRSTSTART_N_BITS: integer := 0;
160    C_MEMMAP_LCD_FIRSTSTART_BIN_PT: integer := 0;
161    C_MEMMAP_LCD_LINEOFFSET: integer := 0;
162    C_MEMMAP_LCD_LINEOFFSET_N_BITS: integer := 0;
163    C_MEMMAP_LCD_LINEOFFSET_BIN_PT: integer := 0;
164    C_MEMMAP_LCD_RAMWRITE: integer := 0;
165    C_MEMMAP_LCD_RAMWRITE_N_BITS: integer := 0;
166    C_MEMMAP_LCD_RAMWRITE_BIN_PT: integer := 0;
167    C_MEMMAP_LCD_RESET: integer := 0;
168    C_MEMMAP_LCD_RESET_N_BITS: integer := 0;
169    C_MEMMAP_LCD_RESET_BIN_PT: integer := 0;
170    C_MEMMAP_LCD_RESETLCD: integer := 0;
171    C_MEMMAP_LCD_RESETLCD_N_BITS: integer := 0;
172    C_MEMMAP_LCD_RESETLCD_BIN_PT: integer := 0;
173    C_MEMMAP_LCD_ROWSET: integer := 0;
174    C_MEMMAP_LCD_ROWSET_N_BITS: integer := 0;
175    C_MEMMAP_LCD_ROWSET_BIN_PT: integer := 0;
176    C_MEMMAP_LCD_SECONDEND: integer := 0;
177    C_MEMMAP_LCD_SECONDEND_N_BITS: integer := 0;
178    C_MEMMAP_LCD_SECONDEND_BIN_PT: integer := 0;
179    C_MEMMAP_LCD_SECONDSTART: integer := 0;
180    C_MEMMAP_LCD_SECONDSTART_N_BITS: integer := 0;
181    C_MEMMAP_LCD_SECONDSTART_BIN_PT: integer := 0;
182    C_MEMMAP_LCD_SEND: integer := 0;
183    C_MEMMAP_LCD_SEND_N_BITS: integer := 0;
184    C_MEMMAP_LCD_SEND_BIN_PT: integer := 0;
185    C_MEMMAP_LCD_TOTALCMDTRANSFER: integer := 0;
186    C_MEMMAP_LCD_TOTALCMDTRANSFER_N_BITS: integer := 0;
187    C_MEMMAP_LCD_TOTALCMDTRANSFER_BIN_PT: integer := 0;
188    C_MEMMAP_LEDS: integer := 0;
189    C_MEMMAP_LEDS_N_BITS: integer := 0;
190    C_MEMMAP_LEDS_BIN_PT: integer := 0;
191    C_MEMMAP_LCD_CHARACTERMAP: integer := 0;
192    C_MEMMAP_LCD_CHARACTERMAP_N_BITS: integer := 0;
193    C_MEMMAP_LCD_CHARACTERMAP_BIN_PT: integer := 0;
194    C_MEMMAP_LCD_CHARACTERS: integer := 0;
195    C_MEMMAP_LCD_CHARACTERS_N_BITS: integer := 0;
196    C_MEMMAP_LCD_CHARACTERS_BIN_PT: integer := 0;
197    C_MEMMAP_LCD_COMMANDS: integer := 0;
198    C_MEMMAP_LCD_COMMANDS_N_BITS: integer := 0;
199    C_MEMMAP_LCD_COMMANDS_BIN_PT: integer := 0
200  );
201  port (
202    buttons_big: in std_logic_vector(0 to 1); 
203    buttons_small: in std_logic_vector(0 to 5); 
204    ce: in std_logic; 
205    dip_switch: in std_logic_vector(0 to 3); 
206    plb_abus: in std_logic_vector(0 to 31); 
207    plb_pavalid: in std_logic; 
208    plb_rnw: in std_logic; 
209    plb_wrdbus: in std_logic_vector(0 to C_SPLB_DWIDTH-1); 
210    reset: in std_logic; 
211    splb_clk: in std_logic; 
212    splb_rst: in std_logic; 
213    trackball_ox: in std_logic; 
214    trackball_oxn: in std_logic; 
215    trackball_oy: in std_logic; 
216    trackball_oyn: in std_logic; 
217    trackball_sel2: in std_logic; 
218    buzzer: out std_logic; 
219    cs: out std_logic; 
220    leds: out std_logic_vector(0 to 7); 
221    resetlcd: out std_logic; 
222    scl: out std_logic; 
223    sdi: out std_logic; 
224    sl_addrack: out std_logic; 
225    sl_rdcomp: out std_logic; 
226    sl_rddack: out std_logic; 
227    sl_rddbus: out std_logic_vector(0 to C_SPLB_DWIDTH-1); 
228    sl_wait: out std_logic; 
229    sl_wrcomp: out std_logic; 
230    sl_wrdack: out std_logic; 
231    trackball_sel1: out std_logic; 
232    trackball_xscn: out std_logic; 
233    trackball_yscn: out std_logic
234  );
235end user_io_board_controller_plbw;
236
237architecture structural of user_io_board_controller_plbw is
238  signal buttons_big_x0: std_logic_vector(1 downto 0);
239  signal buttons_small_x0: std_logic_vector(5 downto 0);
240  signal buzzer_x0: std_logic;
241  signal ce_x0: std_logic;
242  signal clk: std_logic;
243  signal cs_x0: std_logic;
244  signal dip_switch_x0: std_logic_vector(3 downto 0);
245  signal leds_x0: std_logic_vector(7 downto 0);
246  signal plb_abus_x0: std_logic_vector(31 downto 0);
247  signal plb_pavalid_x0: std_logic;
248  signal plb_rnw_x0: std_logic;
249  signal plbaddrpref_addrpref_net: std_logic_vector(14 downto 0);
250  signal plbaddrpref_plb_wrdbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
251  signal plbaddrpref_sgplb_wrdbus_net: std_logic_vector(31 downto 0);
252  signal plbaddrpref_sgsl_rddbus_net: std_logic_vector(31 downto 0);
253  signal plbaddrpref_sl_rddbus_net: std_logic_vector(C_SPLB_DWIDTH-1 downto 0);
254  signal reset_x0: std_logic;
255  signal resetlcd_x0: std_logic;
256  signal scl_x0: std_logic;
257  signal sdi_x0: std_logic;
258  signal sl_addrack_x0: std_logic;
259  signal sl_rdcomp_x0: std_logic;
260  signal sl_rddack_x0: std_logic;
261  signal sl_wait_x0: std_logic;
262  signal sl_wrcomp_x0: std_logic;
263  signal sl_wrdack_x0: std_logic;
264  signal splb_rst_x0: std_logic;
265  signal trackball_ox_x0: std_logic;
266  signal trackball_oxn_x0: std_logic;
267  signal trackball_oy_x0: std_logic;
268  signal trackball_oyn_x0: std_logic;
269  signal trackball_sel1_x0: std_logic;
270  signal trackball_sel2_x0: std_logic;
271  signal trackball_xscn_x0: std_logic;
272  signal trackball_yscn_x0: std_logic;
273
274begin
275  buttons_big_x0 <= buttons_big;
276  buttons_small_x0 <= buttons_small;
277  ce_x0 <= ce;
278  dip_switch_x0 <= dip_switch;
279  plb_abus_x0 <= plb_abus;
280  plb_pavalid_x0 <= plb_pavalid;
281  plb_rnw_x0 <= plb_rnw;
282  plbaddrpref_plb_wrdbus_net <= plb_wrdbus;
283  reset_x0 <= reset;
284  clk <= splb_clk;
285  splb_rst_x0 <= splb_rst;
286  trackball_ox_x0 <= trackball_ox;
287  trackball_oxn_x0 <= trackball_oxn;
288  trackball_oy_x0 <= trackball_oy;
289  trackball_oyn_x0 <= trackball_oyn;
290  trackball_sel2_x0 <= trackball_sel2;
291  buzzer <= buzzer_x0;
292  cs <= cs_x0;
293  leds <= leds_x0;
294  resetlcd <= resetlcd_x0;
295  scl <= scl_x0;
296  sdi <= sdi_x0;
297  sl_addrack <= sl_addrack_x0;
298  sl_rdcomp <= sl_rdcomp_x0;
299  sl_rddack <= sl_rddack_x0;
300  sl_rddbus <= plbaddrpref_sl_rddbus_net;
301  sl_wait <= sl_wait_x0;
302  sl_wrcomp <= sl_wrcomp_x0;
303  sl_wrdack <= sl_wrdack_x0;
304  trackball_sel1 <= trackball_sel1_x0;
305  trackball_xscn <= trackball_xscn_x0;
306  trackball_yscn <= trackball_yscn_x0;
307
308  plbaddrpref_x0: entity work.plbaddrpref
309    generic map (
310      C_BASEADDR => C_BASEADDR,
311      C_HIGHADDR => C_HIGHADDR,
312      C_SPLB_DWIDTH => C_SPLB_DWIDTH,
313      C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH
314    )
315    port map (
316      plb_wrdbus => plbaddrpref_plb_wrdbus_net,
317      sgsl_rddbus => plbaddrpref_sgsl_rddbus_net,
318      addrpref => plbaddrpref_addrpref_net,
319      sgplb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
320      sl_rddbus => plbaddrpref_sl_rddbus_net
321    );
322
323  sysgen_dut: entity work.user_io_board_controller_cw
324    port map (
325      buttons_big => buttons_big_x0,
326      buttons_small => buttons_small_x0,
327      ce => ce_x0,
328      clk => clk,
329      dip_switch => dip_switch_x0,
330      plb_abus => plb_abus_x0,
331      plb_pavalid => plb_pavalid_x0,
332      plb_rnw => plb_rnw_x0,
333      plb_wrdbus => plbaddrpref_sgplb_wrdbus_net,
334      reset => reset_x0,
335      sg_plb_addrpref => plbaddrpref_addrpref_net,
336      splb_rst => splb_rst_x0,
337      trackball_ox => trackball_ox_x0,
338      trackball_oxn => trackball_oxn_x0,
339      trackball_oy => trackball_oy_x0,
340      trackball_oyn => trackball_oyn_x0,
341      trackball_sel2 => trackball_sel2_x0,
342      buzzer => buzzer_x0,
343      cs => cs_x0,
344      leds => leds_x0,
345      resetlcd => resetlcd_x0,
346      scl => scl_x0,
347      sdi => sdi_x0,
348      sl_addrack => sl_addrack_x0,
349      sl_rdcomp => sl_rdcomp_x0,
350      sl_rddack => sl_rddack_x0,
351      sl_rddbus => plbaddrpref_sgsl_rddbus_net,
352      sl_wait => sl_wait_x0,
353      sl_wrcomp => sl_wrcomp_x0,
354      sl_wrdack => sl_wrdack_x0,
355      trackball_sel1 => trackball_sel1_x0,
356      trackball_xscn => trackball_xscn_x0,
357      trackball_yscn => trackball_yscn_x0
358    );
359
360end structural;
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