source: PlatformSupport/Deprecated/pcores/user_io_board_controller_plbw_v1_01_a/netlist/binary_counter_virtex2p_7_0_a22528b4c55dc1cd.edn

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2008 8 2 22 17 15)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 10.1.02; Cores Update # 2"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2007 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_count_mode = 0 ")
       (comment "c_load_enable = true ")
       (comment "c_has_aset = false ")
       (comment "c_load_low = false ")
       (comment "c_count_to = 1111111111111111 ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_iv = false ")
       (comment "c_restrict_count = false ")
       (comment "c_has_sclr = false ")
       (comment "c_width = 14 ")
       (comment "c_has_q_thresh1 = false ")
       (comment "c_enable_rlocs = false ")
       (comment "c_has_q_thresh0 = false ")
       (comment "c_thresh1_value = 1111111111111111 ")
       (comment "c_has_load = false ")
       (comment "c_thresh_early = true ")
       (comment "c_has_up = false ")
       (comment "c_has_thresh1 = false ")
       (comment "c_has_thresh0 = false ")
       (comment "c_ainit_val = 11111111111111 ")
       (comment "c_has_ce = true ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_family = virtex2p ")
       (comment "InstanceName = binary_counter_virtex2p_7_0_a22528b4c55dc1cd ")
       (comment "c_has_aclr = false ")
       (comment "c_sync_enable = 0 ")
       (comment "c_has_ainit = false ")
       (comment "c_sinit_val = 11111111111111 ")
       (comment "c_has_sset = false ")
       (comment "c_has_sinit = true ")
       (comment "c_count_by = 0001 ")
       (comment "c_has_l = false ")
       (comment "c_thresh0_value = 1111111111111111 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDSE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port S (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell binary_counter_virtex2p_7_0_a22528b4c55dc1cd
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename CLK "CLK") (direction INPUT))
   (port ( rename CE "CE") (direction INPUT))
   (port ( rename SINIT "SINIT") (direction INPUT))
   (port ( array ( rename Q "Q(13:0)") 14 ) (direction OUTPUT))
   )
  (contents
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      (property INIT (string "aaaa"))
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      (property INIT (string "aaaa"))
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      (property INIT (string "aaaa"))
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   (instance BU53
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   )
   (instance BU54
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   (instance BU56
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      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "aaaa"))
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   (instance BU59
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   (instance BU60
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   (instance BU64
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      (property INIT (string "aaaa"))
   )
   (instance BU65
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
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   (instance BU66
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   (instance BU68
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
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   (instance BU70
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "aaaa"))
   )
   (instance BU71
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
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   (instance BU72
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   (instance BU74
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   (instance BU76
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      (property INIT (string "aaaa"))
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   (instance BU77
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   (instance BU78
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   (instance BU80
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
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   (instance BU82
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property INIT (string "aaaa"))
   )
   (instance BU83
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
   )
   (instance BU85
      (viewRef view_1 (cellRef FDSE (libraryRef xilinxun)))
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   (net N0
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      (portRef CI (instanceRef BU6))
      (portRef I1 (instanceRef BU4))
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   (net (rename N2 "Q(0)")
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      (portRef (member Q 13))
      (portRef DI (instanceRef BU5))
      (portRef I0 (instanceRef BU4))
      (portRef Q (instanceRef BU8))
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   (net (rename N3 "Q(1)")
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      (portRef (member Q 12))
      (portRef DI (instanceRef BU11))
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      (portRef Q (instanceRef BU14))
    )
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   (net (rename N4 "Q(2)")
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      (portRef (member Q 11))
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      (portRef Q (instanceRef BU20))
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   (net (rename N5 "Q(3)")
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      (portRef (member Q 10))
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      (portRef Q (instanceRef BU26))
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      (portRef (member Q 9))
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      (portRef (member Q 8))
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   (net (rename N8 "Q(6)")
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      (portRef (member Q 7))
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      (portRef (member Q 6))
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      (portRef (member Q 5))
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      (portRef (member Q 4))
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    (joined
      (portRef (member Q 3))
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      (portRef Q (instanceRef BU68))
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   (net (rename N13 "Q(11)")
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      (portRef (member Q 2))
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      (portRef Q (instanceRef BU74))
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      (portRef (member Q 1))
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   (net (rename N15 "Q(13)")
    (joined
      (portRef (member Q 0))
      (portRef I0 (instanceRef BU82))
      (portRef Q (instanceRef BU85))
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   )
   (net (rename N16 "CLK")
    (joined
      (portRef CLK)
      (portRef C (instanceRef BU8))
      (portRef C (instanceRef BU14))
      (portRef C (instanceRef BU20))
      (portRef C (instanceRef BU26))
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      (portRef CE)
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   (net N27
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    (joined
      (portRef S (instanceRef BU65))
      (portRef LI (instanceRef BU66))
      (portRef O (instanceRef BU64))
    )
   )
   (net N85
    (joined
      (portRef O (instanceRef BU65))
      (portRef CI (instanceRef BU71))
      (portRef CI (instanceRef BU72))
    )
   )
   (net N88
    (joined
      (portRef S (instanceRef BU71))
      (portRef LI (instanceRef BU72))
      (portRef O (instanceRef BU70))
    )
   )
   (net N90
    (joined
      (portRef O (instanceRef BU71))
      (portRef CI (instanceRef BU77))
      (portRef CI (instanceRef BU78))
    )
   )
   (net N93
    (joined
      (portRef S (instanceRef BU77))
      (portRef LI (instanceRef BU78))
      (portRef O (instanceRef BU76))
    )
   )
   (net N95
    (joined
      (portRef O (instanceRef BU77))
      (portRef CI (instanceRef BU83))
    )
   )
   (net N98
    (joined
      (portRef LI (instanceRef BU83))
      (portRef O (instanceRef BU82))
    )
   )
))))
(design binary_counter_virtex2p_7_0_a22528b4c55dc1cd (cellRef binary_counter_virtex2p_7_0_a22528b4c55dc1cd (libraryRef test_lib))
  (property X_CORE_INFO (string "C_COUNTER_BINARY_V7_0, Xilinx CORE Generator 10.1.02_ip2"))
  (property PART (string "xc2vp2-fg256-7") (owner "Xilinx"))
))