1 | (edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) |
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2 | (status (written (timeStamp 2008 8 2 22 17 28) |
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3 | (author "Xilinx, Inc.") |
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4 | (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 10.1.02; Cores Update # 2")))) |
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5 | (comment " |
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6 | This file is owned and controlled by Xilinx and must be used |
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7 | solely for design, simulation, implementation and creation of |
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8 | design files limited to Xilinx devices or technologies. Use |
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9 | with non-Xilinx devices or technologies is expressly prohibited |
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10 | and immediately terminates your license. |
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11 | |
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12 | XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS' |
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13 | SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR |
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14 | XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION |
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15 | AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION |
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16 | OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS |
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17 | IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, |
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18 | AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE |
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19 | FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY |
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20 | WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE |
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21 | IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
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22 | REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF |
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23 | INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
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24 | FOR A PARTICULAR PURPOSE. |
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25 | |
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26 | Xilinx products are not intended for use in life support |
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27 | appliances, devices, or systems. Use in such applications are |
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28 | expressly prohibited. |
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29 | |
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30 | (c) Copyright 1995-2007 Xilinx, Inc. |
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31 | All rights reserved. |
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32 | |
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33 | ") |
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34 | (comment "Core parameters: ") |
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35 | (comment "c_count_mode = 0 ") |
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36 | (comment "c_load_enable = true ") |
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37 | (comment "c_has_aset = false ") |
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38 | (comment "c_load_low = false ") |
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39 | (comment "c_count_to = 1111111111111111 ") |
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40 | (comment "c_sync_priority = 1 ") |
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41 | (comment "c_has_iv = false ") |
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42 | (comment "c_restrict_count = false ") |
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43 | (comment "c_has_sclr = false ") |
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44 | (comment "c_width = 3 ") |
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45 | (comment "c_has_q_thresh1 = false ") |
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46 | (comment "c_enable_rlocs = false ") |
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47 | (comment "c_has_q_thresh0 = false ") |
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48 | (comment "c_thresh1_value = 1111111111111111 ") |
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49 | (comment "c_has_load = true ") |
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50 | (comment "c_thresh_early = true ") |
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51 | (comment "c_has_up = false ") |
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52 | (comment "c_has_thresh1 = false ") |
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53 | (comment "c_has_thresh0 = false ") |
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54 | (comment "c_ainit_val = 000 ") |
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55 | (comment "c_has_ce = true ") |
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56 | (comment "c_pipe_stages = 0 ") |
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57 | (comment "c_family = virtex2p ") |
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58 | (comment "InstanceName = binary_counter_virtex2p_7_0_b511f9871581ee23 ") |
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59 | (comment "c_has_aclr = false ") |
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60 | (comment "c_sync_enable = 0 ") |
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61 | (comment "c_has_ainit = false ") |
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62 | (comment "c_sinit_val = 000 ") |
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63 | (comment "c_has_sset = false ") |
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64 | (comment "c_has_sinit = true ") |
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65 | (comment "c_count_by = 001 ") |
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66 | (comment "c_has_l = true ") |
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67 | (comment "c_thresh0_value = 1111111111111111 ") |
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68 | (external xilinxun (edifLevel 0) |
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69 | (technology (numberDefinition)) |
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70 | (cell VCC (cellType GENERIC) |
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71 | (view view_1 (viewType NETLIST) |
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72 | (interface |
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73 | (port P (direction OUTPUT)) |
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74 | ) |
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75 | ) |
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76 | ) |
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77 | (cell GND (cellType GENERIC) |
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78 | (view view_1 (viewType NETLIST) |
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79 | (interface |
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80 | (port G (direction OUTPUT)) |
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81 | ) |
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82 | ) |
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83 | ) |
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84 | (cell FDRE (cellType GENERIC) |
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85 | (view view_1 (viewType NETLIST) |
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86 | (interface |
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87 | (port D (direction INPUT)) |
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88 | (port C (direction INPUT)) |
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89 | (port CE (direction INPUT)) |
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90 | (port R (direction INPUT)) |
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91 | (port Q (direction OUTPUT)) |
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92 | ) |
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93 | ) |
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94 | ) |
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95 | (cell LUT4 (cellType GENERIC) |
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96 | (view view_1 (viewType NETLIST) |
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97 | (interface |
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98 | (port I0 (direction INPUT)) |
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99 | (port I1 (direction INPUT)) |
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100 | (port I2 (direction INPUT)) |
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101 | (port I3 (direction INPUT)) |
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102 | (port O (direction OUTPUT)) |
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103 | ) |
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104 | ) |
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105 | ) |
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106 | (cell MULT_AND (cellType GENERIC) |
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107 | (view view_1 (viewType NETLIST) |
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108 | (interface |
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109 | (port I1 (direction INPUT)) |
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110 | (port I0 (direction INPUT)) |
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111 | (port LO (direction OUTPUT)) |
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112 | ) |
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113 | ) |
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114 | ) |
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115 | (cell MUXCY (cellType GENERIC) |
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116 | (view view_1 (viewType NETLIST) |
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117 | (interface |
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118 | (port DI (direction INPUT)) |
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119 | (port CI (direction INPUT)) |
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120 | (port S (direction INPUT)) |
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121 | (port O (direction OUTPUT)) |
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122 | ) |
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123 | ) |
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124 | ) |
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125 | (cell XORCY (cellType GENERIC) |
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126 | (view view_1 (viewType NETLIST) |
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127 | (interface |
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128 | (port LI (direction INPUT)) |
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129 | (port CI (direction INPUT)) |
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130 | (port O (direction OUTPUT)) |
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131 | ) |
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132 | ) |
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133 | ) |
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134 | ) |
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135 | (library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time)))) |
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136 | (cell binary_counter_virtex2p_7_0_b511f9871581ee23 |
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137 | (cellType GENERIC) (view view_1 (viewType NETLIST) |
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138 | (interface |
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139 | (port ( rename CLK "CLK") (direction INPUT)) |
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140 | (port ( rename LOAD "LOAD") (direction INPUT)) |
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141 | (port ( array ( rename L "L(2:0)") 3 ) (direction INPUT)) |
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142 | (port ( rename CE "CE") (direction INPUT)) |
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143 | (port ( rename SINIT "SINIT") (direction INPUT)) |
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144 | (port ( array ( rename Q "Q(2:0)") 3 ) (direction OUTPUT)) |
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145 | ) |
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146 | (contents |
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147 | (instance VCC (viewRef view_1 (cellRef VCC (libraryRef xilinxun)))) |
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148 | (instance GND (viewRef view_1 (cellRef GND (libraryRef xilinxun)))) |
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149 | (instance BU4 |
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150 | (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun))) |
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151 | (property INIT (string "5555")) |
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152 | ) |
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153 | (instance BU6 |
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154 | (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun))) |
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155 | (property INIT (string "7474")) |
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156 | ) |
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157 | (instance BU7 |
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158 | (viewRef view_1 (cellRef MULT_AND (libraryRef xilinxun))) |
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159 | ) |
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160 | (instance BU8 |
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161 | (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun))) |
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162 | ) |
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163 | (instance BU9 |
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164 | (viewRef view_1 (cellRef XORCY (libraryRef xilinxun))) |
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165 | ) |
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166 | (instance BU11 |
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167 | (viewRef view_1 (cellRef FDRE (libraryRef xilinxun))) |
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168 | ) |
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169 | (instance BU13 |
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170 | (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun))) |
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171 | (property INIT (string "b8b8")) |
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172 | ) |
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173 | (instance BU14 |
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174 | (viewRef view_1 (cellRef MULT_AND (libraryRef xilinxun))) |
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175 | ) |
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176 | (instance BU15 |
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177 | (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun))) |
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178 | ) |
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179 | (instance BU16 |
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180 | (viewRef view_1 (cellRef XORCY (libraryRef xilinxun))) |
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181 | ) |
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182 | (instance BU18 |
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183 | (viewRef view_1 (cellRef FDRE (libraryRef xilinxun))) |
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184 | ) |
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185 | (instance BU20 |
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186 | (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun))) |
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187 | (property INIT (string "b8b8")) |
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188 | ) |
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189 | (instance BU21 |
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190 | (viewRef view_1 (cellRef MULT_AND (libraryRef xilinxun))) |
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191 | ) |
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192 | (instance BU22 |
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193 | (viewRef view_1 (cellRef XORCY (libraryRef xilinxun))) |
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194 | ) |
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195 | (instance BU24 |
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196 | (viewRef view_1 (cellRef FDRE (libraryRef xilinxun))) |
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197 | ) |
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198 | (net N0 |
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199 | (joined |
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200 | (portRef G (instanceRef GND)) |
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201 | (portRef CI (instanceRef BU8)) |
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202 | (portRef CI (instanceRef BU9)) |
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203 | (portRef I1 (instanceRef BU4)) |
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204 | (portRef I2 (instanceRef BU4)) |
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205 | (portRef I3 (instanceRef BU4)) |
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206 | (portRef I3 (instanceRef BU6)) |
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207 | (portRef I3 (instanceRef BU13)) |
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208 | (portRef I3 (instanceRef BU20)) |
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209 | ) |
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210 | ) |
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211 | (net (rename N2 "Q(0)") |
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212 | (joined |
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213 | (portRef (member Q 2)) |
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214 | (portRef I1 (instanceRef BU7)) |
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215 | (portRef I0 (instanceRef BU6)) |
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216 | (portRef Q (instanceRef BU11)) |
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217 | ) |
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218 | ) |
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219 | (net (rename N3 "Q(1)") |
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220 | (joined |
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221 | (portRef (member Q 1)) |
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222 | (portRef I1 (instanceRef BU14)) |
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223 | (portRef I0 (instanceRef BU13)) |
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224 | (portRef Q (instanceRef BU18)) |
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225 | ) |
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226 | ) |
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227 | (net (rename N4 "Q(2)") |
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228 | (joined |
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229 | (portRef (member Q 0)) |
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230 | (portRef I1 (instanceRef BU21)) |
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231 | (portRef I0 (instanceRef BU20)) |
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232 | (portRef Q (instanceRef BU24)) |
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233 | ) |
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234 | ) |
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235 | (net (rename N5 "CLK") |
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236 | (joined |
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237 | (portRef CLK) |
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238 | (portRef C (instanceRef BU11)) |
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239 | (portRef C (instanceRef BU18)) |
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240 | (portRef C (instanceRef BU24)) |
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241 | ) |
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242 | ) |
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243 | (net (rename N6 "LOAD") |
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244 | (joined |
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245 | (portRef LOAD) |
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246 | (portRef I0 (instanceRef BU4)) |
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247 | ) |
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248 | ) |
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249 | (net (rename N7 "L(0)") |
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250 | (joined |
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251 | (portRef (member L 2)) |
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252 | (portRef I2 (instanceRef BU6)) |
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253 | ) |
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254 | ) |
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255 | (net (rename N8 "L(1)") |
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256 | (joined |
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257 | (portRef (member L 1)) |
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258 | (portRef I2 (instanceRef BU13)) |
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259 | ) |
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260 | ) |
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261 | (net (rename N9 "L(2)") |
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262 | (joined |
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263 | (portRef (member L 0)) |
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264 | (portRef I2 (instanceRef BU20)) |
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265 | ) |
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266 | ) |
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267 | (net (rename N10 "CE") |
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268 | (joined |
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269 | (portRef CE) |
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270 | (portRef CE (instanceRef BU11)) |
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271 | (portRef CE (instanceRef BU18)) |
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272 | (portRef CE (instanceRef BU24)) |
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273 | ) |
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274 | ) |
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275 | (net (rename N11 "SINIT") |
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276 | (joined |
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277 | (portRef SINIT) |
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278 | (portRef R (instanceRef BU11)) |
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279 | (portRef R (instanceRef BU18)) |
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280 | (portRef R (instanceRef BU24)) |
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281 | ) |
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282 | ) |
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283 | (net N12 |
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284 | (joined |
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285 | (portRef O (instanceRef BU9)) |
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286 | (portRef D (instanceRef BU11)) |
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287 | ) |
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288 | ) |
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289 | (net N13 |
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290 | (joined |
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291 | (portRef O (instanceRef BU16)) |
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292 | (portRef D (instanceRef BU18)) |
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293 | ) |
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294 | ) |
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295 | (net N14 |
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296 | (joined |
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297 | (portRef O (instanceRef BU22)) |
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298 | (portRef D (instanceRef BU24)) |
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299 | ) |
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300 | ) |
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301 | (net N15 |
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302 | (joined |
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303 | (portRef I0 (instanceRef BU7)) |
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304 | (portRef I0 (instanceRef BU14)) |
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305 | (portRef I0 (instanceRef BU21)) |
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306 | (portRef O (instanceRef BU4)) |
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307 | (portRef I1 (instanceRef BU6)) |
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308 | (portRef I1 (instanceRef BU13)) |
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309 | (portRef I1 (instanceRef BU20)) |
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310 | ) |
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311 | ) |
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312 | (net N16 |
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313 | (joined |
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314 | (portRef S (instanceRef BU8)) |
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315 | (portRef LI (instanceRef BU9)) |
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316 | (portRef O (instanceRef BU6)) |
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317 | ) |
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318 | ) |
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319 | (net N19 |
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320 | (joined |
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321 | (portRef LO (instanceRef BU7)) |
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322 | (portRef DI (instanceRef BU8)) |
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323 | ) |
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324 | ) |
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325 | (net N20 |
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326 | (joined |
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327 | (portRef O (instanceRef BU8)) |
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328 | (portRef CI (instanceRef BU15)) |
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329 | (portRef CI (instanceRef BU16)) |
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330 | ) |
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331 | ) |
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332 | (net N23 |
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333 | (joined |
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334 | (portRef S (instanceRef BU15)) |
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335 | (portRef LI (instanceRef BU16)) |
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336 | (portRef O (instanceRef BU13)) |
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337 | ) |
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338 | ) |
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339 | (net N26 |
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340 | (joined |
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341 | (portRef LO (instanceRef BU14)) |
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342 | (portRef DI (instanceRef BU15)) |
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343 | ) |
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344 | ) |
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345 | (net N27 |
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346 | (joined |
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347 | (portRef O (instanceRef BU15)) |
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348 | (portRef CI (instanceRef BU22)) |
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349 | ) |
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350 | ) |
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351 | (net N30 |
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352 | (joined |
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353 | (portRef LI (instanceRef BU22)) |
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354 | (portRef O (instanceRef BU20)) |
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355 | ) |
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356 | ) |
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357 | )))) |
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358 | (design binary_counter_virtex2p_7_0_b511f9871581ee23 (cellRef binary_counter_virtex2p_7_0_b511f9871581ee23 (libraryRef test_lib)) |
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359 | (property X_CORE_INFO (string "C_COUNTER_BINARY_V7_0, Xilinx CORE Generator 10.1.02_ip2")) |
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360 | (property PART (string "xc2vp2-fg256-7") (owner "Xilinx")) |
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361 | )) |
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