[1833] | 1 |
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| 2 | # ##############################################################################
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| 3 | # Template Project for WARP v3 Rev 1.1
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| 4 | # Family: virtex6
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| 5 | # Device: xc6vlx240t
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| 6 | # Package: ff1156
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| 7 | # Speed Grade: -2
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| 8 | # Processor number: 1
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| 9 | # Processor 1: microblaze_0
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| 10 | # Processor and primary bus clock frequency: 160.0 MHz
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| 11 | # Secondary bus clock frequency: 80.0 MHz
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| 12 | # ##############################################################################
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| 13 | PARAMETER VERSION = 2.1.0
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| 14 |
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| 15 |
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| 16 | # User IO (LEDs, buttons, etc.) pins
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| 17 | PORT USERIO_hexdisp_left_pin = USERIO_hexdisp_left_pin, DIR = O, VEC = [0:6]
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| 18 | PORT USERIO_hexdisp_right_pin = USERIO_hexdisp_right_pin, DIR = O, VEC = [0:6]
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| 19 | PORT USERIO_hexdisp_left_dp_pin = USERIO_hexdisp_left_dp_pin, DIR = O
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| 20 | PORT USERIO_hexdisp_right_dp_pin = USERIO_hexdisp_right_dp_pin, DIR = O
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| 21 | PORT USERIO_leds_red_pin = USERIO_leds_red_pin, DIR = O, VEC = [0:3]
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| 22 | PORT USERIO_leds_green_pin = USERIO_leds_green_pin, DIR = O, VEC = [0:3]
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| 23 | PORT USERIO_rfa_led_red_pin = USERIO_rfa_led_red_pin, DIR = O
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| 24 | PORT USERIO_rfa_led_green_pin = USERIO_rfa_led_green_pin, DIR = O
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| 25 | PORT USERIO_rfb_led_red_pin = USERIO_rfb_led_red_pin, DIR = O
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| 26 | PORT USERIO_rfb_led_green_pin = USERIO_rfb_led_green_pin, DIR = O
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| 27 | PORT USERIO_dipsw_pin = USERIO_dipsw_pin, DIR = I, VEC = [0:3]
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| 28 | PORT USERIO_pb_u_pin = USERIO_pb_u_pin, DIR = I
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| 29 | PORT USERIO_pb_m_pin = USERIO_pb_m_pin, DIR = I
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| 30 | PORT USERIO_pb_d_pin = USERIO_pb_d_pin, DIR = I
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| 31 | # USB UART transceiver pins
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| 32 | PORT UART_USB_RX_pin = UART_USB_RX_pin, DIR = I
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| 33 | PORT UART_USB_TX_pin = UART_USB_TX_pin, DIR = O
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| 34 | # IIC EEPROM pins
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| 35 | PORT IIC_EEPROM_iic_scl_pin = IIC_EEPROM_iic_scl_pin, DIR = IO
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| 36 | PORT IIC_EEPROM_iic_sda_pin = IIC_EEPROM_iic_sda_pin, DIR = IO
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| 37 | # AD9963 ADC/DAC control pins (RFA & RFB)
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| 38 | PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O
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| 39 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
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| 40 | PORT RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O
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| 41 | PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O
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| 42 | PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O
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| 43 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
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| 44 | PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O
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| 45 | PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O
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| 46 | # AD9512 clock buffer control pins (RF reference & sampling clocks)
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| 47 | PORT clk_rfref_spi_cs_n_pin = clk_rfref_spi_cs_n, DIR = O
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| 48 | PORT clk_rfref_spi_mosi_pin = clk_rfref_spi_mosi, DIR = O
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| 49 | PORT clk_rfref_spi_sclk_pin = clk_rfref_spi_sclk, DIR = O
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| 50 | PORT clk_rfref_spi_miso_pin = clk_rfref_spi_miso, DIR = I
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| 51 | PORT clk_rfref_func_pin = net_vcc, DIR = O
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| 52 | PORT clk_samp_spi_cs_n_pin = clk_samp_spi_cs_n, DIR = O
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| 53 | PORT clk_samp_spi_mosi_pin = clk_samp_spi_mosi, DIR = O
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| 54 | PORT clk_samp_spi_sclk_pin = clk_samp_spi_sclk, DIR = O
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| 55 | PORT clk_samp_spi_miso_pin = clk_samp_spi_miso, DIR = I
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| 56 | PORT clk_samp_func_pin = net_vcc, DIR = O
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| 57 | # RFA transceiver and front-end
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| 58 | PORT RFA_TxEn_pin = RFA_TxEn, DIR = O
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| 59 | PORT RFA_RxEn_pin = RFA_RxEn, DIR = O
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| 60 | PORT RFA_RxHP_pin = RFA_RxHP, DIR = O
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| 61 | PORT RFA_SHDN_pin = RFA_SHDN, DIR = O
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| 62 | PORT RFA_SPI_SCLK_pin = RFA_SPI_SCLK, DIR = O
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| 63 | PORT RFA_SPI_MOSI_pin = RFA_SPI_MOSI, DIR = O
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| 64 | PORT RFA_SPI_CSn_pin = RFA_SPI_CSn, DIR = O
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| 65 | PORT RFA_B_pin = RFA_B, DIR = O, VEC = [0:6]
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| 66 | PORT RFA_LD_pin = RFA_LD, DIR = I
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| 67 | PORT RFA_PAEn_24_pin = RFA_PAEn_24, DIR = O
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| 68 | PORT RFA_PAEn_5_pin = RFA_PAEn_5, DIR = O
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| 69 | PORT RFA_AntSw_pin = RFA_AntSw, DIR = O, VEC = [0:1]
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| 70 | # RFB transceiver and front-end
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| 71 | PORT RFB_TxEn_pin = RFB_TxEn, DIR = O
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| 72 | PORT RFB_RxEn_pin = RFB_RxEn, DIR = O
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| 73 | PORT RFB_RxHP_pin = RFB_RxHP, DIR = O
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| 74 | PORT RFB_SHDN_pin = RFB_SHDN, DIR = O
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| 75 | PORT RFB_SPI_SCLK_pin = RFB_SPI_SCLK, DIR = O
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| 76 | PORT RFB_SPI_MOSI_pin = RFB_SPI_MOSI, DIR = O
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| 77 | PORT RFB_SPI_CSn_pin = RFB_SPI_CSn, DIR = O
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| 78 | PORT RFB_B_pin = RFB_B, DIR = O, VEC = [0:6]
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| 79 | PORT RFB_LD_pin = RFB_LD, DIR = I
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| 80 | PORT RFB_PAEn_24_pin = RFB_PAEn_24, DIR = O
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| 81 | PORT RFB_PAEn_5_pin = RFB_PAEn_5, DIR = O
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| 82 | PORT RFB_AntSw_pin = RFB_AntSw, DIR = O, VEC = [0:1]
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| 83 | # RFA AD pins
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| 84 | PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
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| 85 | PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
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| 86 | PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
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| 87 | PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
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| 88 | PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
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| 89 | PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
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| 90 | # RFB AD pins
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| 91 | PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
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| 92 | PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
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| 93 | PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
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| 94 | PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
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| 95 | PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
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| 96 | PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
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| 97 | # RSSI ADC pins
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| 98 | PORT RFA_RSSI_D = warplab_radio1_rssi_D, DIR = I, VEC = [9:0]
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| 99 | PORT RFB_RSSI_D = warplab_radio2_rssi_D, DIR = I, VEC = [9:0]
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| 100 | PORT RF_RSSI_CLK = warplab_rssi_clk, DIR = O
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| 101 | PORT RF_RSSI_PD = net_gnd, DIR = O
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| 102 | # 80MHz sampling clock from AD9512
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| 103 | PORT samp_clk_p_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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| 104 | PORT samp_clk_n_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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| 105 | # 200MHz LVDS oscillator input
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| 106 | PORT osc200_p_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
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| 107 | PORT osc200_n_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
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| 108 | # System reset, tied to RESET push button
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| 109 | PORT rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
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| 110 |
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| 111 |
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| 112 | BEGIN microblaze
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| 113 | PARAMETER INSTANCE = microblaze_0
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| 114 | PARAMETER C_USE_BARREL = 1
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| 115 | PARAMETER C_DEBUG_ENABLED = 1
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| 116 | PARAMETER HW_VER = 8.20.b
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| 117 | PARAMETER C_USE_DIV = 1
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| 118 | PARAMETER C_UNALIGNED_EXCEPTIONS = 1
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| 119 | BUS_INTERFACE DPLB = plb_primary
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| 120 | BUS_INTERFACE IPLB = plb_primary
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| 121 | BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
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| 122 | BUS_INTERFACE DLMB = dlmb
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| 123 | BUS_INTERFACE ILMB = ilmb
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| 124 | PORT MB_RESET = mb_reset
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| 125 | END
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| 126 |
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| 127 | BEGIN plb_v46
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| 128 | PARAMETER INSTANCE = plb_primary
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| 129 | PARAMETER HW_VER = 1.05.a
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| 130 | PORT PLB_Clk = clk_160MHz
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| 131 | PORT SYS_Rst = sys_bus_reset
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| 132 | END
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| 133 |
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| 134 | BEGIN lmb_v10
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| 135 | PARAMETER INSTANCE = ilmb
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| 136 | PARAMETER HW_VER = 2.00.b
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| 137 | PORT LMB_Clk = clk_160MHz
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| 138 | PORT SYS_Rst = sys_bus_reset
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| 139 | END
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| 140 |
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| 141 | BEGIN lmb_v10
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| 142 | PARAMETER INSTANCE = dlmb
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| 143 | PARAMETER HW_VER = 2.00.b
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| 144 | PORT LMB_Clk = clk_160MHz
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| 145 | PORT SYS_Rst = sys_bus_reset
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| 146 | END
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| 147 |
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| 148 | BEGIN lmb_bram_if_cntlr
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| 149 | PARAMETER INSTANCE = dlmb_cntlr
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| 150 | PARAMETER HW_VER = 3.00.b
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| 151 | PARAMETER C_BASEADDR = 0x00000000
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| 152 | PARAMETER C_HIGHADDR = 0x0000ffff
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| 153 | BUS_INTERFACE SLMB = dlmb
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| 154 | BUS_INTERFACE BRAM_PORT = dlmb_port
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| 155 | END
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| 156 |
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| 157 | BEGIN lmb_bram_if_cntlr
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| 158 | PARAMETER INSTANCE = ilmb_cntlr
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| 159 | PARAMETER HW_VER = 3.00.b
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| 160 | PARAMETER C_BASEADDR = 0x00000000
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| 161 | PARAMETER C_HIGHADDR = 0x0000ffff
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| 162 | BUS_INTERFACE SLMB = ilmb
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| 163 | BUS_INTERFACE BRAM_PORT = ilmb_port
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| 164 | END
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| 165 |
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| 166 | BEGIN bram_block
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| 167 | PARAMETER INSTANCE = lmb_bram
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| 168 | PARAMETER HW_VER = 1.00.a
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| 169 | BUS_INTERFACE PORTA = ilmb_port
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| 170 | BUS_INTERFACE PORTB = dlmb_port
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| 171 | END
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| 172 |
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| 173 | BEGIN w3_userio
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| 174 | PARAMETER INSTANCE = w3_userio_0
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| 175 | PARAMETER HW_VER = 1.00.a
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| 176 | PARAMETER C_BASEADDR = 0xc8e00000
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| 177 | PARAMETER C_HIGHADDR = 0xc8e0ffff
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| 178 | BUS_INTERFACE SPLB = plb_primary
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| 179 | PORT hexdisp_left = USERIO_hexdisp_left_pin
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| 180 | PORT hexdisp_right = USERIO_hexdisp_right_pin
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| 181 | PORT hexdisp_left_dp = USERIO_hexdisp_left_dp_pin
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| 182 | PORT hexdisp_right_dp = USERIO_hexdisp_right_dp_pin
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| 183 | PORT leds_red = USERIO_leds_red_pin
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| 184 | PORT leds_green = USERIO_leds_green_pin
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| 185 | PORT rfa_led_red = USERIO_rfa_led_red_pin
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| 186 | PORT rfa_led_green = USERIO_rfa_led_green_pin
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| 187 | PORT rfb_led_red = USERIO_rfb_led_red_pin
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| 188 | PORT rfb_led_green = USERIO_rfb_led_green_pin
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| 189 | PORT dipsw = USERIO_dipsw_pin
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| 190 | PORT pb_u = USERIO_pb_u_pin
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| 191 | PORT pb_m = USERIO_pb_m_pin
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| 192 | PORT pb_d = USERIO_pb_d_pin
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| 193 | PORT usr_rfa_led_red = RFA_statLED_Rx
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| 194 | PORT usr_rfa_led_green = RFA_statLED_Tx
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| 195 | PORT usr_rfb_led_red = RFB_statLED_Rx
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| 196 | PORT usr_rfb_led_green = RFB_statLED_Tx
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| 197 | PORT DNA_Port_Clk = clk_40MHz
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| 198 | END
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| 199 |
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| 200 | BEGIN w3_iic_eeprom
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| 201 | PARAMETER INSTANCE = w3_iic_eeprom_0
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| 202 | PARAMETER HW_VER = 1.00.b
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| 203 | PARAMETER C_BASEADDR = 0xcbe00000
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| 204 | PARAMETER C_HIGHADDR = 0xcbe0ffff
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| 205 | BUS_INTERFACE SPLB = plb_primary
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| 206 | PORT iic_scl = IIC_EEPROM_iic_scl_pin
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| 207 | PORT iic_sda = IIC_EEPROM_iic_sda_pin
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| 208 | END
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| 209 |
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| 210 | BEGIN xps_uartlite
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| 211 | PARAMETER INSTANCE = UART_USB
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| 212 | PARAMETER C_BAUDRATE = 57600
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| 213 | PARAMETER C_DATA_BITS = 8
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| 214 | PARAMETER C_USE_PARITY = 0
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| 215 | PARAMETER C_ODD_PARITY = 0
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| 216 | PARAMETER HW_VER = 1.02.a
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| 217 | PARAMETER C_BASEADDR = 0x84000000
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| 218 | PARAMETER C_HIGHADDR = 0x8400ffff
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| 219 | BUS_INTERFACE SPLB = plb_primary
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| 220 | PORT RX = UART_USB_RX_pin
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| 221 | PORT TX = UART_USB_TX_pin
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| 222 | END
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| 223 |
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| 224 | BEGIN clock_generator
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| 225 | PARAMETER INSTANCE = clock_generator_ProcBusSamp_Clocks
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| 226 | PARAMETER C_EXT_RESET_HIGH = 1
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| 227 | PARAMETER HW_VER = 4.03.a
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| 228 | # 80MHz clock input (driven by AD9512 for sampling clock)
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| 229 | PARAMETER C_CLKIN_FREQ = 80000000
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| 230 | # 2x Sampling clock 0 deg phase
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| 231 | PARAMETER C_CLKOUT0_FREQ = 80000000
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| 232 | PARAMETER C_CLKOUT0_PHASE = 0
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| 233 | PARAMETER C_CLKOUT0_GROUP = MMCM0
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| 234 | PARAMETER C_CLKOUT0_BUF = TRUE
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| 235 | # MB and primary PLB
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| 236 | PARAMETER C_CLKOUT1_FREQ = 160000000
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| 237 | PARAMETER C_CLKOUT1_PHASE = 0
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| 238 | PARAMETER C_CLKOUT1_GROUP = MMCM0
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| 239 | PARAMETER C_CLKOUT1_BUF = TRUE
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| 240 | # Sampling clock 0 deg phase
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| 241 | PARAMETER C_CLKOUT2_FREQ = 40000000
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| 242 | PARAMETER C_CLKOUT2_PHASE = 0
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| 243 | PARAMETER C_CLKOUT2_GROUP = MMCM0
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| 244 | PARAMETER C_CLKOUT2_BUF = TRUE
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| 245 | # Sampling clock 90 deg phase
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| 246 | PARAMETER C_CLKOUT3_FREQ = 40000000
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| 247 | PARAMETER C_CLKOUT3_PHASE = 90
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| 248 | PARAMETER C_CLKOUT3_BUF = TRUE
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| 249 | PARAMETER C_CLKOUT3_GROUP = MMCM0
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| 250 | # IDELAYCTRL refclk
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| 251 | PARAMETER C_CLKOUT4_FREQ = 200000000
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| 252 | PARAMETER C_CLKOUT4_PHASE = 0
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| 253 | PARAMETER C_CLKOUT4_GROUP = NONE
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| 254 | PARAMETER C_CLKOUT4_BUF = TRUE
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| 255 | PORT CLKIN = ad_refclk_in
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| 256 | PORT CLKOUT0 = clk_80MHz
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| 257 | PORT CLKOUT1 = clk_160MHz
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| 258 | PORT CLKOUT2 = clk_40MHz
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| 259 | PORT CLKOUT3 = clk_40MHz_90degphase
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| 260 | PORT CLKOUT4 = clk_200MHz
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| 261 | PORT RST = sys_rst_s
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| 262 | PORT LOCKED = clk_gen_0_locked
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| 263 | END
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| 264 |
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| 265 | BEGIN mdm
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| 266 | PARAMETER INSTANCE = mdm_0
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| 267 | PARAMETER C_MB_DBG_PORTS = 1
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| 268 | PARAMETER C_USE_UART = 1
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| 269 | PARAMETER HW_VER = 2.00.b
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| 270 | PARAMETER C_BASEADDR = 0x84400000
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| 271 | PARAMETER C_HIGHADDR = 0x8440ffff
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| 272 | BUS_INTERFACE SPLB = plb_primary
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| 273 | BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
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| 274 | PORT Debug_SYS_Rst = Debug_SYS_Rst
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| 275 | END
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| 276 |
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| 277 | BEGIN proc_sys_reset
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| 278 | PARAMETER INSTANCE = proc_sys_reset_0
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| 279 | PARAMETER C_EXT_RESET_HIGH = 1
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| 280 | PARAMETER HW_VER = 3.00.a
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| 281 | PORT Slowest_sync_clk = clk_40MHz
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| 282 | PORT Ext_Reset_In = sys_rst_s
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| 283 | PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
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| 284 | PORT Dcm_locked = clk_gen_0_locked
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| 285 | PORT MB_Reset = mb_reset
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| 286 | PORT Bus_Struct_Reset = sys_bus_reset
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| 287 | END
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| 288 |
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| 289 | BEGIN bram_block
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| 290 | PARAMETER INSTANCE = bram_block_0
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| 291 | PARAMETER HW_VER = 1.00.a
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| 292 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
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| 293 | END
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| 294 |
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| 295 | BEGIN xps_bram_if_cntlr
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| 296 | PARAMETER INSTANCE = xps_bram_if_cntlr_0
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| 297 | PARAMETER HW_VER = 1.00.b
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| 298 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32
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| 299 | PARAMETER C_BASEADDR = 0x83820000
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| 300 | PARAMETER C_HIGHADDR = 0x8383ffff
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| 301 | BUS_INTERFACE SPLB = plb_primary
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| 302 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
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| 303 | END
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| 304 |
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| 305 | BEGIN bram_block
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| 306 | PARAMETER INSTANCE = bram_block_1
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| 307 | PARAMETER HW_VER = 1.00.a
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| 308 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
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| 309 | END
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| 310 |
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| 311 | BEGIN xps_bram_if_cntlr
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| 312 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
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| 313 | PARAMETER HW_VER = 1.00.b
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| 314 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32
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| 315 | PARAMETER C_BASEADDR = 0x83810000
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| 316 | PARAMETER C_HIGHADDR = 0x8381ffff
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| 317 | BUS_INTERFACE SPLB = plb_primary
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| 318 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
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| 319 | END
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| 320 |
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| 321 | BEGIN xps_timer
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| 322 | PARAMETER INSTANCE = xps_timer_0
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| 323 | PARAMETER HW_VER = 1.02.a
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| 324 | PARAMETER C_BASEADDR = 0x83c00000
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| 325 | PARAMETER C_HIGHADDR = 0x83c0ffff
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| 326 | BUS_INTERFACE SPLB = plb_secondary_80MHz
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| 327 | END
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| 328 |
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| 329 | # ###############
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| 330 | # WARP pcores
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| 331 | # ###############
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| 332 | BEGIN w3_clock_controller
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| 333 | PARAMETER INSTANCE = w3_clock_controller_0
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| 334 | PARAMETER HW_VER = 3.00.b
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| 335 | PARAMETER C_BASEADDR = 0xc0400000
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| 336 | PARAMETER C_HIGHADDR = 0xc040ffff
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| 337 | BUS_INTERFACE SPLB = plb_primary
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| 338 | PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
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| 339 | PORT samp_spi_cs_n = clk_samp_spi_cs_n
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| 340 | PORT samp_spi_mosi = clk_samp_spi_mosi
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| 341 | PORT rfref_spi_mosi = clk_rfref_spi_mosi
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| 342 | PORT samp_spi_sclk = clk_samp_spi_sclk
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| 343 | PORT rfref_spi_sclk = clk_rfref_spi_sclk
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| 344 | PORT samp_spi_miso = clk_samp_spi_miso
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| 345 | PORT rfref_spi_miso = clk_rfref_spi_miso
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| 346 | PORT usr_status = net_gnd
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| 347 | END
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| 348 |
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| 349 | BEGIN w3_ad_controller
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| 350 | PARAMETER INSTANCE = w3_ad_controller_0
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| 351 | PARAMETER HW_VER = 3.00.b
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| 352 | PARAMETER C_BASEADDR = 0xc6000000
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| 353 | PARAMETER C_HIGHADDR = 0xc600ffff
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| 354 | BUS_INTERFACE SPLB = plb_primary
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| 355 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
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| 356 | PORT RFB_AD_reset_n = RFB_AD_reset_n
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| 357 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
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| 358 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
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| 359 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
|
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| 360 | PORT RFA_AD_reset_n = RFA_AD_reset_n
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| 361 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
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| 362 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
|
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| 363 | END
|
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| 364 |
|
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| 365 | BEGIN radio_controller
|
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| 366 | PARAMETER INSTANCE = radio_controller_0
|
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| 367 | PARAMETER HW_VER = 3.00.b
|
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| 368 | PARAMETER C_BASEADDR = 0xcac00000
|
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| 369 | PARAMETER C_HIGHADDR = 0xcac0ffff
|
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| 370 | BUS_INTERFACE SPLB = plb_primary
|
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| 371 | PORT RFA_TxEn = RFA_TxEn
|
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| 372 | PORT RFA_RxEn = RFA_RxEn
|
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| 373 | PORT RFA_RxHP = RFA_RxHP
|
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| 374 | PORT RFA_SHDN = RFA_SHDN
|
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| 375 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
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| 376 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
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| 377 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
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| 378 | PORT RFA_B = RFA_B
|
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| 379 | PORT RFA_LD = RFA_LD
|
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| 380 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
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| 381 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
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| 382 | PORT RFA_AntSw = RFA_AntSw
|
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| 383 | PORT RFB_TxEn = RFB_TxEn
|
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| 384 | PORT RFB_RxEn = RFB_RxEn
|
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| 385 | PORT RFB_RxHP = RFB_RxHP
|
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| 386 | PORT RFB_SHDN = RFB_SHDN
|
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| 387 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
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| 388 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
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| 389 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
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| 390 | PORT RFB_B = RFB_B
|
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| 391 | PORT RFB_LD = RFB_LD
|
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| 392 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
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| 393 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
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| 394 | PORT RFB_AntSw = RFB_AntSw
|
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| 395 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
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| 396 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
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| 397 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
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| 398 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
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| 399 | END
|
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| 400 |
|
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| 401 | BEGIN w3_ad_bridge
|
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| 402 | PARAMETER INSTANCE = w3_ad_bridge_0
|
---|
| 403 | # include IDELAYCTRL, since TEMACs are gone
|
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| 404 | PARAMETER INCLUDE_IDELAYCTRL = 1
|
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| 405 | PARAMETER HW_VER = 3.00.g
|
---|
| 406 | # Clock ports (inputs to w3_ad_bridge)
|
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| 407 | PORT clk200 = clk_200MHz
|
---|
| 408 | PORT sys_samp_clk_Tx = clk_40MHz
|
---|
| 409 | PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
|
---|
| 410 | PORT sys_samp_clk_Rx = clk_40MHz
|
---|
| 411 | # Top-level AD9963 ports
|
---|
| 412 | PORT ad_RFA_TXD = rfa_txd
|
---|
| 413 | PORT ad_RFA_TXCLK = rfa_txclk
|
---|
| 414 | PORT ad_RFA_TXIQ = rfa_txiq
|
---|
| 415 | PORT ad_RFA_TRXD = rfa_trxd
|
---|
| 416 | PORT ad_RFA_TRXCLK = rfa_trxclk
|
---|
| 417 | PORT ad_RFA_TRXIQ = rfa_trxiq
|
---|
| 418 | PORT ad_RFB_TXD = rfb_txd
|
---|
| 419 | PORT ad_RFB_TXCLK = rfb_txclk
|
---|
| 420 | PORT ad_RFB_TXIQ = rfb_txiq
|
---|
| 421 | PORT ad_RFB_TRXD = rfb_trxd
|
---|
| 422 | PORT ad_RFB_TRXCLK = rfb_trxclk
|
---|
| 423 | PORT ad_RFB_TRXIQ = rfb_trxiq
|
---|
| 424 | # ####
|
---|
| 425 | # User ports - connect these to custom logic
|
---|
| 426 | # Each port is Fix12_11
|
---|
| 427 | # RFA Tx
|
---|
| 428 | PORT user_RFA_TXD_I = net_gnd
|
---|
| 429 | PORT user_RFA_TXD_Q = net_gnd
|
---|
| 430 | # RFB Tx
|
---|
| 431 | PORT user_RFB_TXD_I = net_gnd
|
---|
| 432 | PORT user_RFB_TXD_Q = net_gnd
|
---|
| 433 | END
|
---|
| 434 |
|
---|
| 435 | # RFA Rx
|
---|
| 436 | # PORT user_RFA_RXD_I = <user net>
|
---|
| 437 | # PORT user_RFA_RXD_Q = <user net>
|
---|
| 438 | # RFB Rx
|
---|
| 439 | # PORT user_RFB_RXD_I = <user net>
|
---|
| 440 | # PORT user_RFB_RXD_Q = <user net>
|
---|
| 441 | BEGIN plbv46_plbv46_bridge
|
---|
| 442 | PARAMETER INSTANCE = plb_primary_secondary_bridge
|
---|
| 443 | PARAMETER HW_VER = 1.04.a
|
---|
| 444 | PARAMETER C_BUS_CLOCK_RATIO = 2
|
---|
| 445 | PARAMETER C_NUM_ADDR_RNG = 1
|
---|
| 446 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000
|
---|
| 447 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
|
---|
| 448 | PARAMETER C_RNG0_BASEADDR = 0x83c00000
|
---|
| 449 | PARAMETER C_RNG0_HIGHADDR = 0x83c0ffff
|
---|
| 450 | BUS_INTERFACE MPLB = plb_secondary_80MHz
|
---|
| 451 | BUS_INTERFACE SPLB = plb_primary
|
---|
| 452 | END
|
---|
| 453 |
|
---|
| 454 | BEGIN plb_v46
|
---|
| 455 | PARAMETER INSTANCE = plb_secondary_80MHz
|
---|
| 456 | PARAMETER HW_VER = 1.05.a
|
---|
| 457 | PORT PLB_Clk = clk_80MHz
|
---|
| 458 | PORT SYS_Rst = sys_bus_reset
|
---|
| 459 | END
|
---|
| 460 |
|
---|
| 461 | BEGIN xps_sysmon_adc
|
---|
| 462 | PARAMETER INSTANCE = xps_sysmon_adc_0
|
---|
| 463 | PARAMETER HW_VER = 3.00.b
|
---|
| 464 | PARAMETER C_DCLK_RATIO = 2
|
---|
| 465 | PARAMETER C_BASEADDR = 0x83800000
|
---|
| 466 | PARAMETER C_HIGHADDR = 0x8380ffff
|
---|
| 467 | BUS_INTERFACE SPLB = plb_primary
|
---|
| 468 | END
|
---|
| 469 |
|
---|