1 |
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2 | # ##############################################################################
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3 | # Template Project for WARP v3 Rev 1.1
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4 | # Family: virtex6
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5 | # Device: xc6vlx240t
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6 | # Package: ff1156
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7 | # Speed Grade: -2
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8 | # Processor number: 1
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9 | # Processor 1: microblaze_0
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10 | # Processor and primary bus clock frequency: 160.0 MHz
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11 | # Secondary bus clock frequency: 80.0 MHz
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12 | # ##############################################################################
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13 | PARAMETER VERSION = 2.1.0
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14 |
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15 |
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16 | # User IO (LEDs, buttons, etc.) pins
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17 | PORT USERIO_hexdisp_left_pin = USERIO_hexdisp_left_pin, DIR = O, VEC = [0:6]
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18 | PORT USERIO_hexdisp_right_pin = USERIO_hexdisp_right_pin, DIR = O, VEC = [0:6]
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19 | PORT USERIO_hexdisp_left_dp_pin = USERIO_hexdisp_left_dp_pin, DIR = O
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20 | PORT USERIO_hexdisp_right_dp_pin = USERIO_hexdisp_right_dp_pin, DIR = O
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21 | PORT USERIO_leds_red_pin = USERIO_leds_red_pin, DIR = O, VEC = [0:3]
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22 | PORT USERIO_leds_green_pin = USERIO_leds_green_pin, DIR = O, VEC = [0:3]
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23 | PORT USERIO_rfa_led_red_pin = USERIO_rfa_led_red_pin, DIR = O
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24 | PORT USERIO_rfa_led_green_pin = USERIO_rfa_led_green_pin, DIR = O
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25 | PORT USERIO_rfb_led_red_pin = USERIO_rfb_led_red_pin, DIR = O
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26 | PORT USERIO_rfb_led_green_pin = USERIO_rfb_led_green_pin, DIR = O
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27 | PORT USERIO_dipsw_pin = USERIO_dipsw_pin, DIR = I, VEC = [0:3]
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28 | PORT USERIO_pb_u_pin = USERIO_pb_u_pin, DIR = I
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29 | PORT USERIO_pb_m_pin = USERIO_pb_m_pin, DIR = I
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30 | PORT USERIO_pb_d_pin = USERIO_pb_d_pin, DIR = I
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31 | # USB UART transceiver pins
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32 | PORT UART_USB_RX_pin = UART_USB_RX_pin, DIR = I
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33 | PORT UART_USB_TX_pin = UART_USB_TX_pin, DIR = O
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34 | # IIC EEPROM pins
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35 | PORT IIC_EEPROM_iic_scl_pin = IIC_EEPROM_iic_scl_pin, DIR = IO
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36 | PORT IIC_EEPROM_iic_sda_pin = IIC_EEPROM_iic_sda_pin, DIR = IO
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37 | # Eth A RGMII pins
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38 | PORT ETH_A_TemacPhy_RST_n_pin = ETH_A_TemacPhy_RST_n_pin, DIR = O
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39 | PORT ETH_A_RGMII_TXD_0_pin = ETH_A_RGMII_TXD_0_pin, DIR = O, VEC = [3:0]
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40 | PORT ETH_A_RGMII_TX_CTL_0_pin = ETH_A_RGMII_TX_CTL_0_pin, DIR = O
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41 | PORT ETH_A_RGMII_TXC_0_pin = ETH_A_RGMII_TXC_0_pin, DIR = O
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42 | PORT ETH_A_RGMII_RXD_0_pin = ETH_A_RGMII_RXD_0_pin, DIR = I, VEC = [3:0]
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43 | PORT ETH_A_RGMII_RX_CTL_0_pin = ETH_A_RGMII_RX_CTL_0_pin, DIR = I
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44 | PORT ETH_A_RGMII_RXC_0_pin = ETH_A_RGMII_RXC_0_pin, DIR = I
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45 | PORT ETH_A_MDC_0_pin = ETH_A_MDC_0_pin, DIR = O
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46 | PORT ETH_A_MDIO_0_pin = ETH_A_MDIO_0_pin, DIR = IO
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47 | # Eth A RGMII pins
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48 | PORT ETH_B_RGMII_TXD_0_pin = ETH_B_RGMII_TXD_0_pin, DIR = O, VEC = [3:0]
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49 | PORT ETH_B_RGMII_TX_CTL_0_pin = ETH_B_RGMII_TX_CTL_0_pin, DIR = O
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50 | PORT ETH_B_RGMII_TXC_0_pin = ETH_B_RGMII_TXC_0_pin, DIR = O
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51 | PORT ETH_B_RGMII_RXD_0_pin = ETH_B_RGMII_RXD_0_pin, DIR = I, VEC = [3:0]
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52 | PORT ETH_B_RGMII_RX_CTL_0_pin = ETH_B_RGMII_RX_CTL_0_pin, DIR = I
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53 | PORT ETH_B_RGMII_RXC_0_pin = ETH_B_RGMII_RXC_0_pin, DIR = I
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54 | PORT ETH_B_MDC_0_pin = ETH_B_MDC_0_pin, DIR = O
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55 | PORT ETH_B_MDIO_0_pin = ETH_B_MDIO_0_pin, DIR = IO
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56 | # DDR3 SO-DIMM slot pins
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57 | PORT DDR3_2GB_SODIMM_Clk_pin = DDR3_2GB_SODIMM_Clk_pin, DIR = O
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58 | PORT DDR3_2GB_SODIMM_Clk_n_pin = DDR3_2GB_SODIMM_Clk_n_pin, DIR = O
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59 | PORT DDR3_2GB_SODIMM_CE_pin = DDR3_2GB_SODIMM_CE_pin, DIR = O
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60 | PORT DDR3_2GB_SODIMM_CS_n_pin = DDR3_2GB_SODIMM_CS_n_pin, DIR = O
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61 | PORT DDR3_2GB_SODIMM_ODT_pin = DDR3_2GB_SODIMM_ODT_pin, DIR = O
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62 | PORT DDR3_2GB_SODIMM_RAS_n_pin = DDR3_2GB_SODIMM_RAS_n_pin, DIR = O
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63 | PORT DDR3_2GB_SODIMM_CAS_n_pin = DDR3_2GB_SODIMM_CAS_n_pin, DIR = O
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64 | PORT DDR3_2GB_SODIMM_WE_n_pin = DDR3_2GB_SODIMM_WE_n_pin, DIR = O
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65 | PORT DDR3_2GB_SODIMM_BankAddr_pin = DDR3_2GB_SODIMM_BankAddr_pin, DIR = O, VEC = [2:0]
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66 | PORT DDR3_2GB_SODIMM_Addr_pin = DDR3_2GB_SODIMM_Addr_pin, DIR = O, VEC = [14:0]
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67 | PORT DDR3_2GB_SODIMM_DQ_pin = DDR3_2GB_SODIMM_DQ_pin, DIR = IO, VEC = [31:0]
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68 | PORT DDR3_2GB_SODIMM_DM_pin = DDR3_2GB_SODIMM_DM_pin, DIR = O, VEC = [3:0]
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69 | PORT DDR3_2GB_SODIMM_Reset_n_pin = DDR3_2GB_SODIMM_Reset_n_pin, DIR = O
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70 | PORT DDR3_2GB_SODIMM_DQS_pin = DDR3_2GB_SODIMM_DQS_pin, DIR = IO, VEC = [3:0]
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71 | PORT DDR3_2GB_SODIMM_DQS_n_pin = DDR3_2GB_SODIMM_DQS_n_pin, DIR = IO, VEC = [3:0]
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72 | # AD9963 ADC/DAC control pins (RFA & RFB)
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73 | PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O
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74 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
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75 | PORT RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O
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76 | PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O
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77 | PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O
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78 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
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79 | PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O
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80 | PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O
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81 | # AD9512 clock buffer control pins (RF reference & sampling clocks)
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82 | PORT clk_rfref_spi_cs_n_pin = clk_rfref_spi_cs_n, DIR = O
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83 | PORT clk_rfref_spi_mosi_pin = clk_rfref_spi_mosi, DIR = O
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84 | PORT clk_rfref_spi_sclk_pin = clk_rfref_spi_sclk, DIR = O
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85 | PORT clk_rfref_spi_miso_pin = clk_rfref_spi_miso, DIR = I
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86 | PORT clk_rfref_func_pin = net_vcc, DIR = O
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87 | PORT clk_samp_spi_cs_n_pin = clk_samp_spi_cs_n, DIR = O
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88 | PORT clk_samp_spi_mosi_pin = clk_samp_spi_mosi, DIR = O
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89 | PORT clk_samp_spi_sclk_pin = clk_samp_spi_sclk, DIR = O
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90 | PORT clk_samp_spi_miso_pin = clk_samp_spi_miso, DIR = I
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91 | PORT clk_samp_func_pin = net_vcc, DIR = O
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92 | # RFA transceiver and front-end
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93 | PORT RFA_TxEn_pin = RFA_TxEn, DIR = O
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94 | PORT RFA_RxEn_pin = RFA_RxEn, DIR = O
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95 | PORT RFA_RxHP_pin = RFA_RxHP, DIR = O
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96 | PORT RFA_SHDN_pin = RFA_SHDN, DIR = O
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97 | PORT RFA_SPI_SCLK_pin = RFA_SPI_SCLK, DIR = O
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98 | PORT RFA_SPI_MOSI_pin = RFA_SPI_MOSI, DIR = O
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99 | PORT RFA_SPI_CSn_pin = RFA_SPI_CSn, DIR = O
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100 | PORT RFA_B_pin = RFA_B, DIR = O, VEC = [0:6]
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101 | PORT RFA_LD_pin = RFA_LD, DIR = I
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102 | PORT RFA_PAEn_24_pin = RFA_PAEn_24, DIR = O
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103 | PORT RFA_PAEn_5_pin = RFA_PAEn_5, DIR = O
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104 | PORT RFA_AntSw_pin = RFA_AntSw, DIR = O, VEC = [0:1]
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105 | # RFB transceiver and front-end
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106 | PORT RFB_TxEn_pin = RFB_TxEn, DIR = O
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107 | PORT RFB_RxEn_pin = RFB_RxEn, DIR = O
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108 | PORT RFB_RxHP_pin = RFB_RxHP, DIR = O
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109 | PORT RFB_SHDN_pin = RFB_SHDN, DIR = O
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110 | PORT RFB_SPI_SCLK_pin = RFB_SPI_SCLK, DIR = O
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111 | PORT RFB_SPI_MOSI_pin = RFB_SPI_MOSI, DIR = O
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112 | PORT RFB_SPI_CSn_pin = RFB_SPI_CSn, DIR = O
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113 | PORT RFB_B_pin = RFB_B, DIR = O, VEC = [0:6]
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114 | PORT RFB_LD_pin = RFB_LD, DIR = I
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115 | PORT RFB_PAEn_24_pin = RFB_PAEn_24, DIR = O
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116 | PORT RFB_PAEn_5_pin = RFB_PAEn_5, DIR = O
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117 | PORT RFB_AntSw_pin = RFB_AntSw, DIR = O, VEC = [0:1]
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118 | # RFA AD pins
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119 | PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
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120 | PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
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121 | PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
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122 | PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
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123 | PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
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124 | PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
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125 | # RFB AD pins
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126 | PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
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127 | PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
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128 | PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
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129 | PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
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130 | PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
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131 | PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
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132 | # RSSI ADC pins
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133 | PORT RFA_RSSI_D = warplab_radio1_rssi_D, DIR = I, VEC = [9:0]
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134 | PORT RFB_RSSI_D = warplab_radio2_rssi_D, DIR = I, VEC = [9:0]
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135 | PORT RF_RSSI_CLK = warplab_rssi_clk, DIR = O
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136 | PORT RF_RSSI_PD = net_gnd, DIR = O
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137 | # 80MHz sampling clock from AD9512
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138 | PORT samp_clk_p_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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139 | PORT samp_clk_n_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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140 | # 200MHz LVDS oscillator input
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141 | PORT osc200_p_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
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142 | PORT osc200_n_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
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143 | # System reset, tied to RESET push button
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144 | PORT rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
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145 |
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146 |
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147 | BEGIN microblaze
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148 | PARAMETER INSTANCE = microblaze_0
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149 | PARAMETER C_USE_BARREL = 1
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150 | PARAMETER C_DEBUG_ENABLED = 1
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151 | PARAMETER HW_VER = 8.20.b
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152 | PARAMETER C_USE_DIV = 1
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153 | PARAMETER C_UNALIGNED_EXCEPTIONS = 1
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154 | BUS_INTERFACE DPLB = plb_primary
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155 | BUS_INTERFACE IPLB = plb_primary
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156 | BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
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157 | BUS_INTERFACE DLMB = dlmb
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158 | BUS_INTERFACE ILMB = ilmb
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159 | PORT MB_RESET = mb_reset
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160 | END
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161 |
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162 | BEGIN plb_v46
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163 | PARAMETER INSTANCE = plb_primary
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164 | PARAMETER HW_VER = 1.05.a
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165 | PORT PLB_Clk = clk_160MHz
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166 | PORT SYS_Rst = sys_bus_reset
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167 | END
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168 |
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169 | BEGIN lmb_v10
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170 | PARAMETER INSTANCE = ilmb
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171 | PARAMETER HW_VER = 2.00.b
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172 | PORT LMB_Clk = clk_160MHz
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173 | PORT SYS_Rst = sys_bus_reset
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174 | END
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175 |
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176 | BEGIN lmb_v10
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177 | PARAMETER INSTANCE = dlmb
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178 | PARAMETER HW_VER = 2.00.b
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179 | PORT LMB_Clk = clk_160MHz
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180 | PORT SYS_Rst = sys_bus_reset
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181 | END
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182 |
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183 | BEGIN lmb_bram_if_cntlr
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184 | PARAMETER INSTANCE = dlmb_cntlr
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185 | PARAMETER HW_VER = 3.00.b
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186 | PARAMETER C_BASEADDR = 0x00000000
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187 | PARAMETER C_HIGHADDR = 0x0000ffff
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188 | BUS_INTERFACE SLMB = dlmb
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189 | BUS_INTERFACE BRAM_PORT = dlmb_port
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190 | END
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191 |
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192 | BEGIN lmb_bram_if_cntlr
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193 | PARAMETER INSTANCE = ilmb_cntlr
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194 | PARAMETER HW_VER = 3.00.b
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195 | PARAMETER C_BASEADDR = 0x00000000
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196 | PARAMETER C_HIGHADDR = 0x0000ffff
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197 | BUS_INTERFACE SLMB = ilmb
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198 | BUS_INTERFACE BRAM_PORT = ilmb_port
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199 | END
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200 |
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201 | BEGIN bram_block
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202 | PARAMETER INSTANCE = lmb_bram
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203 | PARAMETER HW_VER = 1.00.a
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204 | BUS_INTERFACE PORTA = ilmb_port
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205 | BUS_INTERFACE PORTB = dlmb_port
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206 | END
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207 |
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208 | BEGIN w3_userio
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209 | PARAMETER INSTANCE = w3_userio_0
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210 | PARAMETER HW_VER = 1.00.a
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211 | PARAMETER C_BASEADDR = 0xc8e00000
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212 | PARAMETER C_HIGHADDR = 0xc8e0ffff
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213 | BUS_INTERFACE SPLB = plb_primary
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214 | PORT hexdisp_left = USERIO_hexdisp_left_pin
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215 | PORT hexdisp_right = USERIO_hexdisp_right_pin
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216 | PORT hexdisp_left_dp = USERIO_hexdisp_left_dp_pin
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217 | PORT hexdisp_right_dp = USERIO_hexdisp_right_dp_pin
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218 | PORT leds_red = USERIO_leds_red_pin
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219 | PORT leds_green = USERIO_leds_green_pin
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220 | PORT rfa_led_red = USERIO_rfa_led_red_pin
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221 | PORT rfa_led_green = USERIO_rfa_led_green_pin
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222 | PORT rfb_led_red = USERIO_rfb_led_red_pin
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223 | PORT rfb_led_green = USERIO_rfb_led_green_pin
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224 | PORT dipsw = USERIO_dipsw_pin
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225 | PORT pb_u = USERIO_pb_u_pin
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226 | PORT pb_m = USERIO_pb_m_pin
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227 | PORT pb_d = USERIO_pb_d_pin
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228 | PORT usr_rfa_led_red = RFA_statLED_Rx
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229 | PORT usr_rfa_led_green = RFA_statLED_Tx
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230 | PORT usr_rfb_led_red = RFB_statLED_Rx
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231 | PORT usr_rfb_led_green = RFB_statLED_Tx
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232 | PORT DNA_Port_Clk = clk_40MHz
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233 | END
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234 |
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235 | BEGIN w3_iic_eeprom
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236 | PARAMETER INSTANCE = w3_iic_eeprom_0
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237 | PARAMETER HW_VER = 1.00.b
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238 | PARAMETER C_BASEADDR = 0xcbe00000
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239 | PARAMETER C_HIGHADDR = 0xcbe0ffff
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240 | BUS_INTERFACE SPLB = plb_primary
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241 | PORT iic_scl = IIC_EEPROM_iic_scl_pin
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242 | PORT iic_sda = IIC_EEPROM_iic_sda_pin
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243 | END
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244 |
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245 | BEGIN xps_uartlite
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246 | PARAMETER INSTANCE = UART_USB
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247 | PARAMETER C_BAUDRATE = 57600
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248 | PARAMETER C_DATA_BITS = 8
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249 | PARAMETER C_USE_PARITY = 0
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250 | PARAMETER C_ODD_PARITY = 0
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251 | PARAMETER HW_VER = 1.02.a
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252 | PARAMETER C_BASEADDR = 0x84000000
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253 | PARAMETER C_HIGHADDR = 0x8400ffff
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254 | BUS_INTERFACE SPLB = plb_primary
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255 | PORT RX = UART_USB_RX_pin
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256 | PORT TX = UART_USB_TX_pin
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257 | END
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258 |
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259 | BEGIN xps_ll_temac
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260 | PARAMETER INSTANCE = ETH_A
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261 | PARAMETER C_NUM_IDELAYCTRL = 1
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262 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y2
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263 | PARAMETER C_PHY_TYPE = 3
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264 | PARAMETER C_TEMAC1_ENABLED = 0
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265 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
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266 | PARAMETER C_TEMAC_TYPE = 3
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267 | PARAMETER C_TEMAC0_PHYADDR = 0b00001
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268 | PARAMETER HW_VER = 2.03.a
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269 | PARAMETER C_BASEADDR = 0x87100000
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270 | PARAMETER C_HIGHADDR = 0x8717ffff
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271 | BUS_INTERFACE SPLB = plb_primary
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272 | BUS_INTERFACE LLINK0 = ETH_A_llink0
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273 | PORT TemacPhy_RST_n = ETH_A_TemacPhy_RST_n_pin
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274 | PORT GTX_CLK_0 = clk_125MHz
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275 | PORT REFCLK = clk_200MHz
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276 | PORT LlinkTemac0_CLK = clk_160MHz
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277 | PORT RGMII_TXD_0 = ETH_A_RGMII_TXD_0_pin
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278 | PORT RGMII_TX_CTL_0 = ETH_A_RGMII_TX_CTL_0_pin
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279 | PORT RGMII_TXC_0 = ETH_A_RGMII_TXC_0_pin
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280 | PORT RGMII_RXD_0 = ETH_A_RGMII_RXD_0_pin
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281 | PORT RGMII_RX_CTL_0 = ETH_A_RGMII_RX_CTL_0_pin
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282 | PORT RGMII_RXC_0 = ETH_A_RGMII_RXC_0_pin
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283 | PORT MDC_0 = ETH_A_MDC_0_pin
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284 | PORT MDIO_0 = ETH_A_MDIO_0_pin
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285 | END
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286 |
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287 | BEGIN xps_ll_temac
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288 | PARAMETER INSTANCE = ETH_B
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289 | PARAMETER C_NUM_IDELAYCTRL = 0
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290 | PARAMETER C_PHY_TYPE = 3
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291 | PARAMETER C_TEMAC1_ENABLED = 0
|
---|
292 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
293 | PARAMETER C_TEMAC_TYPE = 3
|
---|
294 | PARAMETER C_TEMAC0_PHYADDR = 0b00001
|
---|
295 | PARAMETER HW_VER = 2.03.a
|
---|
296 | PARAMETER C_BASEADDR = 0x87000000
|
---|
297 | PARAMETER C_HIGHADDR = 0x8707ffff
|
---|
298 | BUS_INTERFACE SPLB = plb_primary
|
---|
299 | BUS_INTERFACE LLINK0 = ETH_B_llink0
|
---|
300 | PORT GTX_CLK_0 = clk_125MHz
|
---|
301 | PORT REFCLK = clk_200MHz
|
---|
302 | PORT LlinkTemac0_CLK = clk_160MHz
|
---|
303 | PORT RGMII_TXD_0 = ETH_B_RGMII_TXD_0_pin
|
---|
304 | PORT RGMII_TX_CTL_0 = ETH_B_RGMII_TX_CTL_0_pin
|
---|
305 | PORT RGMII_TXC_0 = ETH_B_RGMII_TXC_0_pin
|
---|
306 | PORT RGMII_RXD_0 = ETH_B_RGMII_RXD_0_pin
|
---|
307 | PORT RGMII_RX_CTL_0 = ETH_B_RGMII_RX_CTL_0_pin
|
---|
308 | PORT RGMII_RXC_0 = ETH_B_RGMII_RXC_0_pin
|
---|
309 | PORT MDC_0 = ETH_B_MDC_0_pin
|
---|
310 | PORT MDIO_0 = ETH_B_MDIO_0_pin
|
---|
311 | END
|
---|
312 |
|
---|
313 | BEGIN mpmc
|
---|
314 | PARAMETER INSTANCE = DDR3_2GB_SODIMM
|
---|
315 | PARAMETER C_NUM_PORTS = 1
|
---|
316 | PARAMETER C_MEM_TYPE = DDR3
|
---|
317 | PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
|
---|
318 | PARAMETER C_MEM_ODT_TYPE = 1
|
---|
319 | PARAMETER C_MEM_REG_DIMM = 0
|
---|
320 | PARAMETER C_MEM_CLK_WIDTH = 1
|
---|
321 | PARAMETER C_MEM_ODT_WIDTH = 1
|
---|
322 | PARAMETER C_MEM_CE_WIDTH = 1
|
---|
323 | PARAMETER C_MEM_CS_N_WIDTH = 1
|
---|
324 | PARAMETER C_MEM_DATA_WIDTH = 32
|
---|
325 | PARAMETER C_MEM_NDQS_COL0 = 4
|
---|
326 | PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000003020100
|
---|
327 | PARAMETER C_PIM0_BASETYPE = 2
|
---|
328 | PARAMETER HW_VER = 6.05.a
|
---|
329 | PARAMETER C_FAMILY = virtex6
|
---|
330 | PARAMETER C_MPMC_BASEADDR = 0x40000000
|
---|
331 | PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
|
---|
332 | BUS_INTERFACE SPLB0 = plb_primary
|
---|
333 | PORT MPMC_Clk0 = clk_160MHz
|
---|
334 | PORT MPMC_Clk_200MHz = clk_200MHz
|
---|
335 | PORT MPMC_Rst = sys_periph_reset
|
---|
336 | PORT MPMC_Clk_Mem = clk_320MHz
|
---|
337 | PORT MPMC_Clk_Rd_Base = clk_320MHz_nobuf_varphase
|
---|
338 | PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
|
---|
339 | PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
|
---|
340 | PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
|
---|
341 | PORT DDR3_Clk = DDR3_2GB_SODIMM_Clk_pin
|
---|
342 | PORT DDR3_Clk_n = DDR3_2GB_SODIMM_Clk_n_pin
|
---|
343 | PORT DDR3_CE = DDR3_2GB_SODIMM_CE_pin
|
---|
344 | PORT DDR3_CS_n = DDR3_2GB_SODIMM_CS_n_pin
|
---|
345 | PORT DDR3_ODT = DDR3_2GB_SODIMM_ODT_pin
|
---|
346 | PORT DDR3_RAS_n = DDR3_2GB_SODIMM_RAS_n_pin
|
---|
347 | PORT DDR3_CAS_n = DDR3_2GB_SODIMM_CAS_n_pin
|
---|
348 | PORT DDR3_WE_n = DDR3_2GB_SODIMM_WE_n_pin
|
---|
349 | PORT DDR3_BankAddr = DDR3_2GB_SODIMM_BankAddr_pin
|
---|
350 | PORT DDR3_Addr = DDR3_2GB_SODIMM_Addr_pin
|
---|
351 | PORT DDR3_DQ = DDR3_2GB_SODIMM_DQ_pin
|
---|
352 | PORT DDR3_DM = DDR3_2GB_SODIMM_DM_pin
|
---|
353 | PORT DDR3_Reset_n = DDR3_2GB_SODIMM_Reset_n_pin
|
---|
354 | PORT DDR3_DQS = DDR3_2GB_SODIMM_DQS_pin
|
---|
355 | PORT DDR3_DQS_n = DDR3_2GB_SODIMM_DQS_n_pin
|
---|
356 | END
|
---|
357 |
|
---|
358 | BEGIN xps_ll_fifo
|
---|
359 | PARAMETER INSTANCE = ETH_A_fifo
|
---|
360 | PARAMETER HW_VER = 1.02.a
|
---|
361 | PARAMETER C_BASEADDR = 0x81a20000
|
---|
362 | PARAMETER C_HIGHADDR = 0x81a2ffff
|
---|
363 | BUS_INTERFACE SPLB = plb_primary
|
---|
364 | BUS_INTERFACE LLINK = ETH_A_llink0
|
---|
365 | END
|
---|
366 |
|
---|
367 | BEGIN xps_ll_fifo
|
---|
368 | PARAMETER INSTANCE = ETH_B_fifo
|
---|
369 | PARAMETER HW_VER = 1.02.a
|
---|
370 | PARAMETER C_BASEADDR = 0x81a00000
|
---|
371 | PARAMETER C_HIGHADDR = 0x81a0ffff
|
---|
372 | BUS_INTERFACE SPLB = plb_primary
|
---|
373 | BUS_INTERFACE LLINK = ETH_B_llink0
|
---|
374 | END
|
---|
375 |
|
---|
376 | BEGIN clock_generator
|
---|
377 | PARAMETER INSTANCE = clock_generator_ProcBusSamp_Clocks
|
---|
378 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
379 | PARAMETER HW_VER = 4.03.a
|
---|
380 | # 80MHz clock input (driven by AD9512 for sampling clock)
|
---|
381 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
382 | # 2x Sampling clock 0 deg phase
|
---|
383 | PARAMETER C_CLKOUT0_FREQ = 80000000
|
---|
384 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
385 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
386 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
387 | # MB and primary PLB
|
---|
388 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
389 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
390 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
391 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
392 | # Sampling clock 0 deg phase
|
---|
393 | PARAMETER C_CLKOUT2_FREQ = 40000000
|
---|
394 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
395 | PARAMETER C_CLKOUT2_GROUP = MMCM0
|
---|
396 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
397 | # Sampling clock 90 deg phase
|
---|
398 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
399 | PARAMETER C_CLKOUT3_PHASE = 90
|
---|
400 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
401 | PARAMETER C_CLKOUT3_GROUP = MMCM0
|
---|
402 | PORT CLKIN = ad_refclk_in
|
---|
403 | PORT CLKOUT0 = clk_80MHz
|
---|
404 | PORT CLKOUT1 = clk_160MHz
|
---|
405 | PORT CLKOUT2 = clk_40MHz
|
---|
406 | PORT CLKOUT3 = clk_40MHz_90degphase
|
---|
407 | PORT RST = sys_rst_s
|
---|
408 | PORT LOCKED = clk_gen_0_locked
|
---|
409 | END
|
---|
410 |
|
---|
411 | BEGIN clock_generator
|
---|
412 | PARAMETER INSTANCE = clock_generator_asyncClks
|
---|
413 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
414 | PARAMETER HW_VER = 4.03.a
|
---|
415 | # 200MHz clock input (driven by 200MHz LVDS oscillator)
|
---|
416 | PARAMETER C_CLKIN_FREQ = 200000000
|
---|
417 | # TEMAC TxClk
|
---|
418 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
419 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
420 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
421 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
422 | # IDELAYCTRL refclk
|
---|
423 | PARAMETER C_CLKOUT1_FREQ = 200000000
|
---|
424 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
425 | PARAMETER C_CLKOUT1_GROUP = NONE
|
---|
426 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
427 | PORT CLKIN = osc200_in
|
---|
428 | PORT CLKOUT0 = clk_125MHz
|
---|
429 | PORT CLKOUT1 = clk_200MHz
|
---|
430 | PORT RST = sys_rst_s
|
---|
431 | PORT LOCKED = clk_gen_1_locked
|
---|
432 | END
|
---|
433 |
|
---|
434 | BEGIN clock_generator
|
---|
435 | PARAMETER INSTANCE = clock_generator_MPMC_Clocks
|
---|
436 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
437 | PARAMETER HW_VER = 4.03.a
|
---|
438 | # 80MHz clock input (driven by other clock generator)
|
---|
439 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
440 | # MPMC DRAM clock (2x bus)
|
---|
441 | PARAMETER C_CLKOUT0_FREQ = 320000000
|
---|
442 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
443 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
444 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
445 | # MPMC DRAM clock (2x bus, variable phase)
|
---|
446 | PARAMETER C_CLKOUT1_FREQ = 320000000
|
---|
447 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
448 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
449 | PARAMETER C_CLKOUT1_BUF = FALSE
|
---|
450 | PARAMETER C_CLKOUT1_VARIABLE_PHASE = TRUE
|
---|
451 | PARAMETER C_PSDONE_GROUP = MMCM0
|
---|
452 | PORT CLKIN = clk_80MHz
|
---|
453 | PORT CLKOUT0 = clk_320MHz
|
---|
454 | PORT CLKOUT1 = clk_320MHz_nobuf_varphase
|
---|
455 | PORT PSCLK = clk_80MHz
|
---|
456 | PORT PSEN = MPMC_DCM_PSEN
|
---|
457 | PORT PSINCDEC = MPMC_DCM_PSINCDEC
|
---|
458 | PORT PSDONE = MPMC_DCM_PSDONE
|
---|
459 | PORT RST = sys_rst_s
|
---|
460 | PORT LOCKED = clk_gen_2_locked
|
---|
461 | END
|
---|
462 |
|
---|
463 | BEGIN mdm
|
---|
464 | PARAMETER INSTANCE = mdm_0
|
---|
465 | PARAMETER C_MB_DBG_PORTS = 1
|
---|
466 | PARAMETER C_USE_UART = 1
|
---|
467 | PARAMETER HW_VER = 2.00.b
|
---|
468 | PARAMETER C_BASEADDR = 0x84400000
|
---|
469 | PARAMETER C_HIGHADDR = 0x8440ffff
|
---|
470 | BUS_INTERFACE SPLB = plb_primary
|
---|
471 | BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
|
---|
472 | PORT Debug_SYS_Rst = Debug_SYS_Rst
|
---|
473 | END
|
---|
474 |
|
---|
475 | BEGIN proc_sys_reset
|
---|
476 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
477 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
478 | PARAMETER HW_VER = 3.00.a
|
---|
479 | PORT Slowest_sync_clk = clk_40MHz
|
---|
480 | PORT Ext_Reset_In = sys_rst_s
|
---|
481 | PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
|
---|
482 | PORT Dcm_locked = clk_gen_all_locked
|
---|
483 | PORT MB_Reset = mb_reset
|
---|
484 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
485 | PORT Peripheral_Reset = sys_periph_reset
|
---|
486 | END
|
---|
487 |
|
---|
488 | BEGIN util_reduced_logic
|
---|
489 | PARAMETER INSTANCE = clk_gen_locked_AND
|
---|
490 | PARAMETER HW_VER = 1.00.a
|
---|
491 | PARAMETER C_OPERATION = AND
|
---|
492 | PARAMETER C_SIZE = 3
|
---|
493 | PORT Op1 = clk_gen_0_locked & clk_gen_1_locked & clk_gen_2_locked
|
---|
494 | PORT Res = clk_gen_all_locked
|
---|
495 | END
|
---|
496 |
|
---|
497 | BEGIN bram_block
|
---|
498 | PARAMETER INSTANCE = bram_block_0
|
---|
499 | PARAMETER HW_VER = 1.00.a
|
---|
500 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
|
---|
501 | END
|
---|
502 |
|
---|
503 | BEGIN xps_bram_if_cntlr
|
---|
504 | PARAMETER INSTANCE = xps_bram_if_cntlr_0
|
---|
505 | PARAMETER HW_VER = 1.00.b
|
---|
506 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32
|
---|
507 | PARAMETER C_BASEADDR = 0x20060000
|
---|
508 | PARAMETER C_HIGHADDR = 0x2007ffff
|
---|
509 | BUS_INTERFACE SPLB = plb_primary
|
---|
510 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
|
---|
511 | END
|
---|
512 |
|
---|
513 | BEGIN bram_block
|
---|
514 | PARAMETER INSTANCE = bram_block_1
|
---|
515 | PARAMETER HW_VER = 1.00.a
|
---|
516 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
|
---|
517 | END
|
---|
518 |
|
---|
519 | BEGIN xps_bram_if_cntlr
|
---|
520 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
---|
521 | PARAMETER HW_VER = 1.00.b
|
---|
522 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32
|
---|
523 | PARAMETER C_BASEADDR = 0x20050000
|
---|
524 | PARAMETER C_HIGHADDR = 0x2005ffff
|
---|
525 | BUS_INTERFACE SPLB = plb_primary
|
---|
526 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
|
---|
527 | END
|
---|
528 |
|
---|
529 | BEGIN xps_timer
|
---|
530 | PARAMETER INSTANCE = xps_timer_0
|
---|
531 | PARAMETER HW_VER = 1.02.a
|
---|
532 | PARAMETER C_BASEADDR = 0x83c00000
|
---|
533 | PARAMETER C_HIGHADDR = 0x83c0ffff
|
---|
534 | BUS_INTERFACE SPLB = plb_secondary_80MHz
|
---|
535 | END
|
---|
536 |
|
---|
537 | # ###############
|
---|
538 | # WARP pcores
|
---|
539 | # ###############
|
---|
540 | BEGIN w3_clock_controller
|
---|
541 | PARAMETER INSTANCE = w3_clock_controller_0
|
---|
542 | PARAMETER HW_VER = 3.00.b
|
---|
543 | PARAMETER C_BASEADDR = 0xc0400000
|
---|
544 | PARAMETER C_HIGHADDR = 0xc040ffff
|
---|
545 | BUS_INTERFACE SPLB = plb_primary
|
---|
546 | PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
|
---|
547 | PORT samp_spi_cs_n = clk_samp_spi_cs_n
|
---|
548 | PORT samp_spi_mosi = clk_samp_spi_mosi
|
---|
549 | PORT rfref_spi_mosi = clk_rfref_spi_mosi
|
---|
550 | PORT samp_spi_sclk = clk_samp_spi_sclk
|
---|
551 | PORT rfref_spi_sclk = clk_rfref_spi_sclk
|
---|
552 | PORT samp_spi_miso = clk_samp_spi_miso
|
---|
553 | PORT rfref_spi_miso = clk_rfref_spi_miso
|
---|
554 | PORT usr_status = net_gnd
|
---|
555 | END
|
---|
556 |
|
---|
557 | BEGIN w3_ad_controller
|
---|
558 | PARAMETER INSTANCE = w3_ad_controller_0
|
---|
559 | PARAMETER HW_VER = 3.00.b
|
---|
560 | PARAMETER C_BASEADDR = 0xc6000000
|
---|
561 | PARAMETER C_HIGHADDR = 0xc600ffff
|
---|
562 | BUS_INTERFACE SPLB = plb_primary
|
---|
563 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
|
---|
564 | PORT RFB_AD_reset_n = RFB_AD_reset_n
|
---|
565 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
|
---|
566 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
|
---|
567 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
|
---|
568 | PORT RFA_AD_reset_n = RFA_AD_reset_n
|
---|
569 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
|
---|
570 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
|
---|
571 | END
|
---|
572 |
|
---|
573 | BEGIN radio_controller
|
---|
574 | PARAMETER INSTANCE = radio_controller_0
|
---|
575 | PARAMETER HW_VER = 3.00.b
|
---|
576 | PARAMETER C_BASEADDR = 0xcac00000
|
---|
577 | PARAMETER C_HIGHADDR = 0xcac0ffff
|
---|
578 | BUS_INTERFACE SPLB = plb_primary
|
---|
579 | PORT RFA_TxEn = RFA_TxEn
|
---|
580 | PORT RFA_RxEn = RFA_RxEn
|
---|
581 | PORT RFA_RxHP = RFA_RxHP
|
---|
582 | PORT RFA_SHDN = RFA_SHDN
|
---|
583 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
---|
584 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
---|
585 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
---|
586 | PORT RFA_B = RFA_B
|
---|
587 | PORT RFA_LD = RFA_LD
|
---|
588 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
---|
589 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
---|
590 | PORT RFA_AntSw = RFA_AntSw
|
---|
591 | PORT RFB_TxEn = RFB_TxEn
|
---|
592 | PORT RFB_RxEn = RFB_RxEn
|
---|
593 | PORT RFB_RxHP = RFB_RxHP
|
---|
594 | PORT RFB_SHDN = RFB_SHDN
|
---|
595 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
---|
596 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
---|
597 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
---|
598 | PORT RFB_B = RFB_B
|
---|
599 | PORT RFB_LD = RFB_LD
|
---|
600 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
---|
601 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
---|
602 | PORT RFB_AntSw = RFB_AntSw
|
---|
603 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
---|
604 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
---|
605 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
---|
606 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
---|
607 | END
|
---|
608 |
|
---|
609 | BEGIN w3_ad_bridge
|
---|
610 | PARAMETER INSTANCE = w3_ad_bridge_0
|
---|
611 | # exclude IDELAYCTRL, since TEMACs include them
|
---|
612 | PARAMETER INCLUDE_IDELAYCTRL = 0
|
---|
613 | PARAMETER HW_VER = 3.00.g
|
---|
614 | # Clock ports (inputs to w3_ad_bridge)
|
---|
615 | PORT clk200 = net_gnd
|
---|
616 | PORT sys_samp_clk_Tx = clk_40MHz
|
---|
617 | PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
|
---|
618 | PORT sys_samp_clk_Rx = clk_40MHz
|
---|
619 | # Top-level AD9963 ports
|
---|
620 | PORT ad_RFA_TXD = rfa_txd
|
---|
621 | PORT ad_RFA_TXCLK = rfa_txclk
|
---|
622 | PORT ad_RFA_TXIQ = rfa_txiq
|
---|
623 | PORT ad_RFA_TRXD = rfa_trxd
|
---|
624 | PORT ad_RFA_TRXCLK = rfa_trxclk
|
---|
625 | PORT ad_RFA_TRXIQ = rfa_trxiq
|
---|
626 | PORT ad_RFB_TXD = rfb_txd
|
---|
627 | PORT ad_RFB_TXCLK = rfb_txclk
|
---|
628 | PORT ad_RFB_TXIQ = rfb_txiq
|
---|
629 | PORT ad_RFB_TRXD = rfb_trxd
|
---|
630 | PORT ad_RFB_TRXCLK = rfb_trxclk
|
---|
631 | PORT ad_RFB_TRXIQ = rfb_trxiq
|
---|
632 | # ####
|
---|
633 | # User ports - connect these to custom logic
|
---|
634 | # Each port is Fix12_11
|
---|
635 | # RFA Tx
|
---|
636 | PORT user_RFA_TXD_I = net_gnd
|
---|
637 | PORT user_RFA_TXD_Q = net_gnd
|
---|
638 | # RFB Tx
|
---|
639 | PORT user_RFB_TXD_I = net_gnd
|
---|
640 | PORT user_RFB_TXD_Q = net_gnd
|
---|
641 | END
|
---|
642 |
|
---|
643 | # RFA Rx
|
---|
644 | # PORT user_RFA_RXD_I = <user net>
|
---|
645 | # PORT user_RFA_RXD_Q = <user net>
|
---|
646 | # RFB Rx
|
---|
647 | # PORT user_RFB_RXD_I = <user net>
|
---|
648 | # PORT user_RFB_RXD_Q = <user net>
|
---|
649 | BEGIN plbv46_plbv46_bridge
|
---|
650 | PARAMETER INSTANCE = plb_primary_secondary_bridge
|
---|
651 | PARAMETER HW_VER = 1.04.a
|
---|
652 | PARAMETER C_BUS_CLOCK_RATIO = 2
|
---|
653 | PARAMETER C_NUM_ADDR_RNG = 1
|
---|
654 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000
|
---|
655 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
|
---|
656 | PARAMETER C_RNG0_BASEADDR = 0x83c00000
|
---|
657 | PARAMETER C_RNG0_HIGHADDR = 0x83c0ffff
|
---|
658 | BUS_INTERFACE MPLB = plb_secondary_80MHz
|
---|
659 | BUS_INTERFACE SPLB = plb_primary
|
---|
660 | END
|
---|
661 |
|
---|
662 | BEGIN plb_v46
|
---|
663 | PARAMETER INSTANCE = plb_secondary_80MHz
|
---|
664 | PARAMETER HW_VER = 1.05.a
|
---|
665 | PORT PLB_Clk = clk_80MHz
|
---|
666 | PORT SYS_Rst = sys_bus_reset
|
---|
667 | END
|
---|
668 |
|
---|
669 | BEGIN xps_sysmon_adc
|
---|
670 | PARAMETER INSTANCE = xps_sysmon_adc_0
|
---|
671 | PARAMETER HW_VER = 3.00.b
|
---|
672 | PARAMETER C_DCLK_RATIO = 2
|
---|
673 | PARAMETER C_BASEADDR = 0x83800000
|
---|
674 | PARAMETER C_HIGHADDR = 0x8380ffff
|
---|
675 | BUS_INTERFACE SPLB = plb_primary
|
---|
676 | END
|
---|
677 |
|
---|