| 1 | #User IO
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| 2 | Net USERIO_hexdisp_left_pin<0> LOC=AL33 | IOSTANDARD = LVCMOS25;
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| 3 | Net USERIO_hexdisp_left_pin<1> LOC=AK33 | IOSTANDARD = LVCMOS25;
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| 4 | Net USERIO_hexdisp_left_pin<2> LOC=AH32 | IOSTANDARD = LVCMOS25;
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| 5 | Net USERIO_hexdisp_left_pin<3> LOC=AF29 | IOSTANDARD = LVCMOS25;
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| 6 | Net USERIO_hexdisp_left_pin<4> LOC=AE29 | IOSTANDARD = LVCMOS25;
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| 7 | Net USERIO_hexdisp_left_pin<5> LOC=AK32 | IOSTANDARD = LVCMOS25;
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| 8 | Net USERIO_hexdisp_left_pin<6> LOC=AF30 | IOSTANDARD = LVCMOS25;
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| 9 | Net USERIO_hexdisp_right_pin<0> LOC=AE28 | IOSTANDARD = LVCMOS25;
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| 10 | Net USERIO_hexdisp_right_pin<1> LOC=AD26 | IOSTANDARD = LVCMOS25;
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| 11 | Net USERIO_hexdisp_right_pin<2> LOC=AC24 | IOSTANDARD = LVCMOS25;
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| 12 | Net USERIO_hexdisp_right_pin<3> LOC=AE23 | IOSTANDARD = LVCMOS25;
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| 13 | Net USERIO_hexdisp_right_pin<4> LOC=AC22 | IOSTANDARD = LVCMOS25;
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| 14 | Net USERIO_hexdisp_right_pin<5> LOC=AD27 | IOSTANDARD = LVCMOS25;
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| 15 | Net USERIO_hexdisp_right_pin<6> LOC=AB23 | IOSTANDARD = LVCMOS25;
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| 16 | Net USERIO_hexdisp_left_dp_pin LOC=AG30 | IOSTANDARD = LVCMOS25;
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| 17 | Net USERIO_hexdisp_right_dp_pin LOC=AC23 | IOSTANDARD = LVCMOS25;
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| 18 | Net USERIO_leds_red_pin<0> LOC=AN34 | IOSTANDARD = LVCMOS25;
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| 19 | Net USERIO_leds_red_pin<1> LOC=AM33 | IOSTANDARD = LVCMOS25;
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| 20 | Net USERIO_leds_red_pin<2> LOC=AN33 | IOSTANDARD = LVCMOS25;
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| 21 | Net USERIO_leds_red_pin<3> LOC=AP33 | IOSTANDARD = LVCMOS25;
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| 22 | Net USERIO_leds_green_pin<0> LOC=AD22 | IOSTANDARD = LVCMOS25;
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| 23 | Net USERIO_leds_green_pin<1> LOC=AE22 | IOSTANDARD = LVCMOS25;
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| 24 | Net USERIO_leds_green_pin<2> LOC=AM32 | IOSTANDARD = LVCMOS25;
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| 25 | Net USERIO_leds_green_pin<3> LOC=AN32 | IOSTANDARD = LVCMOS25;
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| 26 | Net USERIO_rfa_led_red_pin LOC=AL34 | IOSTANDARD = LVCMOS25;
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| 27 | Net USERIO_rfa_led_green_pin LOC=AK34 | IOSTANDARD = LVCMOS25;
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| 28 | Net USERIO_rfb_led_red_pin LOC=AJ34 | IOSTANDARD = LVCMOS25;
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| 29 | Net USERIO_rfb_led_green_pin LOC=AH34 | IOSTANDARD = LVCMOS25;
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| 30 | Net USERIO_dipsw_pin<0> LOC=AM22 | IOSTANDARD = LVCMOS15;
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| 31 | Net USERIO_dipsw_pin<1> LOC=AL23 | IOSTANDARD = LVCMOS15;
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| 32 | Net USERIO_dipsw_pin<2> LOC=AM23 | IOSTANDARD = LVCMOS15;
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| 33 | Net USERIO_dipsw_pin<3> LOC=AN23 | IOSTANDARD = LVCMOS15;
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| 34 | Net USERIO_pb_u_pin LOC=AM21 | IOSTANDARD = LVCMOS15;
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| 35 | Net USERIO_pb_m_pin LOC=AN22 | IOSTANDARD = LVCMOS15;
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| 36 | Net USERIO_pb_d_pin LOC=AP22 | IOSTANDARD = LVCMOS15;
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| 37 |
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| 38 | #USB UART on WARP v3 rev 1.1 |
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| 39 | Net UART_USB_TX_pin LOC = H9 | IOSTANDARD=LVCMOS25; #FT230X RXD pin |
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| 40 | Net UART_USB_RX_pin LOC = J9 | IOSTANDARD=LVCMOS25; #FT230X TXD pin |
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| 41 | |
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| 42 | #Debug pins 0, 1 for rev1.0 with off-board USB UART |
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| 43 | #Net UART_USB_RX_pin LOC = AG27 | IOSTANDARD=LVCMOS25; #debughdr0, FT230X TXD pin |
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| 44 | #Net UART_USB_TX_pin LOC = AE26 | IOSTANDARD=LVCMOS25; #debughdr1, FT230X RXD pin
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| 45 |
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| 46 | #IIC EEPROM
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| 47 | Net IIC_EEPROM_iic_sda_pin LOC = AG23 | IOSTANDARD=LVCMOS25;
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| 48 | Net IIC_EEPROM_iic_scl_pin LOC = AF23 | IOSTANDARD=LVCMOS25;
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| 49 |
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| 50 | #ETH A
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| 51 | Net ETH_A_TemacPhy_RST_n_pin LOC=L9 | IOSTANDARD = LVCMOS25 | TIG;
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| 52 | Net ETH_A_RGMII_TXD_0_pin<0> LOC=AF9 | IOSTANDARD = LVCMOS25;
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| 53 | Net ETH_A_RGMII_TXD_0_pin<1> LOC=AF10 | IOSTANDARD = LVCMOS25;
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| 54 | Net ETH_A_RGMII_TXD_0_pin<2> LOC=AD9 | IOSTANDARD = LVCMOS25;
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| 55 | Net ETH_A_RGMII_TXD_0_pin<3> LOC=AD10 | IOSTANDARD = LVCMOS25;
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| 56 | Net ETH_A_RGMII_TX_CTL_0_pin LOC=AG8 | IOSTANDARD = LVCMOS25;
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| 57 | Net ETH_A_RGMII_TXC_0_pin LOC=AE9 | IOSTANDARD = LVCMOS25;
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| 58 | Net ETH_A_RGMII_RXD_0_pin<0> LOC=AK9 | IOSTANDARD = LVCMOS25;
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| 59 | Net ETH_A_RGMII_RXD_0_pin<1> LOC=AJ9 | IOSTANDARD = LVCMOS25;
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| 60 | Net ETH_A_RGMII_RXD_0_pin<2> LOC=AH8 | IOSTANDARD = LVCMOS25;
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| 61 | Net ETH_A_RGMII_RXD_0_pin<3> LOC=AH9 | IOSTANDARD = LVCMOS25;
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| 62 | Net ETH_A_RGMII_RX_CTL_0_pin LOC=AL9 | IOSTANDARD = LVCMOS25;
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| 63 | Net ETH_A_RGMII_RXC_0_pin LOC=AC10 | IOSTANDARD = LVCMOS25;
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| 64 | Net ETH_A_MDC_0_pin LOC=AP9 | IOSTANDARD = LVCMOS25;
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| 65 | Net ETH_A_MDIO_0_pin LOC=AK8 | IOSTANDARD = LVCMOS25;
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| 66 |
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| 67 | #ETH B
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| 68 | Net ETH_B_RGMII_TXD_0_pin<0> LOC=M10 | IOSTANDARD = LVCMOS25;
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| 69 | Net ETH_B_RGMII_TXD_0_pin<1> LOC=B8 | IOSTANDARD = LVCMOS25;
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| 70 | Net ETH_B_RGMII_TXD_0_pin<2> LOC=AC9 | IOSTANDARD = LVCMOS25;
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| 71 | Net ETH_B_RGMII_TXD_0_pin<3> LOC=E9 | IOSTANDARD = LVCMOS25;
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| 72 | Net ETH_B_RGMII_TX_CTL_0_pin LOC=D10 | IOSTANDARD = LVCMOS25;
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| 73 | Net ETH_B_RGMII_TXC_0_pin LOC=AB10 | IOSTANDARD = LVCMOS25;
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| 74 | Net ETH_B_RGMII_RXD_0_pin<0> LOC=A9 | IOSTANDARD = LVCMOS25;
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| 75 | Net ETH_B_RGMII_RXD_0_pin<1> LOC=D9 | IOSTANDARD = LVCMOS25;
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| 76 | Net ETH_B_RGMII_RXD_0_pin<2> LOC=C9 | IOSTANDARD = LVCMOS25;
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| 77 | Net ETH_B_RGMII_RXD_0_pin<3> LOC=F10 | IOSTANDARD = LVCMOS25;
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| 78 | Net ETH_B_RGMII_RX_CTL_0_pin LOC=A8 | IOSTANDARD = LVCMOS25;
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| 79 | Net ETH_B_RGMII_RXC_0_pin LOC=L10 | IOSTANDARD = LVCMOS25;
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| 80 | Net ETH_B_MDC_0_pin LOC=AN9 | IOSTANDARD = LVCMOS25;
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| 81 | Net ETH_B_MDIO_0_pin LOC=AL8 | IOSTANDARD = LVCMOS25;
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| 82 |
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| 83 | #DDR3 SO-DIMM
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| 84 | Net DDR3_2GB_SODIMM_Clk_pin LOC=AC15 | IOSTANDARD = DIFF_SSTL15;
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| 85 | Net DDR3_2GB_SODIMM_Clk_n_pin LOC=AD15 | IOSTANDARD = DIFF_SSTL15;
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| 86 | Net DDR3_2GB_SODIMM_CE_pin LOC=AF18 | IOSTANDARD = SSTL15;
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| 87 | Net DDR3_2GB_SODIMM_CS_n_pin LOC=AL16 | IOSTANDARD = SSTL15;
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| 88 | Net DDR3_2GB_SODIMM_ODT_pin LOC=AP15 | IOSTANDARD = SSTL15;
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| 89 | Net DDR3_2GB_SODIMM_RAS_n_pin LOC=AM16 | IOSTANDARD = SSTL15;
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| 90 | Net DDR3_2GB_SODIMM_CAS_n_pin LOC=AJ17 | IOSTANDARD = SSTL15;
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| 91 | Net DDR3_2GB_SODIMM_WE_n_pin LOC=AF15 | IOSTANDARD = SSTL15;
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| 92 | Net DDR3_2GB_SODIMM_BankAddr_pin<0> LOC=AG15 | IOSTANDARD = SSTL15;
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| 93 | Net DDR3_2GB_SODIMM_BankAddr_pin<1> LOC=AP16 | IOSTANDARD = SSTL15;
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| 94 | Net DDR3_2GB_SODIMM_BankAddr_pin<2> LOC=AD17 | IOSTANDARD = SSTL15;
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| 95 | Net DDR3_2GB_SODIMM_Addr_pin<0> LOC=AM17 | IOSTANDARD = SSTL15;
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| 96 | Net DDR3_2GB_SODIMM_Addr_pin<1> LOC=AF16 | IOSTANDARD = SSTL15;
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| 97 | Net DDR3_2GB_SODIMM_Addr_pin<2> LOC=AN17 | IOSTANDARD = SSTL15;
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| 98 | Net DDR3_2GB_SODIMM_Addr_pin<3> LOC=AG17 | IOSTANDARD = SSTL15;
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| 99 | Net DDR3_2GB_SODIMM_Addr_pin<4> LOC=AK16 | IOSTANDARD = SSTL15;
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| 100 | Net DDR3_2GB_SODIMM_Addr_pin<5> LOC=AG16 | IOSTANDARD = SSTL15;
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| 101 | Net DDR3_2GB_SODIMM_Addr_pin<6> LOC=AK17 | IOSTANDARD = SSTL15;
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| 102 | Net DDR3_2GB_SODIMM_Addr_pin<7> LOC=AG18 | IOSTANDARD = SSTL15;
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| 103 | Net DDR3_2GB_SODIMM_Addr_pin<8> LOC=AE16 | IOSTANDARD = SSTL15;
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| 104 | Net DDR3_2GB_SODIMM_Addr_pin<9> LOC=AD16 | IOSTANDARD = SSTL15;
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| 105 | Net DDR3_2GB_SODIMM_Addr_pin<10> LOC=AH15 | IOSTANDARD = SSTL15;
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| 106 | Net DDR3_2GB_SODIMM_Addr_pin<11> LOC=AH18 | IOSTANDARD = SSTL15;
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| 107 | Net DDR3_2GB_SODIMM_Addr_pin<12> LOC=AE17 | IOSTANDARD = SSTL15;
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| 108 | Net DDR3_2GB_SODIMM_Addr_pin<13> LOC=AJ16 | IOSTANDARD = SSTL15;
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| 109 | Net DDR3_2GB_SODIMM_Addr_pin<14> LOC=AK18 | IOSTANDARD = SSTL15;
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| 110 | Net DDR3_2GB_SODIMM_DQ_pin<0> LOC=AK29 | IOSTANDARD = SSTL15_T_DCI;
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| 111 | Net DDR3_2GB_SODIMM_DQ_pin<1> LOC=AN30 | IOSTANDARD = SSTL15_T_DCI;
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| 112 | Net DDR3_2GB_SODIMM_DQ_pin<2> LOC=AL29 | IOSTANDARD = SSTL15_T_DCI;
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| 113 | Net DDR3_2GB_SODIMM_DQ_pin<3> LOC=AN29 | IOSTANDARD = SSTL15_T_DCI;
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| 114 | Net DDR3_2GB_SODIMM_DQ_pin<4> LOC=AP31 | IOSTANDARD = SSTL15_T_DCI;
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| 115 | Net DDR3_2GB_SODIMM_DQ_pin<5> LOC=AP30 | IOSTANDARD = SSTL15_T_DCI;
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| 116 | Net DDR3_2GB_SODIMM_DQ_pin<6> LOC=AH28 | IOSTANDARD = SSTL15_T_DCI;
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| 117 | Net DDR3_2GB_SODIMM_DQ_pin<7> LOC=AH27 | IOSTANDARD = SSTL15_T_DCI;
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| 118 | Net DDR3_2GB_SODIMM_DQ_pin<8> LOC=AK28 | IOSTANDARD = SSTL15_T_DCI;
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| 119 | Net DDR3_2GB_SODIMM_DQ_pin<9> LOC=AL28 | IOSTANDARD = SSTL15_T_DCI;
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| 120 | Net DDR3_2GB_SODIMM_DQ_pin<10> LOC=AJ27 | IOSTANDARD = SSTL15_T_DCI;
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| 121 | Net DDR3_2GB_SODIMM_DQ_pin<11> LOC=AH25 | IOSTANDARD = SSTL15_T_DCI;
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| 122 | Net DDR3_2GB_SODIMM_DQ_pin<12> LOC=AP29 | IOSTANDARD = SSTL15_T_DCI;
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| 123 | Net DDR3_2GB_SODIMM_DQ_pin<13> LOC=AM27 | IOSTANDARD = SSTL15_T_DCI;
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| 124 | Net DDR3_2GB_SODIMM_DQ_pin<14> LOC=AJ25 | IOSTANDARD = SSTL15_T_DCI;
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| 125 | Net DDR3_2GB_SODIMM_DQ_pin<15> LOC=AH24 | IOSTANDARD = SSTL15_T_DCI;
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| 126 | Net DDR3_2GB_SODIMM_DQ_pin<16> LOC=AJ24 | IOSTANDARD = SSTL15_T_DCI;
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| 127 | Net DDR3_2GB_SODIMM_DQ_pin<17> LOC=AK24 | IOSTANDARD = SSTL15_T_DCI;
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| 128 | Net DDR3_2GB_SODIMM_DQ_pin<18> LOC=AL24 | IOSTANDARD = SSTL15_T_DCI;
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| 129 | Net DDR3_2GB_SODIMM_DQ_pin<19> LOC=AK23 | IOSTANDARD = SSTL15_T_DCI;
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| 130 | Net DDR3_2GB_SODIMM_DQ_pin<20> LOC=AP27 | IOSTANDARD = SSTL15_T_DCI;
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| 131 | Net DDR3_2GB_SODIMM_DQ_pin<21> LOC=AM26 | IOSTANDARD = SSTL15_T_DCI;
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| 132 | Net DDR3_2GB_SODIMM_DQ_pin<22> LOC=AN25 | IOSTANDARD = SSTL15_T_DCI;
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| 133 | Net DDR3_2GB_SODIMM_DQ_pin<23> LOC=AN24 | IOSTANDARD = SSTL15_T_DCI;
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| 134 | Net DDR3_2GB_SODIMM_DQ_pin<24> LOC=AD21 | IOSTANDARD = SSTL15_T_DCI;
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| 135 | Net DDR3_2GB_SODIMM_DQ_pin<25> LOC=AE21 | IOSTANDARD = SSTL15_T_DCI;
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| 136 | Net DDR3_2GB_SODIMM_DQ_pin<26> LOC=AK22 | IOSTANDARD = SSTL15_T_DCI;
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| 137 | Net DDR3_2GB_SODIMM_DQ_pin<27> LOC=AL18 | IOSTANDARD = SSTL15_T_DCI;
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| 138 | Net DDR3_2GB_SODIMM_DQ_pin<28> LOC=AN19 | IOSTANDARD = SSTL15_T_DCI;
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| 139 | Net DDR3_2GB_SODIMM_DQ_pin<29> LOC=AP19 | IOSTANDARD = SSTL15_T_DCI;
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| 140 | Net DDR3_2GB_SODIMM_DQ_pin<30> LOC=AM18 | IOSTANDARD = SSTL15_T_DCI;
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| 141 | Net DDR3_2GB_SODIMM_DQ_pin<31> LOC=AN18 | IOSTANDARD = SSTL15_T_DCI;
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| 142 | Net DDR3_2GB_SODIMM_DM_pin<0> LOC=AM30 | IOSTANDARD = SSTL15;
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| 143 | Net DDR3_2GB_SODIMM_DM_pin<1> LOC=AL26 | IOSTANDARD = SSTL15;
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| 144 | Net DDR3_2GB_SODIMM_DM_pin<2> LOC=AP26 | IOSTANDARD = SSTL15;
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| 145 | Net DDR3_2GB_SODIMM_DM_pin<3> LOC=AJ22 | IOSTANDARD = SSTL15;
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| 146 | Net DDR3_2GB_SODIMM_Reset_n_pin LOC=AP17 | IOSTANDARD = SSTL15;
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| 147 | Net DDR3_2GB_SODIMM_DQS_pin<0> LOC=AG25 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 148 | Net DDR3_2GB_SODIMM_DQS_pin<1> LOC=AN28 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 149 | Net DDR3_2GB_SODIMM_DQS_pin<2> LOC=AM25 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 150 | Net DDR3_2GB_SODIMM_DQS_pin<3> LOC=AG22 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 151 | Net DDR3_2GB_SODIMM_DQS_n_pin<0> LOC=AG26 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 152 | Net DDR3_2GB_SODIMM_DQS_n_pin<1> LOC=AM28 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 153 | Net DDR3_2GB_SODIMM_DQS_n_pin<2> LOC=AL25 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 154 | Net DDR3_2GB_SODIMM_DQS_n_pin<3> LOC=AH22 | IOSTANDARD = DIFF_SSTL15_T_DCI;
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| 155 |
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| 156 | #System clock (80MHz, from sampling clock buffer)
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| 157 | NET samp_clk_n_pin LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
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| 158 | NET samp_clk_p_pin LOC = U23 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
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| 159 | Net samp_clk_p_pin TNM_NET = samp_clk_pin;
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| 160 | TIMESPEC TS_samp_clk_pin = PERIOD samp_clk_pin 80000 kHz;
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| 161 |
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| 162 | #System clock (200MHz, from LVDS oscillator)
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| 163 | Net osc200_p_pin LOC = A10 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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| 164 | Net osc200_n_pin LOC = B10 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE;
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| 165 | Net osc200_p_pin TNM_NET = osc200_p_pin;
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| 166 | TIMESPEC TS_osc200_p_pin = PERIOD osc200_p_pin 200000 kHz;
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| 167 |
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| 168 | #Processor reset (RESET button on board)
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| 169 | Net rst_1_sys_rst_pin LOC = AH13 | IOSTANDARD=LVCMOS15 | TIG;
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| 170 | Net rst_1_sys_rst_pin TIG;
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| 171 |
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| 172 | INST clock_generator_MPMC_Clocks/*/MMCM0_INST*/MMCM_ADV_inst LOC = MMCM_ADV_X0Y2;
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| 173 |
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| 174 | ####################################### |
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| 175 | #MAX2829 transceivers and RF front end |
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| 176 | NET RFA_SPI_SCLK_pin LOC=T34 | IOSTANDARD=LVCMOS25; |
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| 177 | NET RFA_SPI_MOSI_pin LOC=T33 | IOSTANDARD=LVCMOS25; |
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| 178 | NET RFA_SPI_CSn_pin LOC=U32 | IOSTANDARD=LVCMOS25; |
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| 179 | NET RFA_SHDN_pin LOC=U27 | IOSTANDARD=LVCMOS25; |
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| 180 | NET RFA_TxEn_pin LOC=T31 | IOSTANDARD=LVCMOS25; |
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| 181 | NET RFA_RxEn_pin LOC=U33 | IOSTANDARD=LVCMOS25; |
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| 182 | NET RFA_RxHP_pin LOC=AG32 | IOSTANDARD=LVCMOS25; |
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| 183 | NET RFA_PAEn_24_pin LOC=U25 | IOSTANDARD=LVCMOS25; |
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| 184 | NET RFA_PAEn_5_pin LOC=U28 | IOSTANDARD=LVCMOS25; |
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| 185 | NET RFA_ANTSW_pin<0> LOC=U31 | IOSTANDARD=LVCMOS25; |
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| 186 | NET RFA_ANTSW_pin<1> LOC=U30 | IOSTANDARD=LVCMOS25; |
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| 187 | NET RFA_LD_pin LOC=U26 | IOSTANDARD=LVCMOS25; |
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| 188 | NET RFA_B_pin<0> LOC=AG33 | IOSTANDARD=LVCMOS25;
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| 189 | NET RFA_B_pin<1> LOC=AF31 | IOSTANDARD=LVCMOS25;
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| 190 | NET RFA_B_pin<2> LOC=AF33 | IOSTANDARD=LVCMOS25;
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| 191 | NET RFA_B_pin<3> LOC=AG31 | IOSTANDARD=LVCMOS25;
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| 192 | NET RFA_B_pin<4> LOC=AF34 | IOSTANDARD=LVCMOS25;
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| 193 | NET RFA_B_pin<5> LOC=AE33 | IOSTANDARD=LVCMOS25;
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| 194 | NET RFA_B_pin<6> LOC=AE34 | IOSTANDARD=LVCMOS25;
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| 195 | |
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| 196 | NET RFB_SPI_SCLK_pin LOC=H34 | IOSTANDARD=LVCMOS25; |
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| 197 | NET RFB_SPI_MOSI_pin LOC=H33 | IOSTANDARD=LVCMOS25; |
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| 198 | NET RFB_SPI_CSn_pin LOC=J32 | IOSTANDARD=LVCMOS25; |
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| 199 | NET RFB_SHDN_pin LOC=J34 | IOSTANDARD=LVCMOS25; |
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| 200 | NET RFB_TxEn_pin LOC=H32 | IOSTANDARD=LVCMOS25; |
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| 201 | NET RFB_RxEn_pin LOC=J31 | IOSTANDARD=LVCMOS25; |
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| 202 | NET RFB_RxHP_pin LOC=R28 | IOSTANDARD=LVCMOS25; |
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| 203 | NET RFB_PAEn_24_pin LOC=T25 | IOSTANDARD=LVCMOS25; |
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| 204 | NET RFB_PAEn_5_pin LOC=T28 | IOSTANDARD=LVCMOS25; |
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| 205 | NET RFB_ANTSW_pin<0> LOC=T30 | IOSTANDARD=LVCMOS25; |
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| 206 | NET RFB_ANTSW_pin<1> LOC=T29 | IOSTANDARD=LVCMOS25; |
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| 207 | NET RFB_LD_pin LOC=K33 | IOSTANDARD=LVCMOS25; |
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| 208 | NET RFB_B_pin<0> LOC=P27 | IOSTANDARD=LVCMOS25;
|
|---|
| 209 | NET RFB_B_pin<1> LOC=R27 | IOSTANDARD=LVCMOS25;
|
|---|
| 210 | NET RFB_B_pin<2> LOC=R29 | IOSTANDARD=LVCMOS25;
|
|---|
| 211 | NET RFB_B_pin<3> LOC=R26 | IOSTANDARD=LVCMOS25;
|
|---|
| 212 | NET RFB_B_pin<4> LOC=R32 | IOSTANDARD=LVCMOS25;
|
|---|
| 213 | NET RFB_B_pin<5> LOC=T26 | IOSTANDARD=LVCMOS25;
|
|---|
| 214 | NET RFB_B_pin<6> LOC=R31 | IOSTANDARD=LVCMOS25;
|
|---|
| 215 |
|
|---|
| 216 | NET RFA_AD_spi_sclk_pin LOC = AB33 | IOSTANDARD = LVCMOS25;# |
|---|
| 217 | NET RFA_AD_spi_sdio LOC = AC30 | IOSTANDARD = LVCMOS25;# |
|---|
| 218 | NET RFA_AD_spi_cs_n_pin LOC = AB31 | IOSTANDARD = LVCMOS25;# |
|---|
| 219 | NET RFA_AD_reset_n_pin LOC = AA34 | IOSTANDARD = LVCMOS25;# |
|---|
| 220 | |
|---|
| 221 | NET RFB_AD_spi_sclk_pin LOC = P32 | IOSTANDARD = LVCMOS25;# |
|---|
| 222 | NET RFB_AD_spi_sdio LOC = P34 | IOSTANDARD = LVCMOS25;# |
|---|
| 223 | NET RFB_AD_spi_cs_n_pin LOC = N32 | IOSTANDARD = LVCMOS25;# |
|---|
| 224 | NET RFB_AD_reset_n_pin LOC = N34 | IOSTANDARD = LVCMOS25;# |
|---|
| 225 | |
|---|
| 226 | NET clk_rfref_spi_sclk_pin LOC = V25 | IOSTANDARD = LVCMOS25;# |
|---|
| 227 | NET clk_rfref_spi_mosi_pin LOC = W25 | IOSTANDARD = LVCMOS25;# |
|---|
| 228 | NET clk_rfref_spi_cs_n_pin LOC = W27 | IOSTANDARD = LVCMOS25;# |
|---|
| 229 | NET clk_rfref_spi_miso_pin LOC = Y27 | IOSTANDARD = LVCMOS25;# |
|---|
| 230 | NET clk_rfref_func_pin LOC = L26 | IOSTANDARD = LVCMOS25; |
|---|
| 231 | |
|---|
| 232 | NET clk_samp_spi_sclk_pin LOC = W32 | IOSTANDARD = LVCMOS25;# |
|---|
| 233 | NET clk_samp_spi_mosi_pin LOC = Y29 | IOSTANDARD = LVCMOS25;# |
|---|
| 234 | NET clk_samp_spi_cs_n_pin LOC = W31 | IOSTANDARD = LVCMOS25;# |
|---|
| 235 | NET clk_samp_spi_miso_pin LOC = Y28 | IOSTANDARD = LVCMOS25;# |
|---|
| 236 | NET clk_samp_func_pin LOC = R33 | IOSTANDARD = LVCMOS25;# |
|---|
| 237 |
|
|---|
| 238 | #TRXCLK pins driven by AD9963's; assuming 80MHz worst case
|
|---|
| 239 | Net RFA_AD_TRXCLK TNM_NET = RFA_AD_TRXCLK;
|
|---|
| 240 | TIMESPEC TS_RFA_AD_TRXCLK = PERIOD RFA_AD_TRXCLK 80 MHz;
|
|---|
| 241 |
|
|---|
| 242 | Net RFB_AD_TRXCLK TNM_NET = RFB_AD_TRXCLK;
|
|---|
| 243 | TIMESPEC TS_RFB_AD_TRXCLK = PERIOD RFB_AD_TRXCLK 80 MHz;
|
|---|
| 244 |
|
|---|
| 245 | #RFA AD9963
|
|---|
| 246 | NET RFA_AD_TRXD<0> LOC = AC25 | IOSTANDARD = LVCMOS25;
|
|---|
| 247 | NET RFA_AD_TRXD<1> LOC = AB25 | IOSTANDARD = LVCMOS25;
|
|---|
| 248 | NET RFA_AD_TRXD<2> LOC = AB32 | IOSTANDARD = LVCMOS25;
|
|---|
| 249 | NET RFA_AD_TRXD<3> LOC = AC29 | IOSTANDARD = LVCMOS25;
|
|---|
| 250 | NET RFA_AD_TRXD<4> LOC = AD29 | IOSTANDARD = LVCMOS25;
|
|---|
| 251 | NET RFA_AD_TRXD<5> LOC = AC33 | IOSTANDARD = LVCMOS25;
|
|---|
| 252 | NET RFA_AD_TRXD<6> LOC = AD34 | IOSTANDARD = LVCMOS25;
|
|---|
| 253 | NET RFA_AD_TRXD<7> LOC = AC32 | IOSTANDARD = LVCMOS25;
|
|---|
| 254 | NET RFA_AD_TRXD<8> LOC = AD31 | IOSTANDARD = LVCMOS25;
|
|---|
| 255 | NET RFA_AD_TRXD<9> LOC = AD32 | IOSTANDARD = LVCMOS25;
|
|---|
| 256 | NET RFA_AD_TRXD<10> LOC = AE31 | IOSTANDARD = LVCMOS25;
|
|---|
| 257 | NET RFA_AD_TRXD<11> LOC = AE32 | IOSTANDARD = LVCMOS25;
|
|---|
| 258 |
|
|---|
| 259 | NET RFA_AD_TRXCLK LOC = AD30 | IOSTANDARD = LVCMOS25;
|
|---|
| 260 | NET RFA_AD_TRXIQ LOC = AC34 | IOSTANDARD = LVCMOS25;
|
|---|
| 261 |
|
|---|
| 262 | NET RFA_AD_TXCLK LOC = AA31 | IOSTANDARD = LVCMOS25;
|
|---|
| 263 | NET RFA_AD_TXIQ LOC = AA33 | IOSTANDARD = LVCMOS25;
|
|---|
| 264 |
|
|---|
| 265 | NET RFA_AD_TXD<0> LOC = AA25 | IOSTANDARD = LVCMOS25;
|
|---|
| 266 | NET RFA_AD_TXD<1> LOC = AB26 | IOSTANDARD = LVCMOS25;
|
|---|
| 267 | NET RFA_AD_TXD<2> LOC = Y26 | IOSTANDARD = LVCMOS25;
|
|---|
| 268 | NET RFA_AD_TXD<3> LOC = AA26 | IOSTANDARD = LVCMOS25;
|
|---|
| 269 | NET RFA_AD_TXD<4> LOC = AA28 | IOSTANDARD = LVCMOS25;
|
|---|
| 270 | NET RFA_AD_TXD<5> LOC = AA29 | IOSTANDARD = LVCMOS25;
|
|---|
| 271 | NET RFA_AD_TXD<6> LOC = AA30 | IOSTANDARD = LVCMOS25;
|
|---|
| 272 | NET RFA_AD_TXD<7> LOC = AB30 | IOSTANDARD = LVCMOS25;
|
|---|
| 273 | NET RFA_AD_TXD<8> LOC = AB28 | IOSTANDARD = LVCMOS25;
|
|---|
| 274 | NET RFA_AD_TXD<9> LOC = AB27 | IOSTANDARD = LVCMOS25;
|
|---|
| 275 | NET RFA_AD_TXD<10> LOC = AC28 | IOSTANDARD = LVCMOS25;
|
|---|
| 276 | NET RFA_AD_TXD<11> LOC = AC27 | IOSTANDARD = LVCMOS25;
|
|---|
| 277 |
|
|---|
| 278 | #RFB
|
|---|
| 279 | NET RFB_AD_TRXD<0> LOC = N25 | IOSTANDARD = LVCMOS25;
|
|---|
| 280 | NET RFB_AD_TRXD<1> LOC = M25 | IOSTANDARD = LVCMOS25;
|
|---|
| 281 | NET RFB_AD_TRXD<2> LOC = N28 | IOSTANDARD = LVCMOS25;
|
|---|
| 282 | NET RFB_AD_TRXD<3> LOC = N27 | IOSTANDARD = LVCMOS25;
|
|---|
| 283 | NET RFB_AD_TRXD<4> LOC = P29 | IOSTANDARD = LVCMOS25;
|
|---|
| 284 | NET RFB_AD_TRXD<5> LOC = M30 | IOSTANDARD = LVCMOS25;
|
|---|
| 285 | NET RFB_AD_TRXD<6> LOC = N30 | IOSTANDARD = LVCMOS25;
|
|---|
| 286 | NET RFB_AD_TRXD<7> LOC = N29 | IOSTANDARD = LVCMOS25;
|
|---|
| 287 | NET RFB_AD_TRXD<8> LOC = P26 | IOSTANDARD = LVCMOS25;
|
|---|
| 288 | NET RFB_AD_TRXD<9> LOC = P31 | IOSTANDARD = LVCMOS25;
|
|---|
| 289 | NET RFB_AD_TRXD<10> LOC = P25 | IOSTANDARD = LVCMOS25;
|
|---|
| 290 | NET RFB_AD_TRXD<11> LOC = P30 | IOSTANDARD = LVCMOS25;
|
|---|
| 291 |
|
|---|
| 292 | NET RFB_AD_TRXCLK LOC = N33 | IOSTANDARD = LVCMOS25;
|
|---|
| 293 | NET RFB_AD_TRXIQ LOC = M33 | IOSTANDARD = LVCMOS25;
|
|---|
| 294 |
|
|---|
| 295 | NET RFB_AD_TXCLK LOC = L28 | IOSTANDARD = LVCMOS25; |
|---|
| 296 | NET RFB_AD_TXIQ LOC = L29 | IOSTANDARD = LVCMOS25; |
|---|
| 297 | |
|---|
| 298 | NET RFB_AD_TXD<0> LOC = K32 | IOSTANDARD = LVCMOS25; |
|---|
| 299 | NET RFB_AD_TXD<1> LOC = M26 | IOSTANDARD = LVCMOS25; |
|---|
| 300 | NET RFB_AD_TXD<2> LOC = M32 | IOSTANDARD = LVCMOS25; |
|---|
| 301 | NET RFB_AD_TXD<3> LOC = K34 | IOSTANDARD = LVCMOS25; |
|---|
| 302 | NET RFB_AD_TXD<4> LOC = M31 | IOSTANDARD = LVCMOS25; |
|---|
| 303 | NET RFB_AD_TXD<5> LOC = L30 | IOSTANDARD = LVCMOS25; |
|---|
| 304 | NET RFB_AD_TXD<6> LOC = L33 | IOSTANDARD = LVCMOS25; |
|---|
| 305 | NET RFB_AD_TXD<7> LOC = L31 | IOSTANDARD = LVCMOS25; |
|---|
| 306 | NET RFB_AD_TXD<8> LOC = M28 | IOSTANDARD = LVCMOS25; |
|---|
| 307 | NET RFB_AD_TXD<9> LOC = L34 | IOSTANDARD = LVCMOS25; |
|---|
| 308 | NET RFB_AD_TXD<10> LOC = M27 | IOSTANDARD = LVCMOS25; |
|---|
| 309 | NET RFB_AD_TXD<11> LOC = K31 | IOSTANDARD = LVCMOS25; |
|---|
| 310 |
|
|---|
| 311 | NET RF_RSSI_CLK LOC = B32 | IOSTANDARD = LVCMOS25; |
|---|
| 312 | NET RF_RSSI_PD LOC = B34 | IOSTANDARD = LVCMOS25; |
|---|
| 313 | NET RFB_RSSI_D<0> LOC = A33 | IOSTANDARD = LVCMOS25; |
|---|
| 314 | NET RFB_RSSI_D<1> LOC = B33 | IOSTANDARD = LVCMOS25; |
|---|
| 315 | NET RFB_RSSI_D<2> LOC = C33 | IOSTANDARD = LVCMOS25; |
|---|
| 316 | NET RFB_RSSI_D<3> LOC = C34 | IOSTANDARD = LVCMOS25; |
|---|
| 317 | NET RFB_RSSI_D<4> LOC = C32 | IOSTANDARD = LVCMOS25; |
|---|
| 318 | NET RFB_RSSI_D<5> LOC = D31 | IOSTANDARD = LVCMOS25; |
|---|
| 319 | NET RFB_RSSI_D<6> LOC = G30 | IOSTANDARD = LVCMOS25; |
|---|
| 320 | NET RFB_RSSI_D<7> LOC = E31 | IOSTANDARD = LVCMOS25; |
|---|
| 321 | NET RFB_RSSI_D<8> LOC = D32 | IOSTANDARD = LVCMOS25; |
|---|
| 322 | NET RFB_RSSI_D<9> LOC = D34 | IOSTANDARD = LVCMOS25; |
|---|
| 323 | NET RFA_RSSI_D<0> LOC = E32 | IOSTANDARD = LVCMOS25; |
|---|
| 324 | NET RFA_RSSI_D<1> LOC = E33 | IOSTANDARD = LVCMOS25; |
|---|
| 325 | NET RFA_RSSI_D<2> LOC = E34 | IOSTANDARD = LVCMOS25; |
|---|
| 326 | NET RFA_RSSI_D<3> LOC = F30 | IOSTANDARD = LVCMOS25; |
|---|
| 327 | NET RFA_RSSI_D<4> LOC = F31 | IOSTANDARD = LVCMOS25; |
|---|
| 328 | NET RFA_RSSI_D<5> LOC = F34 | IOSTANDARD = LVCMOS25; |
|---|
| 329 | NET RFA_RSSI_D<6> LOC = F33 | IOSTANDARD = LVCMOS25; |
|---|
| 330 | NET RFA_RSSI_D<7> LOC = G31 | IOSTANDARD = LVCMOS25; |
|---|
| 331 | NET RFA_RSSI_D<8> LOC = G33 | IOSTANDARD = LVCMOS25; |
|---|
| 332 | NET RFA_RSSI_D<9> LOC = G32 | IOSTANDARD = LVCMOS25; |
|---|
| 333 |
|
|---|
| 334 |
|
|---|
| 335 | ###### ETH_A |
|---|
| 336 | ###### Hard_Ethernet_MAC |
|---|
| 337 | # This is a RGMII system |
|---|
| 338 | # GTX_CLK_0 = 125MHz |
|---|
| 339 | # LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator |
|---|
| 340 | # Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods |
|---|
| 341 | # Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency |
|---|
| 342 | # allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, |
|---|
| 343 | # the constraints are over constrained. Relaxing them for your system may reduce build time. |
|---|
| 344 | |
|---|
| 345 | NET "*ETH_A*/hrst*" TIG; |
|---|
| 346 | |
|---|
| 347 | # Locate the Tri-Mode Ethernet MAC instance |
|---|
| 348 | INST "*ETH_A*v6_emac" LOC = "TEMAC_X0Y0"; |
|---|
| 349 | |
|---|
| 350 | ############################################################################### |
|---|
| 351 | # CLOCK CONSTRAINTS |
|---|
| 352 | # The following constraints are required. If you choose to not use the example |
|---|
| 353 | # design level of wrapper hierarchy, the net names should be translated to |
|---|
| 354 | # match your design. |
|---|
| 355 | ############################################################################### |
|---|
| 356 | |
|---|
| 357 | # Ethernet GTX_CLK high quality 125 MHz reference clock |
|---|
| 358 | NET "*/GTX_CLK_0" TNM_NET = "ref_gtx_clk"; #name of signal connected to TEMAC GTX_CLK_0 input |
|---|
| 359 | TIMEGRP "v6_emac_v1_3_clk_ref_gtx" = "ref_gtx_clk"; |
|---|
| 360 | TIMESPEC "TS_v6_emac_v1_3_clk_ref_gtx" = PERIOD "v6_emac_v1_3_clk_ref_gtx" 8 ns HIGH 50 %; #constant value based on constant 125 MHZ GTX clock |
|---|
| 361 | |
|---|
| 362 | # Ethernet RGMII PHY-side transmit clock |
|---|
| 363 | # Changed NET Name - Input to bufg_tx_0 |
|---|
| 364 | # ___________ |
|---|
| 365 | # | | |\ |
|---|
| 366 | # | Hard Core |--- tx_clk_0_o --| >---- Tx_Cl_Clk ----- |
|---|
| 367 | # |___________| |/ |
|---|
| 368 | # BUFG |
|---|
| 369 | # |
|---|
| 370 | NET "*ETH_A*/tx_cl_clk" TNM_NET = "A_phy_clk_tx"; |
|---|
| 371 | TIMEGRP "A_v6_emac_v1_3_clk_phy_tx" = "A_phy_clk_tx"; |
|---|
| 372 | TIMESPEC "TS_A_v6_emac_v1_3_clk_phy_tx" = PERIOD "A_v6_emac_v1_3_clk_phy_tx" 8 ns HIGH 50 %; |
|---|
| 373 | |
|---|
| 374 | # Ethernet RGMII PHY-side receive clock |
|---|
| 375 | # Changed NET Name |
|---|
| 376 | # RGMII_RXC_0 is the name of the clock net at the TEMAC Port |
|---|
| 377 | # It is the input to the IODELAY |
|---|
| 378 | # RxClientClk_0 is the name of the BUFG output clock net |
|---|
| 379 | # |
|---|
| 380 | # _________ BUFR |
|---|
| 381 | # | | |\ |
|---|
| 382 | # ---RGMII_RXC_0----| IODELAY |------| >----RxClientClk_0------------ |
|---|
| 383 | # |_________| |/ |
|---|
| 384 | # |
|---|
| 385 | NET "ETH_A_RGMII_RXC_0_pin" TNM_NET = "A_phy_clk_rx"; |
|---|
| 386 | TIMEGRP "A_v6_emac_v1_3_clk_phy_rx" = "A_phy_clk_rx"; |
|---|
| 387 | TIMESPEC "TS_A_v6_emac_v1_3_clk_phy_rx" = PERIOD "A_v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %; |
|---|
| 388 | |
|---|
| 389 | # IDELAYCTRL 200 MHz reference clock |
|---|
| 390 | NET "clk_200*MHz*" TNM_NET = "clk_ref_clk"; #name of signal connected to TEMAC REFCLK input |
|---|
| 391 | TIMEGRP "ref_clk" = "clk_ref_clk"; |
|---|
| 392 | TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50 %; #constant value based on constant 200 MHZ ref clock |
|---|
| 393 | |
|---|
| 394 | # Constrain the DCR interface clock to an example frequency of 100 MHz |
|---|
| 395 | # Changed NET Name |
|---|
| 396 | # NET "DCREMACCLK" TNM_NET = "host_clock"; |
|---|
| 397 | #NET "*ETH_A*/SPLB_CLK" TNM_NET = "host_clock"; |
|---|
| 398 | #TIMEGRP "A_clk_host" = "A_host_clock"; |
|---|
| 399 | #TIMESPEC "TS_A_clk_host" = PERIOD "A_clk_host" 10 ns HIGH 50 %; |
|---|
| 400 | |
|---|
| 401 | ############################################################################### |
|---|
| 402 | # PHYSICAL INTERFACE CONSTRAINTS |
|---|
| 403 | # The following constraints are necessary for proper operation, and are tuned |
|---|
| 404 | # for this example design. They should be modified to suit your design. |
|---|
| 405 | ############################################################################### |
|---|
| 406 | |
|---|
| 407 | # RGMII physical interface constraints |
|---|
| 408 | # ----------------------------------------------------------------------------- |
|---|
| 409 | |
|---|
| 410 | # Set the IDELAY and ODELAY values, tuned for this example design. |
|---|
| 411 | # These values should be modified to suit your design. |
|---|
| 412 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
|---|
| 413 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
|---|
| 414 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
|---|
| 415 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
|---|
| 416 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
|---|
| 417 | |
|---|
| 418 | INST "*ETH_A*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
|---|
| 419 | INST "*ETH_A*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
|---|
| 420 | INST "*ETH_A*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
|---|
| 421 | INST "*ETH_A*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
|---|
| 422 | INST "*ETH_A*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
|---|
| 423 | |
|---|
| 424 | INST "*ETH_A*rgmii_rxc0_delay" IDELAY_VALUE = 0; |
|---|
| 425 | INST "*ETH_A*rgmii_rxc0_delay" SIGNAL_PATTERN = CLOCK; |
|---|
| 426 | |
|---|
| 427 | INST "*ETH_A*rgmii?rgmii_tx_clk_delay" ODELAY_VALUE = 6; |
|---|
| 428 | INST "*ETH_A*rgmii?rgmii_tx_clk_delay" SIGNAL_PATTERN = CLOCK; |
|---|
| 429 | |
|---|
| 430 | # Group all IODELAY-related blocks to use a single IDELAYCTRL |
|---|
| 431 | |
|---|
| 432 | # Change - added TNMs for trace length variations |
|---|
| 433 | INST "ETH_A_RGMII_RXD_0_pin[0]" TNM = "A_rgmii_rx_d0"; |
|---|
| 434 | INST "ETH_A_RGMII_RXD_0_pin[1]" TNM = "A_rgmii_rx_d1"; |
|---|
| 435 | INST "ETH_A_RGMII_RXD_0_pin[2]" TNM = "A_rgmii_rx_d2"; |
|---|
| 436 | INST "ETH_A_RGMII_RXD_0_pin[3]" TNM = "A_rgmii_rx_d3"; |
|---|
| 437 | INST "ETH_A_RGMII_RX_CTL_0_pin" TNM = "A_rgmii_rx_ctrl"; |
|---|
| 438 | |
|---|
| 439 | # Spec: 1.2ns setup time, 1.2ns hold time |
|---|
| 440 | # The internal PHY delays were not used to derive the OFFSET constraints |
|---|
| 441 | # Changed NET Name |
|---|
| 442 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock |
|---|
| 443 | # Therefore the offset in constraint must have less setup time than nominal |
|---|
| 444 | TIMEGRP "A_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
|---|
| 445 | TIMEGRP "A_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
|---|
| 446 | |
|---|
| 447 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock |
|---|
| 448 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 449 | TIMEGRP "A_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
|---|
| 450 | TIMEGRP "A_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
|---|
| 451 | |
|---|
| 452 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock |
|---|
| 453 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 454 | TIMEGRP "A_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
|---|
| 455 | TIMEGRP "A_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
|---|
| 456 | |
|---|
| 457 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock |
|---|
| 458 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 459 | TIMEGRP "A_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
|---|
| 460 | TIMEGRP "A_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
|---|
| 461 | |
|---|
| 462 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock |
|---|
| 463 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 464 | TIMEGRP "A_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
|---|
| 465 | TIMEGRP "A_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
|---|
| 466 | |
|---|
| 467 | |
|---|
| 468 | NET "*ETH_A*/LlinkTemac0_CLK" TNM_NET = "A_LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input |
|---|
| 469 | NET "*ETH_A*/SPLB_Clk" TNM_NET = "A_PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input |
|---|
| 470 | NET "*ETH_A*/REFCLK" TNM_NET = "A_REFCLK"; #name of signal connected to TEMAC REFCLK input |
|---|
| 471 | |
|---|
| 472 | TIMESPEC "TS_A_LL_CLK0_2_RX_CLIENT_CLK0" = FROM A_LLCLK0 TO A_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
|---|
| 473 | TIMESPEC "TS_A_LL_CLK0_2_TX_CLIENT_CLK0" = FROM A_LLCLK0 TO A_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
|---|
| 474 | TIMESPEC "TS_A_RX_CLIENT_CLK0_2_LL_CLK0" = FROM A_phy_clk_rx TO A_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
|---|
| 475 | TIMESPEC "TS_A_TX_CLIENT_CLK0_2_LL_CLK0" = FROM A_phy_clk_tx TO A_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
|---|
| 476 | |
|---|
| 477 | TIMESPEC "TS_A_REF_CLK_2_PLB_CLIENT_CLK" = FROM A_REFCLK TO A_PLBCLK 8000 ps DATAPATHONLY; #varies based on period of PLB clock |
|---|
| 478 | TIMESPEC "TS_A_PLB_CLIENT_CLK_2_REF_CLK" = FROM A_PLBCLK TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock |
|---|
| 479 | |
|---|
| 480 | TIMESPEC "TS_A_REF_CLK_2_TX_CLIENT_CLK0" = FROM A_REFCLK TO A_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
|---|
| 481 | TIMESPEC "TS_A_TX_CLIENT_CLK0_2_REF_CLK" = FROM A_phy_clk_tx TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock |
|---|
| 482 | |
|---|
| 483 | TIMESPEC "TS_A_REF_CLK_2_RX_CLIENT_CLK0" = FROM A_REFCLK TO A_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
|---|
| 484 | TIMESPEC "TS_A_RX_CLIENT_CLK0_2_REF_CLK" = FROM A_phy_clk_rx TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock |
|---|
| 485 | |
|---|
| 486 | |
|---|
| 487 | |
|---|
| 488 | ###### ETH_B |
|---|
| 489 | ###### Hard_Ethernet_MAC |
|---|
| 490 | # This is a RGMII system |
|---|
| 491 | # GTX_CLK_0 = 125MHz |
|---|
| 492 | # LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator |
|---|
| 493 | # Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods |
|---|
| 494 | # Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency |
|---|
| 495 | # allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, |
|---|
| 496 | # the constraints are over constrained. Relaxing them for your system may reduce build time. |
|---|
| 497 | |
|---|
| 498 | NET "*ETH_B*/hrst*" TIG; |
|---|
| 499 | |
|---|
| 500 | # Locate the Tri-Mode Ethernet MAC instance |
|---|
| 501 | INST "*ETH_B*v6_emac" LOC = "TEMAC_X0Y1"; |
|---|
| 502 | |
|---|
| 503 | ############################################################################### |
|---|
| 504 | # CLOCK CONSTRAINTS |
|---|
| 505 | # The following constraints are required. If you choose to not use the example |
|---|
| 506 | # design level of wrapper hierarchy, the net names should be translated to |
|---|
| 507 | # match your design. |
|---|
| 508 | ############################################################################### |
|---|
| 509 | |
|---|
| 510 | # Ethernet RGMII PHY-side transmit clock |
|---|
| 511 | # Changed NET Name - Input to bufg_tx_0 |
|---|
| 512 | # ___________ |
|---|
| 513 | # | | |\ |
|---|
| 514 | # | Hard Core |--- tx_clk_0_o --| >---- Tx_Cl_Clk ----- |
|---|
| 515 | # |___________| |/ |
|---|
| 516 | # BUFG |
|---|
| 517 | # |
|---|
| 518 | NET "*ETH_B*/tx_cl_clk" TNM_NET = "B_phy_clk_tx"; |
|---|
| 519 | TIMEGRP "B_v6_emac_v1_3_clk_phy_tx" = "B_phy_clk_tx"; |
|---|
| 520 | TIMESPEC "TS_B_v6_emac_v1_3_clk_phy_tx" = PERIOD "B_v6_emac_v1_3_clk_phy_tx" 8 ns HIGH 50 %; |
|---|
| 521 | |
|---|
| 522 | # Ethernet RGMII PHY-side receive clock |
|---|
| 523 | # Changed NET Name |
|---|
| 524 | # RGMII_RXC_0 is the name of the clock net at the TEMAC Port |
|---|
| 525 | # It is the input to the IODELAY |
|---|
| 526 | # RxClientClk_0 is the name of the BUFG output clock net |
|---|
| 527 | # |
|---|
| 528 | # _________ BUFR |
|---|
| 529 | # | | |\ |
|---|
| 530 | # ---RGMII_RXC_0----| IODELAY |------| >----RxClientClk_0------------ |
|---|
| 531 | # |_________| |/ |
|---|
| 532 | # |
|---|
| 533 | NET "ETH_B_RGMII_RXC_0_pin" TNM_NET = "B_phy_clk_rx"; |
|---|
| 534 | TIMEGRP "B_v6_emac_v1_3_clk_phy_rx" = "B_phy_clk_rx"; |
|---|
| 535 | TIMESPEC "TS_B_v6_emac_v1_3_clk_phy_rx" = PERIOD "B_v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %; |
|---|
| 536 | |
|---|
| 537 | # Constrain the DCR interface clock to an example frequency of 100 MHz |
|---|
| 538 | # Changed NET Name |
|---|
| 539 | # NET "DCREMACCLK" TNM_NET = "host_clock"; |
|---|
| 540 | NET "*ETH_B*/SPLB_CLK" TNM_NET = "host_clock"; |
|---|
| 541 | TIMEGRP "B_clk_host" = "B_host_clock"; |
|---|
| 542 | TIMESPEC "TS_B_clk_host" = PERIOD "B_clk_host" 10 ns HIGH 50 %; |
|---|
| 543 | |
|---|
| 544 | ############################################################################### |
|---|
| 545 | # PHYSICAL INTERFACE CONSTRAINTS |
|---|
| 546 | # The following constraints are necessary for proper operation, and are tuned |
|---|
| 547 | # for this example design. They should be modified to suit your design. |
|---|
| 548 | ############################################################################### |
|---|
| 549 | |
|---|
| 550 | # RGMII physical interface constraints |
|---|
| 551 | # ----------------------------------------------------------------------------- |
|---|
| 552 | |
|---|
| 553 | # Set the IDELAY and ODELAY values, tuned for this example design. |
|---|
| 554 | # These values should be modified to suit your design. |
|---|
| 555 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
|---|
| 556 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
|---|
| 557 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
|---|
| 558 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
|---|
| 559 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
|---|
| 560 | |
|---|
| 561 | INST "*ETH_B*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
|---|
| 562 | INST "*ETH_B*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
|---|
| 563 | INST "*ETH_B*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
|---|
| 564 | INST "*ETH_B*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
|---|
| 565 | INST "*ETH_B*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
|---|
| 566 | |
|---|
| 567 | INST "*ETH_B*rgmii_rxc0_delay" IDELAY_VALUE = 0; |
|---|
| 568 | INST "*ETH_B*rgmii_rxc0_delay" SIGNAL_PATTERN = CLOCK; |
|---|
| 569 | |
|---|
| 570 | INST "*ETH_B*rgmii?rgmii_tx_clk_delay" ODELAY_VALUE = 6; |
|---|
| 571 | INST "*ETH_B*rgmii?rgmii_tx_clk_delay" SIGNAL_PATTERN = CLOCK; |
|---|
| 572 | |
|---|
| 573 | # Group all IODELAY-related blocks to use a single IDELAYCTRL |
|---|
| 574 | |
|---|
| 575 | # Change - added TNMs for trace length variations |
|---|
| 576 | INST "ETH_B_RGMII_RXD_0_pin[0]" TNM = "B_rgmii_rx_d0"; |
|---|
| 577 | INST "ETH_B_RGMII_RXD_0_pin[1]" TNM = "B_rgmii_rx_d1"; |
|---|
| 578 | INST "ETH_B_RGMII_RXD_0_pin[2]" TNM = "B_rgmii_rx_d2"; |
|---|
| 579 | INST "ETH_B_RGMII_RXD_0_pin[3]" TNM = "B_rgmii_rx_d3"; |
|---|
| 580 | INST "ETH_B_RGMII_RX_CTL_0_pin" TNM = "B_rgmii_rx_ctrl"; |
|---|
| 581 | |
|---|
| 582 | # Spec: 1.2ns setup time, 1.2ns hold time |
|---|
| 583 | # The internal PHY delays were not used to derive the OFFSET constraints |
|---|
| 584 | # Changed NET Name |
|---|
| 585 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock |
|---|
| 586 | # Therefore the offset in constraint must have less setup time than nominal |
|---|
| 587 | TIMEGRP "B_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
|---|
| 588 | TIMEGRP "B_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
|---|
| 589 | |
|---|
| 590 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock |
|---|
| 591 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 592 | TIMEGRP "B_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
|---|
| 593 | TIMEGRP "B_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
|---|
| 594 | |
|---|
| 595 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock |
|---|
| 596 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 597 | TIMEGRP "B_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
|---|
| 598 | TIMEGRP "B_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
|---|
| 599 | |
|---|
| 600 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock |
|---|
| 601 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 602 | TIMEGRP "B_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
|---|
| 603 | TIMEGRP "B_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
|---|
| 604 | |
|---|
| 605 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock |
|---|
| 606 | # Therefore the offset in constraint must have more setup time than nominal |
|---|
| 607 | TIMEGRP "B_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
|---|
| 608 | TIMEGRP "B_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
|---|
| 609 | |
|---|
| 610 | |
|---|
| 611 | NET "*ETH_B*/LlinkTemac0_CLK" TNM_NET = "B_LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input |
|---|
| 612 | NET "*ETH_B*/SPLB_Clk" TNM_NET = "B_PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input |
|---|
| 613 | |
|---|
| 614 | TIMESPEC "TS_B_LL_CLK0_2_RX_CLIENT_CLK0" = FROM B_LLCLK0 TO B_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
|---|
| 615 | TIMESPEC "TS_B_LL_CLK0_2_TX_CLIENT_CLK0" = FROM B_LLCLK0 TO B_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
|---|
| 616 | TIMESPEC "TS_B_RX_CLIENT_CLK0_2_LL_CLK0" = FROM B_phy_clk_rx TO B_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
|---|
| 617 | TIMESPEC "TS_B_TX_CLIENT_CLK0_2_LL_CLK0" = FROM B_phy_clk_tx TO B_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock
|
|---|
| 618 |
|
|---|
| 619 | ###### DDR3_2GB_SODIMM
|
|---|
| 620 | #2012-Apr-2:
|
|---|
| 621 | # -Started with old UCF snippet from early FPGA pinout testing
|
|---|
| 622 | # -Updated LOC constraints to match MIG 13.4 design which met timing for 2GB SO-DIMM (-1 @ 400MHz, -2 @ 533MHz)
|
|---|
| 623 |
|
|---|
| 624 | ###### DDR3_SDRAM
|
|---|
| 625 |
|
|---|
| 626 | # Constrain BUFR clocks used to synchronize data from IOB to fabric logic
|
|---|
| 627 | # Note that ISE cannot infer this from other PERIOD constraints because
|
|---|
| 628 | # of the use of OSERDES blocks in the BUFR clock generation path
|
|---|
| 629 | NET "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/clk_rsync[?]" TNM_NET = TNM_clk_rsync;
|
|---|
| 630 | TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5000 ps; # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0
|
|---|
| 631 |
|
|---|
| 632 | # Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling
|
|---|
| 633 | # edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for
|
|---|
| 634 | # that particular flop. Mark this path as being a full-cycle, rather than
|
|---|
| 635 | # a half cycle path for timing purposes. NOTE: This constraint forces full-
|
|---|
| 636 | # cycle timing to be applied globally for all rising->falling edge paths
|
|---|
| 637 | # in all resynchronizaton clock domains. If the user had modified the logic
|
|---|
| 638 | # in the resync clock domain such that other rising->falling edge paths
|
|---|
| 639 | # exist, then constraint below should be modified to utilize pattern
|
|---|
| 640 | # matching to specific affect only the DQ/DQS ISERDES.Q outputs
|
|---|
| 641 | TIMEGRP "TG_clk_rsync_rise" = RISING "TNM_clk_rsync";
|
|---|
| 642 | TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync";
|
|---|
| 643 | TIMESPEC "TS_clk_rsync_rise_to_fall" = FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" 5000 ps; # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0
|
|---|
| 644 |
|
|---|
| 645 | # Signal to select between controller and physical layer signals. Four divided by two clock
|
|---|
| 646 | # cycles (4 memory clock cycles) are provided by design for the signal to settle down.
|
|---|
| 647 | # Used only by the phy modules.
|
|---|
| 648 | INST "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL";
|
|---|
| 649 | TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = 10000 ps; # This is over-constraint, user can relax it to match 4 memory clock cycles
|
|---|
| 650 |
|
|---|
| 651 | #Internal Vref
|
|---|
| 652 | CONFIG INTERNAL_VREF_BANK22=0.75;
|
|---|
| 653 | CONFIG INTERNAL_VREF_BANK23=0.75;
|
|---|
| 654 | CONFIG INTERNAL_VREF_BANK33=0.75;
|
|---|
| 655 |
|
|---|
| 656 | #DCI Cascading
|
|---|
| 657 | CONFIG DCI_CASCADE = "23 22";
|
|---|
| 658 |
|
|---|
| 659 | #BUFR IOBs (must be unconnected in FPGA and PCB)
|
|---|
| 660 | CONFIG PROHIBIT = AH17,AP20;
|
|---|
| 661 |
|
|---|
| 662 | #BUFIO IOBs (must be unconnected in FPGA and PCB)
|
|---|
| 663 | CONFIG PROHIBIT = AC13,AD12,AF19,AF20,AH23,AK27,AN27,AP11;
|
|---|
| 664 |
|
|---|
| 665 | ######################################################################################
|
|---|
| 666 | ##Place RSYNC OSERDES and IODELAY: ##
|
|---|
| 667 | ######################################################################################
|
|---|
| 668 |
|
|---|
| 669 | #MPMC as of EDK 13.4 only supports 32-bit memories
|
|---|
| 670 | ##Site: AH17 -- Bank 32
|
|---|
| 671 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" LOC = "OLOGIC_X2Y23";
|
|---|
| 672 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" LOC = "IODELAY_X2Y23";
|
|---|
| 673 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" LOC = "BUFR_X2Y1";
|
|---|
| 674 |
|
|---|
| 675 | ##Site: AP20 -- Bank 22
|
|---|
| 676 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y21";
|
|---|
| 677 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y21";
|
|---|
| 678 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y1";
|
|---|
| 679 |
|
|---|
| 680 |
|
|---|
| 681 | ######################################################################################
|
|---|
| 682 | ##Place CPT OSERDES and IODELAY: ##
|
|---|
| 683 | ######################################################################################
|
|---|
| 684 |
|
|---|
| 685 | ##Site: AH23 -- Bank 23
|
|---|
| 686 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X1Y57";
|
|---|
| 687 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" LOC = "IODELAY_X1Y57";
|
|---|
| 688 |
|
|---|
| 689 | ##Site: AK27 -- Bank 23
|
|---|
| 690 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" LOC = "OLOGIC_X1Y59";
|
|---|
| 691 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" LOC = "IODELAY_X1Y59";
|
|---|
| 692 |
|
|---|
| 693 | ##Site: AN27 -- Bank 23
|
|---|
| 694 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" LOC = "OLOGIC_X1Y61";
|
|---|
| 695 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" LOC = "IODELAY_X1Y61";
|
|---|
| 696 |
|
|---|
| 697 | ##Site: AF19 -- Bank 22
|
|---|
| 698 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" LOC = "OLOGIC_X1Y23";
|
|---|
| 699 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" LOC = "IODELAY_X1Y23";
|
|---|
| 700 |
|
|---|
| 701 | #MPMC as of EDK 13.4 only supports 32-bit memories
|
|---|
| 702 | ##Site: AF20 -- Bank 22
|
|---|
| 703 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" LOC = "OLOGIC_X1Y17";
|
|---|
| 704 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" LOC = "IODELAY_X1Y17";
|
|---|
| 705 |
|
|---|
| 706 | ##Site: AP11 -- Bank 33
|
|---|
| 707 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" LOC = "OLOGIC_X2Y57";
|
|---|
| 708 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" LOC = "IODELAY_X2Y57";
|
|---|
| 709 |
|
|---|
| 710 | ##Site: AC13 -- Bank 33
|
|---|
| 711 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" LOC = "OLOGIC_X2Y61";
|
|---|
| 712 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" LOC = "IODELAY_X2Y61";
|
|---|
| 713 |
|
|---|
| 714 | ##Site: AD12 -- Bank 33
|
|---|
| 715 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" LOC = "OLOGIC_X2Y59";
|
|---|
| 716 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" LOC = "IODELAY_X2Y59";
|
|---|
| 717 |
|
|---|
| 718 |
|
|---|
