[724] | 1 | /*! \file warpphy.h |
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| 2 | \brief Header file for the WARPPHY functions |
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| 3 | |
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[1598] | 4 | @version 15.22 |
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[903] | 5 | @author Patrick Murphy and Chris Hunter |
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[724] | 6 | |
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| 7 | This header file contains the macros, function prototypes, and typedefs required for WARPPHY. |
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| 8 | */ |
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| 9 | |
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[675] | 10 | //WARPPHY Interface |
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| 11 | /***************CHANGELOG***************** |
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| 12 | |
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| 13 | ******************************************/ |
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| 14 | /*****************WARPPHY***************** |
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| 15 | Description: This file specifies the |
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| 16 | interface between to the PHY. |
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| 17 | ******************************************/ |
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| 18 | |
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| 19 | #ifndef WARPPHY_H |
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| 20 | #define WARPPHY_H |
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| 21 | |
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[1169] | 22 | //Flag to include a bunch of low-level debugging functions |
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| 23 | // for tweaking values in the PHY cores |
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| 24 | // These can be excluded for most applications, saving a lot of code space |
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[1712] | 25 | #define INCLUDE_WARPPHY_DEBUG_FUNCTIONS 0 |
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[1169] | 26 | |
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| 27 | //Old design flow used OFDM_BASEADDR to refer to the PHY's base address |
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| 28 | // New flow addresses registers directly, not relative to a base address |
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| 29 | // This value is still defined to keep code from breaking |
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[972] | 30 | #define OFDM_BASEADDR 0 |
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[1169] | 31 | |
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| 32 | //PHY packet buffer is actually a PLB BRAM |
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| 33 | // The base address is the address of the PLB BRAM controller |
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[972] | 34 | #define OFDM_PKTBUFF_BASEADDR XPAR_XPS_BRAM_IF_CNTLR_2_BASEADDR |
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[675] | 35 | |
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| 36 | //Masks for configuring modulation settings in the PHY |
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| 37 | //Each is 8 copies of a 4-bit modulation value |
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| 38 | #define MODMASK_BPSK 0x11111111 |
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| 39 | #define MODMASK_QPSK 0x22222222 |
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| 40 | #define MODMASK_16QAM 0x44444444 |
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| 41 | #define MODMASK_64QAM 0x66666666 |
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| 42 | |
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[1208] | 43 | #define MOD_UNCHANGED 0xFF |
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| 44 | |
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[1616] | 45 | #define NUM_BASERATE_SYMBOLS_BPSK_CODED 8 |
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| 46 | #define NUM_BASERATE_SYMBOLS_QPSK_CODED 4 |
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| 47 | #define NUM_BASERATE_SYMBOLS_BPSK_UNCODED 4 |
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| 48 | #define NUM_BASERATE_SYMBOLS_QPSK_UNCODED 2 |
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| 49 | |
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| 50 | //Number of base rate OFDM symbols per packet |
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| 51 | // Must correspond to base rate modulation, number of header bytes and header coding rate |
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| 52 | #define NUM_BASERATE_SYMBOLS NUM_BASERATE_SYMBOLS_QPSK_CODED |
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| 53 | |
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| 54 | //Define number of channel training symbols per packet - must be even! |
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| 55 | // In SISO mode all symbols are used to train the H_AA channel |
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| 56 | // In Alamouti, alternate symbols train H_AA and H_BA |
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| 57 | // In 2x2, alternate symbols train H_AA/H_AB and H_BA/H_BB |
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| 58 | #define NUM_TRAINING_SYMBOLS 2 |
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| 59 | |
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[1169] | 60 | //Number of packet buffers; each sub-buffer is 2KB, so a 64KB PLB BRAM hold 32 buffers |
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[1103] | 61 | #define NUMPKTBUFFS 32 |
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[675] | 62 | |
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[1169] | 63 | //Length of the running RSSI sum in the pkt detector |
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| 64 | // #define'd here so it can be used again below |
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| 65 | #define PKTDET_RSSI_SUMLEN 16 |
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| 66 | |
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| 67 | //Define an RSSI threshold big enough so that carrier sensing will never assert |
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| 68 | // This is used to "disable" carrier sensing at run time |
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| 69 | #define CSMA_DISABLED_THRESH (1023*PKTDET_RSSI_SUMLEN) |
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| 70 | |
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[1494] | 71 | //Initial FFT window offset (number of CP samples to use per Rx FFT) |
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[1616] | 72 | #define INIT_RXFFTOFSET 10 |
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[1279] | 73 | |
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[1105] | 74 | //Code rate selection values, used in header.codeRate field per-packet |
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[1164] | 75 | //#define CONVCODED_PHY 1 |
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[1616] | 76 | #define HDR_CODE_RATE_12 0 |
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| 77 | #define HDR_CODE_RATE_23 1 |
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| 78 | #define HDR_CODE_RATE_34 2 |
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| 79 | #define HDR_CODE_RATE_NONE 3 |
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[1105] | 80 | |
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[1197] | 81 | #define TIMER_MODE_CARRIERSENSE 1 |
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| 82 | #define TIMER_MODE_NOCARRIERSENSE 0 |
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| 83 | |
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[1015] | 84 | //Define scaling values for the PHY's FFT cores |
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| 85 | #define TX_FFT_SCALING_STAGE1 1 |
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| 86 | #define TX_FFT_SCALING_STAGE2 2 |
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| 87 | #define TX_FFT_SCALING_STAGE3 3 |
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| 88 | |
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[1494] | 89 | // Was 1 2 1 |
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| 90 | #define RX_FFT_SCALING_STAGE1 0 |
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| 91 | #define RX_FFT_SCALING_STAGE2 1 |
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| 92 | #define RX_FFT_SCALING_STAGE3 1 |
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[1015] | 93 | |
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[1032] | 94 | //Define thresholds for the AGC |
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[1815] | 95 | #define AGC_THRESH_1 (256-24) |
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| 96 | #define AGC_THRESH_2 (256-55) |
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| 97 | #define AGC_THRESH_3 (256-127) |
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| 98 | |
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| 99 | /*#define AGC_THRESH_1 0xE2 //-30 |
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[1801] | 100 | //#define AGC_THRESH_2 0xCB //-53 |
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| 101 | //#define AGC_THRESH_2 0xC6 //-58 |
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| 102 | #define AGC_THRESH_2 0xB0 //-x |
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| 103 | //#define AGC_THRESH_3 0xA6 //-90 |
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| 104 | #define AGC_THRESH_3 0x81 //-127 |
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[1815] | 105 | */ |
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[1169] | 106 | |
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[941] | 107 | //RX Status register values |
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[1282] | 108 | #define PHYRXSTATUS_INCOMPLETE 0 |
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| 109 | #define PHYRXSTATUS_GOOD 0x5 |
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| 110 | #define PHYRXSTATUS_BAD 0xA |
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| 111 | #define PHYRXSTATUS_PAYLOAD 0x3 |
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| 112 | #define PHYRXSTATUS_HEADER 0xC |
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[941] | 113 | |
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[1208] | 114 | //Antenna configuration constants |
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| 115 | #define ANTMODE_UNCHANGED 0 |
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| 116 | |
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[1226] | 117 | #define ANTMODE_MASK_ANTSEL 0x00F |
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| 118 | #define ANTMODE_MASK_PHYMODE 0x0F0 |
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| 119 | #define ANTMODE_MASK_PHYANTCFG 0xF00 |
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[1208] | 120 | |
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[1226] | 121 | #define ANTMODE_ANTSEL_RADA 0x001 |
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| 122 | #define ANTMODE_ANTSEL_RADB 0x002 |
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| 123 | #define ANTMODE_ANTSEL_BOTHRADS (ANTMODE_ANTSEL_RADA | ANTMODE_ANTSEL_RADB) |
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[1208] | 124 | |
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[1226] | 125 | #define PHYMODE_SISO 0x010 |
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| 126 | #define PHYMODE_ALAMOUTI 0x020 |
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| 127 | #define PHYMODE_2X2MULT 0x040 |
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[1208] | 128 | |
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[1226] | 129 | #define PHYANTCFG_TX_NORMAL 0x100 |
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| 130 | #define PHYANTCFG_TX_SWAPPED 0x200 |
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[1208] | 131 | |
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[1226] | 132 | #define PHYANTCFG_RX_NORMAL 0x100 |
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| 133 | #define PHYANTCFG_RX_SWAPPED 0x200 |
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| 134 | #define PHYANTCFG_RX_SELDIV 0x400 |
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| 135 | |
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| 136 | #define TX_ANTMODE_SISO_ANTA (ANTMODE_ANTSEL_RADA | PHYMODE_SISO | PHYANTCFG_TX_NORMAL) |
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| 137 | #define TX_ANTMODE_SISO_ANTB (ANTMODE_ANTSEL_RADB | PHYMODE_SISO | PHYANTCFG_TX_SWAPPED) |
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| 138 | #define TX_ANTMODE_MULTPLX (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_TX_NORMAL) |
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| 139 | #define TX_ANTMODE_MULTPLX_SWAPPED (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_TX_SWAPPED) |
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| 140 | #define TX_ANTMODE_ALAMOUTI_2ANT (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL) |
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| 141 | #define TX_ANTMODE_ALAMOUTI_2ANT_SWAPPED (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED) |
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| 142 | #define TX_ANTMODE_ALAMOUTI_ANTA (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL) |
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[1232] | 143 | #define TX_ANTMODE_ALAMOUTI_ANTB (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_TX_NORMAL) |
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| 144 | #define TX_ANTMODE_ALAMOUTI_ANTA_SWAPPED (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED) |
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| 145 | #define TX_ANTMODE_ALAMOUTI_ANTB_SWAPPED (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_TX_SWAPPED) |
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[1226] | 146 | |
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| 147 | #define RX_ANTMODE_SISO_ANTA (ANTMODE_ANTSEL_RADA | PHYMODE_SISO | PHYANTCFG_RX_NORMAL) |
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| 148 | #define RX_ANTMODE_SISO_ANTB (ANTMODE_ANTSEL_RADB | PHYMODE_SISO | PHYANTCFG_RX_SWAPPED) |
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| 149 | #define RX_ANTMODE_SISO_SELDIV (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_SISO | PHYANTCFG_RX_SELDIV) |
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| 150 | #define RX_ANTMODE_MULTPLX (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_2X2MULT | PHYANTCFG_RX_NORMAL) |
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| 151 | #define RX_ANTMODE_ALAMOUTI_ANTA (ANTMODE_ANTSEL_RADA | PHYMODE_ALAMOUTI | PHYANTCFG_RX_NORMAL) |
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| 152 | #define RX_ANTMODE_ALAMOUTI_ANTB (ANTMODE_ANTSEL_RADB | PHYMODE_ALAMOUTI | PHYANTCFG_RX_SWAPPED) |
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| 153 | #define RX_ANTMODE_ALAMOUTI_SELDIV (ANTMODE_ANTSEL_BOTHRADS | PHYMODE_ALAMOUTI | PHYANTCFG_RX_SELDIV) |
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| 154 | |
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[720] | 155 | //Bit masks for the options configured in Rx_ControlBits |
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[675] | 156 | #define RESET_BER 0x1 |
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| 157 | #define REQ_LONG_CORR 0x2 |
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[1555] | 158 | //#define UNUSED 0x4 |
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[720] | 159 | #define BIG_PKTBUF_MODE 0x8 |
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[675] | 160 | #define RX_SISO_MODE 0x10 |
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[1555] | 161 | //#define UNUSED 0x20 |
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| 162 | //#define UNUSED 0x40 |
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[1203] | 163 | #define RECORD_CHAN_ESTS 0x80 |
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[1537] | 164 | #define RECORD_CHAN_ESTMAGS 0x100 |
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[675] | 165 | #define BYPASS_CARR_REC 0x200 |
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[720] | 166 | #define COARSE_CFO_EN 0x400 |
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[1516] | 167 | #define EXT_PKTDETRESET_EN 0x800 |
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[1245] | 168 | #define RSSI_GAIN_ADJ 0x1000 |
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[675] | 169 | #define EQ_BYPASS_DIVISION 0x4000 |
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[1164] | 170 | #define TX_DISABLE_PKTDET 0x8000 |
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[675] | 171 | #define SIMPLE_DYN_MOD_EN 0x10000 |
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| 172 | #define SWITCHING_DIV_EN 0x20000 |
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| 173 | #define SISO_ON_ANTB 0x40000 |
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[825] | 174 | #define RESET_ON_BAD_HDR 0x80000 |
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[1192] | 175 | #define RX_ALAMOUTI_MODE 0x100000 |
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| 176 | #define FLEX_BER_MODE 0x200000 |
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| 177 | #define BER_IGNORE_HDR 0x400000 |
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[1208] | 178 | #define PHY_RADIO_RXEN 0x1000000 |
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| 179 | #define AF_SAVEWAVEFORM 0x2000000 |
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[1254] | 180 | #define AUTORESP_FLAGA_RST 0x4000000 |
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| 181 | #define AUTORESP_FLAGB_RST 0x8000000 |
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[1546] | 182 | #define COARSECFO_PKTDET_EN 0x10000000 |
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| 183 | #define CHANMAG_MASKING_EN 0x20000000 |
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[1555] | 184 | //#define UNUSED 0x40000000 |
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[675] | 185 | #define RX_GLOBAL_RESET 0x80000000 |
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| 186 | |
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[1494] | 187 | //Bit masks for PreCFO_Options register |
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| 188 | #define PRECFO_USECOARSE 0x00000001 |
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| 189 | #define PRECFO_USEPILOTS 0x00000002 |
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| 190 | |
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[1208] | 191 | //Bit masks for Tx Start/Reset register |
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| 192 | #define TX_MASTER_RESET 0x1 |
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| 193 | #define TX_START 0x2 |
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| 194 | |
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| 195 | //Bit masks for OFDM Tx options |
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[1494] | 196 | #define TX_SISO_MODE 0x00000001 |
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| 197 | #define TX_ALAMOUTI_MODE 0x00000002 |
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| 198 | #define TX_DISABLE_ANTB_PREAMBLE 0x00000004 |
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| 199 | #define TX_PILOT_SCRAMBLING 0x00000008 |
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| 200 | #define TX_PREAMBLE_B_DLY 0x000000F0 //4-bit value |
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| 201 | #define TX_RANDOM_PAYLOAD 0x00000100 |
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| 202 | #define TX_SWAP_ANTENNAS 0x00000200 |
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| 203 | #define TX_SOFTWARE_TXEN 0x00000400 |
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| 204 | #define TX_EXTERNAL_TXEN 0x00000800 |
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[1541] | 205 | #define TX_ALWAYS_USE_PRECFO 0x00001000 |
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| 206 | #define TX_CAPTURE_RANDOM_PAYLOAD 0x00002000 |
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| 207 | #define TX_AUTO_TWOTX_EN 0x00004000 |
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| 208 | #define TX_START_D0_OUT_EN 0x00008000 |
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| 209 | #define TX_START_D1_OUT_EN 0x00010000 |
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[1555] | 210 | #define TX_ALT_INTERPFILT 0x00020000 |
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| 211 | #define TX_CONJ_ANTB_STS 0x00040000 |
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| 212 | #define TX_CONJ_ANTB_LTS 0x00080000 |
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[1208] | 213 | |
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[1541] | 214 | //Bit masks for Tx_Delays register |
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| 215 | #define TX_EXTAUTO_TXEN_DLY_LSB 0 //0x000000FF //8-bit value |
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| 216 | #define TX_AUTOTX_EXTRA_DLY_LSB 8 //0x00000F00 //4-bit value |
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| 217 | #define TX_START_D_OUTPUTS_DLY_LSB 12 //0x000FF000 //8-bit value |
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| 218 | |
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[1169] | 219 | //Bit masks for the Tx/Rx status bits |
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[1270] | 220 | #define RXSTATUS_PKTDONE_RST 0x1 |
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| 221 | #define RXSTATUS_HEADER_RST 0x2 |
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[1169] | 222 | #define TXSTATUS_DONE_RST 0x4 |
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[675] | 223 | |
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[1169] | 224 | #define RXSTATUS_GOODPKT 0x8 |
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| 225 | #define RXSTATUS_BADPKT 0x10 |
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| 226 | #define RXSTATUS_GOODHEADER 0x20 |
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| 227 | #define RXSTATUS_BADHEADER 0x40 |
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| 228 | #define TXSTATUS_DONE 0x80 |
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[941] | 229 | |
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[1169] | 230 | #define ALL_STATUSBITS_ENABLE (RXSTATUS_GOODHEADER|RXSTATUS_BADHEADER|RXSTATUS_BADPKT|RXSTATUS_GOODPKT|TXSTATUS_DONE) |
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| 231 | #define DEFAULT_STATUSBITS (RXSTATUS_GOODHEADER|RXSTATUS_BADHEADER|RXSTATUS_BADPKT|RXSTATUS_GOODPKT) |
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| 232 | #define DEFAULT_STATUSBITRESETS (RXSTATUS_HEADER_RST|RXSTATUS_PKTDONE_RST|TXSTATUS_DONE_RST) |
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| 233 | |
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[941] | 234 | //Define which radios get used |
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[675] | 235 | //RADIOx_ADDR are defined by the radio controller driver |
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[1801] | 236 | //#define FIRST_RADIO RADIO2_ADDR |
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| 237 | //#define SECOND_RADIO RADIO3_ADDR |
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[1208] | 238 | #define BOTH_RADIOS (FIRST_RADIO | SECOND_RADIO) |
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[675] | 239 | |
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[941] | 240 | //Shorthand for configuring the radio controller's selected band |
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[675] | 241 | #define GHZ_5 0 |
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| 242 | #define GHZ_2 1 |
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| 243 | |
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[1203] | 244 | //Bit masks for OFDM Tx status register |
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| 245 | #define OFDM_TX_BUSY 0x1 |
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| 246 | #define OFDM_TX_HEADERBUSY 0x2 |
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| 247 | |
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[941] | 248 | //Bits 0xF0 are used for 4-bit preable shift value |
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[675] | 249 | #define TX_SISO_ON_ANTB 0x100 |
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| 250 | |
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| 251 | //MAC2PHY Options |
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[941] | 252 | #define TXBLOCK 0x0 |
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| 253 | #define TXNOBLOCK 0x1 |
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[675] | 254 | |
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[941] | 255 | //Macros for accessing the OFDM packet buffer; buff is an integer in [0,NUMPKTBUFFS-1] |
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| 256 | #define warpphy_copyBytesToPhy(buff,src,len) memcpy(OFDM_PKTBUFF_BASEADDR + buff * 0x1000,(src),(len)) |
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| 257 | #define warpphy_copyBytesFromPhy(buff,dest,len) memcpy((dest), OFDM_PKTBUFF_BASEADDR + buff * 0x1000, (len)) |
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[870] | 258 | |
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[941] | 259 | //Macro to retrieve the physical memory address for a given packet buffer index |
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[1103] | 260 | // PHY packet buffers are 2048 bytes (0x800) each |
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| 261 | // The current PHY has 32 buffers, so the buffer index is masked to 5 bits |
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| 262 | // here to avoid returning bogus buffer addresses |
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| 263 | #define warpphy_getBuffAddr(c) (OFDM_PKTBUFF_BASEADDR + (c & 0x1F)*(0x800)) |
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[870] | 264 | |
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[941] | 265 | //Macros to read/write PHY registers |
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[1210] | 266 | #define mimo_ofdmTx_setStartTx(c) ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(OFDM_BASEADDR, ( (c<<1) & TX_START) ) |
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[941] | 267 | #define mimo_ofdmRx_setByteNums(c) ofdm_txrx_mimo_WriteReg_Rx_pktByteNums(OFDM_BASEADDR, c) |
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| 268 | #define mimo_ofdmRx_setRxScaling(c) ofdm_txrx_mimo_WriteReg_Rx_Constellation_Scaling(OFDM_BASEADDR, c) |
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| 269 | #define mimo_ofdmRx_setLongCorrParams(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_LongCorr_Params(OFDM_BASEADDR, c) |
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[1222] | 270 | |
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| 271 | #define mimo_ofdmTx_setPilotIndcies(c) ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Index(0, c) |
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| 272 | #define mimo_ofdmTxRx_setPilotValues(c) ofdm_txrx_mimo_WriteReg_TxRx_Pilots_Values(0, c) |
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| 273 | |
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[1712] | 274 | #define mimo_ofdmTxRx_setFECoptions(codingEn, softEn, zeroTail, scale_qpsk, scale_16qam) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_FEC_CONFIG, ( \ |
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[1615] | 275 | ((codingEn<<0) & 0x1) | \ |
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| 276 | ((softEn<<1) & 0x2) | \ |
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| 277 | ((zeroTail<<2) & 0x4) | \ |
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| 278 | ((scale_qpsk<<4) & 0xF0) | \ |
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| 279 | ((scale_16qam<<8) & 0x1F00))) |
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| 280 | |
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[1712] | 281 | //#define warpphy_setChanEstMinMags(chanAA, chanBA) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CHANEST_MINMAG, ( (chanAA & 0xFFFF) | ( (chanBA & 0xFFFF)<<16))) |
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| 282 | #define warpphy_setChanEstMinMags(estmag) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_CHANEST_MINMAG, (estmag)) |
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[1546] | 283 | |
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[1712] | 284 | #define warpphy_setAFblanking(start, stop) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_AF_BLANKING, ( (start & 0xFFF) | ( (stop & 0xFFF) << 16))) |
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[1546] | 285 | |
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[1712] | 286 | #define warpphy_setTxNumSyms(numBR, numT) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_OFDM_SYMCOUNTS, ( (numT & 0xF) | ( (numBR & 0x1F)<<8) ) ) |
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| 287 | #define warpphy_setRxNumSyms(numBR, numT) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_OFDM_SYMBOLCOUNTS, ( (numT & 0xF) | ( (numBR & 0x1F)<<16) ) ) |
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[1169] | 288 | |
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[1712] | 289 | #define warpphy_setPreCFOoptions(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PRECFO_OPTIONS, c) |
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[1494] | 290 | #define warpphy_getPreCFO_pktBuf(bufInd) XIo_In32( (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTBUFFREQOFFSETS + (4*((bufInd)&0x1F))) ) |
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[1504] | 291 | #define warpphy_setPreCFO_pktBuf(bufInd, cfoVal) XIo_Out32( (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_PKTBUFFREQOFFSETS + (4*((bufInd)&0x1F))), cfoVal) |
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| 292 | |
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[1494] | 293 | #define warpphy_getPreCFO_pkt_coarse() XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFOEST) |
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| 294 | #define warpphy_getPreCFO_pkt_pilots() XIo_In32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PILOTCFOEST) |
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[1712] | 295 | #define warpphy_setPilotCFOCorrection(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_PRECFO_PILOTCALCCORRECTION, c) |
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[1494] | 296 | |
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[1712] | 297 | #define warpphy_setCoarseCFOCorrection(c) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_RX_COARSECFO_CORRECTION, c) |
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[1522] | 298 | |
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[1169] | 299 | #define mimo_ofdmTx_setTxScaling(pre, pay) ofdm_txrx_mimo_WriteReg_Tx_Scaling(OFDM_BASEADDR, ((0xFFFF & pre) | (0xFFFF0000 & (pay<<16))) ) |
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| 300 | |
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[675] | 301 | #define mimo_ofdmTx_setControlBits(c) ofdm_txrx_mimo_WriteReg_Tx_ControlBits(OFDM_BASEADDR, c) |
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| 302 | #define mimo_ofdmTx_getOptions() ofdm_txrx_mimo_ReadReg_Tx_ControlBits(OFDM_BASEADDR) |
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[1541] | 303 | |
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[1712] | 304 | #define mimo_ofdmTx_setDelays(extTxEn, extraAutoTx, txStartOut) XIo_Out32(XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TX_DELAYS, ( \ |
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[1541] | 305 | ( (extTxEn&0xFF) << TX_EXTAUTO_TXEN_DLY_LSB) | \ |
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| 306 | ( (extraAutoTx&0xF) << TX_AUTOTX_EXTRA_DLY_LSB) | \ |
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| 307 | ( (txStartOut&0xFF) << TX_START_D_OUTPUTS_DLY_LSB))) |
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| 308 | |
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[941] | 309 | #define mimo_ofdmTxRx_setFFTScaling(c) ofdm_txrx_mimo_WriteReg_TxRx_FFT_Scaling(OFDM_BASEADDR, c) |
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| 310 | #define mimo_ofdmRx_setFFTWindowOffset(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & 0xFFFFE07F) | ((c&0x3F)<<7)) |
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[1245] | 311 | |
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[941] | 312 | #define mimo_ofdmRx_setPktDetDly(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & 0xFFFFFF80)| (c&0x7F)) |
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[1245] | 313 | #define mimo_ofdmRx_setCFOCalcDly(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & ~0x001F0000) | ( (c&0x1F)<<16 )) |
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[1260] | 314 | #define mimo_ofdmRx_setCFOMaxDiff(c) ofdm_txrx_mimo_WriteReg_Rx_PktDet_Delay(OFDM_BASEADDR, (ofdm_txrx_mimo_ReadReg_Rx_PktDet_Delay(OFDM_BASEADDR) & ~0xFF000000) | ( (c&0xFF)<<24 )) |
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[1245] | 315 | |
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[941] | 316 | #define mimo_ofdmTx_setPktDoneReset(c) ofdm_txrx_mimo_WriteReg_Tx_Start_Reset_Control(OFDM_BASEADDR, (c<<2)&0x4) |
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[1282] | 317 | #define mimo_ofdmRx_getPayloadStatus() (PHYRXSTATUS_PAYLOAD & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR)) |
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| 318 | #define mimo_ofdmRx_getHeaderStatus() ((PHYRXSTATUS_HEADER & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR))) |
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| 319 | #define mimo_ofdmRx_getPktStatus() (((PHYRXSTATUS_PAYLOAD | PHYRXSTATUS_HEADER) & ofdm_txrx_mimo_ReadReg_Rx_packet_done(OFDM_BASEADDR))) |
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[675] | 320 | |
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[1222] | 321 | #define mimo_ofdmRx_setAFTxScaling(c) ofdm_rx_mimo_WriteReg_Rx_AFScaling(0, c) |
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[1164] | 322 | |
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[1524] | 323 | #define mimo_ofdmRx_setPilotCalcParams(minMag) ofdm_rx_mimo_WriteReg_Rx_PilotCalcParams(0, (minMag & 0xFFF)) |
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[1279] | 324 | |
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[1164] | 325 | //Timer Defines |
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| 326 | #define TIMER_A 0 |
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| 327 | #define TIMER_B 1 |
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| 328 | #define TIMER_C 2 |
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| 329 | #define TIMER_D 3 |
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| 330 | |
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| 331 | #define TIMER_A_DONE 0x1 |
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| 332 | #define TIMER_B_DONE 0x100 |
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| 333 | #define TIMER_C_DONE 0x10000 |
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| 334 | #define TIMER_D_DONE 0x1000000 |
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| 335 | |
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| 336 | #define TIMER_A_ACTIVE 0x2 |
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| 337 | #define TIMER_B_ACTIVE 0x200 |
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| 338 | #define TIMER_C_ACTIVE 0x20000 |
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| 339 | #define TIMER_D_ACTIVE 0x2000000 |
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| 340 | |
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| 341 | #define TIMER_A_PAUSED 0x4 |
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| 342 | #define TIMER_B_PAUSED 0x400 |
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| 343 | #define TIMER_C_PAUSED 0x40000 |
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| 344 | #define TIMER_D_PAUSED 0x4000000 |
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| 345 | |
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[1224] | 346 | //Byte indicies of various header fields (used for the autoRepsonse setup) |
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[1232] | 347 | #define PKTHEADER_INDX_SRCADDR 4 |
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[1224] | 348 | #define PKTHEADER_INDX_DSTADDR 6 |
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[1232] | 349 | #define PKTHEADER_INDX_RLYADDR 8 |
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[1224] | 350 | #define PKTHEADER_INDX_TYPE 10 |
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[1632] | 351 | #define PKTHEADER_INDX_RETX 11 |
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| 352 | #define PKTHEADER_INDX_SEQ 12 |
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| 353 | #define PKTHEADER_INDX_PREVCHECK 20 |
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| 354 | #define PKTHEADER_INDX_CHECK 22 |
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[1224] | 355 | |
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[1214] | 356 | ///Structure contains PHY header |
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| 357 | typedef struct { |
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| 358 | ///Full-rate modulation order |
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[1632] | 359 | unsigned char fullRate; //0 |
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[1214] | 360 | ///Rate for convolutional error correction code |
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[1632] | 361 | unsigned char codeRate; //1 |
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[1214] | 362 | ///The length of the packet (in bytes). NOTE: This should only specify the length of the payload to-be-sent. |
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[1632] | 363 | unsigned short int length; //2 |
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[1214] | 364 | ///Source MAC address. |
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[1632] | 365 | unsigned short int srcAddr; //4 |
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[1214] | 366 | ///Destination MAC address. |
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[1632] | 367 | unsigned short int destAddr; //6 |
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[1214] | 368 | ///Relay MAC address. |
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[1632] | 369 | unsigned short int relAddr; //8 |
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[1214] | 370 | ///Type of packet this particular Macframe corresponds to (e.g. DATA, ACKPACKET, etc.) |
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[1632] | 371 | unsigned char pktType; //10 |
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[1214] | 372 | ///Reserved byte |
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[1632] | 373 | unsigned char remainingTx; //11 |
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[1491] | 374 | ///Sequence number of this packet |
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[1632] | 375 | unsigned int seqNum; //12-15 |
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[1214] | 376 | ///Reserved byte |
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[1650] | 377 | unsigned short int timeLeft; |
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| 378 | unsigned char cogParam; |
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| 379 | unsigned char reserved0; |
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| 380 | unsigned char reserved1; //20 |
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| 381 | unsigned char reserved2; //21 |
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[1633] | 382 | |
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[1214] | 383 | ///Checksum of the packet will be automatically inserted by PHY |
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[1632] | 384 | unsigned short int checksum; //22 |
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| 385 | } phyHeader; |
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[719] | 386 | |
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[941] | 387 | //Prototypes for functions in warpphy.c |
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[675] | 388 | int warpphy_init(); |
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[720] | 389 | void warpphy_clearRxInterrupts(); |
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[828] | 390 | void warpphy_clearTxInterrupts(); |
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[827] | 391 | int warpphy_pktTx(unsigned int block); |
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[675] | 392 | void mimo_ofdmRx_enable(); |
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| 393 | void mimo_ofdmRx_disable(); |
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| 394 | void mimo_ofdmRx_setOptions(unsigned int someOptions, unsigned int intType); |
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| 395 | unsigned int mimo_ofdmRx_getOptions(); |
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[720] | 396 | void mimo_ofdmTx_disable(); |
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[675] | 397 | void mimo_ofdmTx_enable(); |
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| 398 | void warpphy_setBuffs(unsigned char txBufOffset, unsigned char rxBufOffset); |
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[1169] | 399 | void warpphy_setNumTrainingSyms(unsigned int numTraining); |
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[675] | 400 | void warpphy_setPktDlyPlus(); |
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| 401 | void warpphy_setPktDlyMinus(); |
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| 402 | void warpphy_set_PN_KPlus(unsigned int increment); |
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| 403 | void warpphy_set_PN_KMinus(unsigned int decrement); |
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[733] | 404 | void warpphy_set_CFODebugOutput(unsigned char outputSel); |
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[828] | 405 | void print_CFO_constants(); |
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[675] | 406 | void warpphy_set_B_KPPlus(unsigned int increment); |
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| 407 | void warpphy_set_B_KPMinus(unsigned int decrement); |
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| 408 | void warpphy_set_B_KIPlus(unsigned int increment); |
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| 409 | void warpphy_set_B_KIMinus(unsigned int decrement); |
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| 410 | void warpphy_set_FFTOffset_Plus(); |
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| 411 | void warpphy_set_FFTOffset_Minus(); |
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| 412 | void warpphy_setNoiseTargetPlus(); |
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| 413 | void warpphy_setNoiseTargetMinus(); |
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| 414 | void warpphy_setTargetPlus(); |
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| 415 | void warpphy_setTargetMinus(); |
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[1208] | 416 | void warpphy_set_modulation(unsigned char baseRate, unsigned char TxAntAFullRate, unsigned char TxAntBFullRate, unsigned char RxAntAFullRate, unsigned char RxAntBFullRate); |
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[1169] | 417 | int warpphy_setChannel(unsigned char band, unsigned int chan); |
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[903] | 418 | int warpphy_applyTxDCOCorrection(unsigned int radioSelection); |
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| 419 | void warpphy_clearRxHeaderInterrupt(); |
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| 420 | void warpphy_setPktDetPlus(unsigned int offset); |
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| 421 | void warpphy_setPktDetMinus(unsigned int offset); |
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| 422 | void warpphy_setCSMAPlus(unsigned int offset); |
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[856] | 423 | void warpphy_setCSMAMinus(unsigned int offset); |
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[903] | 424 | int warpphy_isFree(); |
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[1164] | 425 | char warpphy_pollRxStatus(unsigned char type); |
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[941] | 426 | void ofdm_AGC_SetTarget(unsigned int target); |
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[1594] | 427 | inline void ofdm_AGC_SetDCO(unsigned int AGCstate); |
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[941] | 428 | void ofdm_AGC_Reset(); |
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| 429 | void ofdm_AGC_MasterReset(); |
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| 430 | void ofdm_AGC_Initialize(int noise_estimate); |
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| 431 | void ofdm_AGC_setNoiseEstimate(int noise_estimate); |
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| 432 | unsigned int ofdm_AGC_GetGains(void); |
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| 433 | void ofdm_timer_start(); |
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| 434 | void ofdm_timer_stop(); |
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| 435 | void ofdm_timer_clearInterrupt(); |
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[1103] | 436 | int warpphy_setTxPower(unsigned char txPwr); |
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[1208] | 437 | int warpphy_setAntennaMode(unsigned int txMode, unsigned int rxMode); |
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[1316] | 438 | void warpphy_incrementTxScaling(int incr_preamble, int incr_payload); |
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[1245] | 439 | void warpphy_setLongCorrThresh(unsigned short thresh); |
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[1616] | 440 | void warpphy_setEnergyDetThresh(unsigned short thresh); |
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[1260] | 441 | void warpphy_clearAutoResponseFlag(unsigned char flagID); |
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[1264] | 442 | void warpphy_setAntBPreambleShift(unsigned char shift); |
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[1375] | 443 | void warpphy_AFrecordEnable(unsigned char recordEn); |
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[1537] | 444 | void warpphy_setNumBaseRateSyms(unsigned int numSyms); |
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[1633] | 445 | void warpphy_setAutoCorrDetParams(unsigned short corrThresh, unsigned short energyThresh); |
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[1661] | 446 | void warpphy_setCarrierSenseThresh(unsigned short thresh); |
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[1712] | 447 | void warpphy_clearRxPktStatus(); |
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| 448 | int warpphy_waitForTx(); |
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| 449 | int warpphy_applyTxDCOCalibration(); |
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[941] | 450 | |
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[1177] | 451 | //warp_timer function prototypes |
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[1049] | 452 | void warp_timer_start(unsigned char timer); |
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[1177] | 453 | void warp_timer_pause(unsigned char timer); |
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[1049] | 454 | void warp_timer_resume(unsigned char timer); |
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| 455 | void warp_timer_setMode(unsigned char timer, unsigned char mode); |
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[1177] | 456 | void warp_timer_resetDone(unsigned char timer); |
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| 457 | void warp_timer_resetAllDoneStatus(); |
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| 458 | void warp_timer_setTimer(unsigned char timer, unsigned int slotTime, unsigned int slotCount); |
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| 459 | void warp_timer_init(); |
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[1049] | 460 | unsigned char warp_timer_getStatus(unsigned char timer); |
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[1177] | 461 | unsigned char warp_timer_isDone(unsigned char timer); |
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[1049] | 462 | unsigned char warp_timer_isActive(unsigned char timer); |
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| 463 | unsigned char warp_timer_isPaused(unsigned char timer); |
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| 464 | unsigned int warp_timer_getStatuses(); |
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[1177] | 465 | unsigned char warp_timer_getDoneStatus(); |
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[1226] | 466 | void warpphy_saveAFpkt(unsigned char doSave); |
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[1232] | 467 | int warpphy_setTxAntennaSwap(unsigned int txMode); |
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[1477] | 468 | unsigned int warpphy_returnGainsDB(); |
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[1049] | 469 | |
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[1232] | 470 | //Register access macros |
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[1712] | 471 | #define mimo_ofdmTxRx_getAction0() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION0)) |
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| 472 | #define mimo_ofdmTxRx_getAction1() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION1)) |
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| 473 | #define mimo_ofdmTxRx_getAction2() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION2)) |
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| 474 | #define mimo_ofdmTxRx_getAction3() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION3)) |
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| 475 | #define mimo_ofdmTxRx_getAction4() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION4)) |
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| 476 | #define mimo_ofdmTxRx_getAction5() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION5)) |
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| 477 | #define mimo_ofdmTxRx_getAction6() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION6)) |
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| 478 | #define mimo_ofdmTxRx_getAction7() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION7)) |
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[1203] | 479 | |
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[1712] | 480 | #define mimo_ofdmTxRx_setAction0(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION0, d)) |
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| 481 | #define mimo_ofdmTxRx_setAction1(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION1, d)) |
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| 482 | #define mimo_ofdmTxRx_setAction2(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION2, d)) |
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| 483 | #define mimo_ofdmTxRx_setAction3(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION3, d)) |
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| 484 | #define mimo_ofdmTxRx_setAction4(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION4, d)) |
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| 485 | #define mimo_ofdmTxRx_setAction5(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION5, d)) |
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| 486 | #define mimo_ofdmTxRx_setAction6(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION6, d)) |
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| 487 | #define mimo_ofdmTxRx_setAction7(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_ACTION7, d)) |
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[1203] | 488 | |
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[1712] | 489 | #define mimo_ofdmTxRx_getMatch0() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH0)) |
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| 490 | #define mimo_ofdmTxRx_getMatch1() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH1)) |
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| 491 | #define mimo_ofdmTxRx_getMatch2() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH2)) |
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| 492 | #define mimo_ofdmTxRx_getMatch3() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH3)) |
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| 493 | #define mimo_ofdmTxRx_getMatch4() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH4)) |
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| 494 | #define mimo_ofdmTxRx_getMatch5() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH5)) |
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| 495 | #define mimo_ofdmTxRx_getMatch6() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH6)) |
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| 496 | #define mimo_ofdmTxRx_getMatch7() (XIo_In32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH7)) |
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[1203] | 497 | |
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[1712] | 498 | #define mimo_ofdmTxRx_setMatch0(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH0, d)) |
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| 499 | #define mimo_ofdmTxRx_setMatch1(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH1, d)) |
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| 500 | #define mimo_ofdmTxRx_setMatch2(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH2, d)) |
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| 501 | #define mimo_ofdmTxRx_setMatch3(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH3, d)) |
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| 502 | #define mimo_ofdmTxRx_setMatch4(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH4, d)) |
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| 503 | #define mimo_ofdmTxRx_setMatch5(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH5, d)) |
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| 504 | #define mimo_ofdmTxRx_setMatch6(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH6, d)) |
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| 505 | #define mimo_ofdmTxRx_setMatch7(d) (XIo_Out32((unsigned int)XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXRX_AUTOREPLY_MATCH7, d)) |
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[1203] | 506 | |
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[1232] | 507 | //Match definition fields for match units 0-5 (comparison of incoming header with static value) |
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[1203] | 508 | #define PHY_AUTORESPONSE_MATCH_BYTEADDR_MASK 0x0000001F |
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| 509 | #define PHY_AUTORESPONSE_MATCH_BYTEADDR_OFFSET 0 |
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| 510 | |
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| 511 | #define PHY_AUTORESPONSE_MATCH_LENGTH_MASK 0x00000060 |
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| 512 | #define PHY_AUTORESPONSE_MATCH_LENGTH_OFFSET 5 |
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| 513 | |
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| 514 | #define PHY_AUTORESPONSE_MATCH_VALUE_MASK 0xFFFFFF00 |
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| 515 | #define PHY_AUTORESPONSE_MATCH_VALUE_OFFSET 8 |
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| 516 | |
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| 517 | #define PHY_AUTORESPONSE_MATCH_VALUE_MAP(c) ((c<<PHY_AUTORESPONSE_MATCH_VALUE_OFFSET) & PHY_AUTORESPONSE_MATCH_VALUE_MASK) |
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| 518 | #define PHY_AUTORESPONSE_MATCH_LENGTH_MAP(c) ((c<<PHY_AUTORESPONSE_MATCH_LENGTH_OFFSET) & PHY_AUTORESPONSE_MATCH_LENGTH_MASK) |
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| 519 | #define PHY_AUTORESPONSE_MATCH_BYTEADDR_MAP(c) ((c<<PHY_AUTORESPONSE_MATCH_BYTEADDR_OFFSET) & PHY_AUTORESPONSE_MATCH_BYTEADDR_MASK) |
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| 520 | |
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| 521 | #define PHY_AUTORESPONSE_MATCH_CONFIG(addr, len, val) (PHY_AUTORESPONSE_MATCH_BYTEADDR_MAP(addr) | PHY_AUTORESPONSE_MATCH_LENGTH_MAP(len) | PHY_AUTORESPONSE_MATCH_VALUE_MAP(val)) |
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| 522 | |
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[1232] | 523 | //Match definition fields for match units 6-7 (comparison of incoming header with previously received header corresponding to saved waveform) |
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| 524 | #define PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET 0 |
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| 525 | #define PHY_AUTORESPONSE_MATCH_RXADDR0_MASK (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET) |
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| 526 | #define PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET 5 |
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| 527 | #define PHY_AUTORESPONSE_MATCH_PREVADDR0_MASK (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET) |
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| 528 | |
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| 529 | #define PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET 10 |
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| 530 | #define PHY_AUTORESPONSE_MATCH_RXADDR1_MASK (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET) |
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| 531 | #define PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET 15 |
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| 532 | #define PHY_AUTORESPONSE_MATCH_PREVADDR1_MASK (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET) |
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| 533 | #define PHY_AUTORESPONSE_MATCH_ADDR1_EN 0x40000000 |
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| 534 | |
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| 535 | #define PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET 20 |
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| 536 | #define PHY_AUTORESPONSE_MATCH_RXADDR2_MASK (0x0000001F<< PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET) |
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| 537 | #define PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET 25 |
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| 538 | #define PHY_AUTORESPONSE_MATCH_PREVADDR2_MASK (0x0000001F<< PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET) |
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| 539 | #define PHY_AUTORESPONSE_MATCH_ADDR2_EN 0x80000000 |
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| 540 | |
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| 541 | //Macro to help define header comparison match configuration registers |
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| 542 | #define PHY_AUTORESPONSE_MATCH_HDRCOMP_CONFIG(rxAddr0, prevAddr0, rxAddr1, prevAddr1, useAddr1, rxAddr2, prevAddr2, useAddr2) (\ |
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| 543 | ( (rxAddr0 << PHY_AUTORESPONSE_MATCH_RXADDR0_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR0_MASK) | \ |
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| 544 | ( (rxAddr1 << PHY_AUTORESPONSE_MATCH_RXADDR1_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR1_MASK) | \ |
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| 545 | ( (rxAddr2 << PHY_AUTORESPONSE_MATCH_RXADDR2_OFFSET) & PHY_AUTORESPONSE_MATCH_RXADDR2_MASK) | \ |
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| 546 | ( (prevAddr0 << PHY_AUTORESPONSE_MATCH_PREVADDR0_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR0_MASK) | \ |
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| 547 | ( (prevAddr1 << PHY_AUTORESPONSE_MATCH_PREVADDR1_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR1_MASK) | \ |
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| 548 | ( (prevAddr2 << PHY_AUTORESPONSE_MATCH_PREVADDR2_OFFSET) & PHY_AUTORESPONSE_MATCH_PREVADDR2_MASK) | \ |
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| 549 | ( useAddr1 ? PHY_AUTORESPONSE_MATCH_ADDR1_EN : 0) | \ |
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| 550 | ( useAddr2 ? PHY_AUTORESPONSE_MATCH_ADDR2_EN : 0) ) |
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| 551 | |
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| 552 | |
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[1203] | 553 | //Action fields |
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| 554 | #define PHY_AUTORESPONSE_ACT_ID_MASK 0x00FC0000 |
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| 555 | #define PHY_AUTORESPONSE_ACT_ID_OFFSET 18 |
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| 556 | |
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| 557 | #define PHY_AUTORESPONSE_ACT_PARAM_MASK 0xFF000000 |
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| 558 | #define PHY_AUTORESPONSE_ACT_PARAM_OFFSET 24 |
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| 559 | #define PHY_AUTORESPONSE_MAP_ACT_PARAM(c) ((c<<PHY_AUTORESPONSE_ACT_PARAM_OFFSET) & PHY_AUTORESPONSE_ACT_PARAM_MASK) |
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| 560 | |
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[1254] | 561 | #define PHY_AUTORESPONSE_ACT_TRANS_HDR 0x00010000 |
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| 562 | #define PHY_AUTORESPONSE_ACT_USE_PRECFO 0x00020000 |
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[1594] | 563 | #define PHY_AUTORESPONSE_ACT_RETX_CRC 0x00000200 |
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[1516] | 564 | #define PHY_AUTORESPONSE_ACT_SWAP_ANT 0x00000400 |
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[1254] | 565 | |
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| 566 | #define PHY_AUTORESPONSE_REQ_GOODHDR 0x000800 |
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| 567 | #define PHY_AUTORESPONSE_REQ_BADPKT 0x001000 |
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| 568 | #define PHY_AUTORESPONSE_REQ_GOODPKT 0x002000 |
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| 569 | |
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| 570 | #define PHY_AUTORESPONSE_REQ_FLAGA 0x004000 |
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| 571 | #define PHY_AUTORESPONSE_REQ_FLAGB 0x008000 |
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| 572 | |
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[1203] | 573 | #define PHY_AUTORESPONSE_REQ_MATCH0 0x001 |
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| 574 | #define PHY_AUTORESPONSE_REQ_MATCH1 0x002 |
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| 575 | #define PHY_AUTORESPONSE_REQ_MATCH2 0x004 |
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| 576 | #define PHY_AUTORESPONSE_REQ_MATCH3 0x008 |
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| 577 | #define PHY_AUTORESPONSE_REQ_MATCH4 0x010 |
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| 578 | #define PHY_AUTORESPONSE_REQ_MATCH5 0x020 |
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[1232] | 579 | #define PHY_AUTORESPONSE_REQ_MATCH6 0x040 |
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| 580 | #define PHY_AUTORESPONSE_REQ_MATCH7 0x080 |
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[1203] | 581 | |
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[1232] | 582 | #define PHY_AUTORESPONSE_REQ_MATCHALL (PHY_AUTORESPONSE_REQ_MATCH0 | PHY_AUTORESPONSE_REQ_MATCH1 | PHY_AUTORESPONSE_REQ_MATCH2 | PHY_AUTORESPONSE_REQ_MATCH3 | PHY_AUTORESPONSE_REQ_MATCH4 | PHY_AUTORESPONSE_REQ_MATCH5 | PHY_AUTORESPONSE_REQ_MATCH6 | PHY_AUTORESPONSE_REQ_MATCH7) |
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| 583 | #define PHY_AUTORESPONSE_REQ_ALLCONDS (PHY_AUTORESPONSE_REQ_MATCHALL | PHY_AUTORESPONSE_REQ_FLAGA | PHY_AUTORESPONSE_REQ_FLAGB | PHY_AUTORESPONSE_REQ_GOODHDR | PHY_AUTORESPONSE_REQ_BADPKT | PHY_AUTORESPONSE_REQ_GOODPKT) |
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| 584 | |
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[1203] | 585 | //ActionIDs |
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[1232] | 586 | #define PHY_AUTORESPONSE_ACTID_DISABLED ((00<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK) |
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| 587 | #define PHY_AUTORESPONSE_ACTID_SETFLAGA ((62<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK) |
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| 588 | #define PHY_AUTORESPONSE_ACTID_SETFLAGB ((61<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK) |
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[1203] | 589 | #define PHY_AUTORESPONSE_ACTID_TXPKTBUF(c) (( c<<PHY_AUTORESPONSE_ACT_ID_OFFSET) & PHY_AUTORESPONSE_ACT_ID_MASK) |
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| 590 | |
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[1224] | 591 | #define PHY_HEADERTRANSLATE_SET(actionBuf, txByteNum, srcBuf, srcByteNum) \ |
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| 592 | XIo_Out32(\ |
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| 593 | (XPAR_OFDM_TXRX_MIMO_PLBW_0_MEMMAP_TXHEADERTRANSLATE + ((actionBuf)*32*sizeof(int)) + ((txByteNum)*sizeof(int))),\ |
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[1232] | 594 | (((srcBuf) & 0x1F)<<5) | ((srcByteNum) & 0x1F)) |
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[1224] | 595 | |
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[1232] | 596 | //Macro to help construct autoResponse Tx actions |
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[1516] | 597 | #define PHY_AUTORESPONSE_TXACTION_CONFIG(pktBuf, actionOptions, delay, conditions) (\ |
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[1232] | 598 | (PHY_AUTORESPONSE_ACTID_TXPKTBUF(pktBuf) ) | \ |
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[1516] | 599 | (actionOptions & (PHY_AUTORESPONSE_ACT_SWAP_ANT | PHY_AUTORESPONSE_ACT_TRANS_HDR | PHY_AUTORESPONSE_ACT_USE_PRECFO)) | \ |
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[1232] | 600 | (PHY_AUTORESPONSE_MAP_ACT_PARAM(delay) ) | \ |
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| 601 | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS))) |
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[1224] | 602 | |
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[1232] | 603 | //Macro to help construct autoResponse action for setting Flag A |
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| 604 | #define PHY_AUTORESPONSE_ACTION_SETFLAGA_CONFIG(conditions) (PHY_AUTORESPONSE_ACTID_SETFLAGA | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS))) |
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[1203] | 605 | |
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[1232] | 606 | //Macro to help construct autoResponse action for setting Flag B |
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| 607 | #define PHY_AUTORESPONSE_ACTION_SETFLAGB_CONFIG(conditions) (PHY_AUTORESPONSE_ACTID_SETFLAGB | (conditions & (PHY_AUTORESPONSE_REQ_ALLCONDS))) |
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[1203] | 608 | |
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[1260] | 609 | //Flag IDs for user functions |
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| 610 | #define AUTORESP_FLAGID_A 1 |
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| 611 | #define AUTORESP_FLAGID_B 2 |
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| 612 | |
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[869] | 613 | #endif |
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