source: ReferenceDesigns/w3_802.11/c/wlan_mac_high_framework/include/wlan_mac_high.h

Last change on this file was 5877, checked in by chunter, 3 months ago

1) Added new compilation warnings beyond -Wall : -Wclobbered -Wempty-body -Wmissing-field-initializers -Wmissing-parameter-type -Wold-style-declaration -Woverride-init -Wsign-compare -Wtype-limits -Wuninitialized -Wunused-but-set-parameter -Wformat -Wstrict-aliasing -Wshadow

Any warnings that cropped up with the inclusion of these were addressed in this commit

File size: 20.1 KB
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1/** @file wlan_mac_high.h
2 *  @brief Top-level WLAN MAC High Framework
3 *
4 *  This contains the top-level code for accessing the WLAN MAC High Framework.
5 *
6 *  @copyright Copyright 2014-2017, Mango Communications. All rights reserved.
7 *          Distributed under the Mango Communications Reference Design License
8 *                See LICENSE.txt included in the design archive or
9 *                at http://mangocomm.com/802.11/license
10 *
11 *  This file is part of the Mango 802.11 Reference Design (https://mangocomm.com/802.11)
12 */
13
14
15/*************************** Constant Definitions ****************************/
16#ifndef WLAN_MAC_HIGH_H_
17#define WLAN_MAC_HIGH_H_
18
19#include "wlan_mac_high_sw_config.h"
20
21#include "xil_types.h"
22#include "wlan_mac_common.h"
23
24/********************************************************************
25 * Auxiliary (AUX) BRAM and DRAM (DDR) Memory Maps
26
27 * The 802.11 Reference Design hardware includes a 64 KB BRAM block named
28 * AUX BRAM. This block is mapped into the address space of CPU High
29 * and provides a low-latency memory block for data storage beyond the
30 * DLMB.
31 *
32 * The reference code uses the AUX BRAM to store various data structures
33 * that provides references to larger blocks in DRAM. These data structures
34 * benefit from the low-latency access of the BRAM block.
35 *
36 * For example, the doubly-linked list of Tx Queue entries is stored in the
37 * AUX BRAM. Each list entry points to a dedicated 4KB buffer in DRAM. The C code
38 * can manage a queue with quick list operatations in BRAM while the queued packets
39 * themselves are stored in the slower but *much* larger DRAM.
40 *
41 * The 64 KB AUX BRAM block is divided as follows:
42 *
43 * ***************************** AUX BRAM Map *********************************************
44 * Description                      | Size
45 * -------------------------------------------------------------------------------------------------
46 * Tx Queue list entries (entry.data points to DRAM)      | 40960 B (TX_QUEUE_DL_ENTRY_MEM_SIZE)
47 * BSS Info list entries (entry.data points to DRAM)      |  4608 B (BSS_INFO_DL_ENTRY_MEM_SIZE)
48 * Station Info list entries (entry.data points to DRAM)  |  4608 B (STATION_INFO_DL_ENTRY_MEM_SIZE)
49 * ETH A Tx DMA buffer descriptors                        |    64 B (ETH_TX_BD_MEM_SIZE)
50 * ETH A Rx DMA buffer descriptors                        | 15296 B (ETH_RX_BD_MEM_SIZE)
51 * -------------------------------------------------------------------------------------------------
52 *
53 * On WARP v3 1 GB of the DDR3 SO-DIMM DRAM is mapped into the address space of CPU High.
54 * This memory space is used as follows:
55 *
56 * ******************************* DRAM Map *********************************************************
57 * Description                      | Size
58 * --------------------------------------------------------------------------------------------------
59 * wlan_exp Eth buffers             |    1024 KB (WLAN_EXP_ETH_BUFFERS_SECTION_SIZE)
60 * Tx queue buffers                 |    1400 KB (TX_QUEUE_BUFFER_SIZE)
61 * BSS Info buffers                 |      27 KB (BSS_INFO_BUFFER_SIZE)
62 * Station Info buffers             |      69 KB (STATION_INFO_BUFFER_SIZE)
63 * User scratch space               |   10000 KB (USER_SCRATCH_SIZE)
64 * Event log                        | 1036056 KB (EVENT_LOG_SIZE)
65 * --------------------------------------------------------------------------------------------------
66 *
67 *
68 ************************************************************************************************/
69
70
71#define AUX_BRAM_BASE                      (XPAR_MB_HIGH_AUX_BRAM_CTRL_S_AXI_BASEADDR)
72#define AUX_BRAM_SIZE                      (XPAR_MB_HIGH_AUX_BRAM_CTRL_S_AXI_HIGHADDR - XPAR_MB_HIGH_AUX_BRAM_CTRL_S_AXI_BASEADDR + 1)
73#define AUX_BRAM_HIGH                      (XPAR_MB_HIGH_AUX_BRAM_CTRL_S_AXI_HIGHADDR)
74
75#define DRAM_BASE                          (XPAR_DDR3_SODIMM_S_AXI_BASEADDR)
76#define DRAM_SIZE                          (XPAR_DDR3_SODIMM_S_AXI_HIGHADDR - XPAR_DDR3_SODIMM_S_AXI_BASEADDR + 1)
77#define DRAM_HIGH                          (XPAR_DDR3_SODIMM_S_AXI_HIGHADDR)
78
79
80
81#define CALC_HIGH_ADDR(base, size)         ((base)+((size)-1))
82
83
84
85/********************************************************************
86 * wlan_exp and IP/UDP library Ethernet buffers
87 *
88 * The wlan_exp Ethernet handling code uses large buffers for constructing packets
89 * for transmission and for processing received packets. The IP/UDP library uses
90 * multiple buffers to pipeline Ethernet operations. The library also supports jumbo
91 * frames. As a result the wlan_exp and IP/UDP library Ethernet buffers are too large
92 * to store in on-chip BRAM. Instead the first 1MB of the DRAM is reserved for use
93 * by the wlan_exp Ethernet code.
94 *
95 * The linker script for CPU High *must* include a dedicated section allocated at the
96 * base of the DRAM address range. The macros below assume this section exist and
97 * are used to verify the wlan_exp and IP/UDP library code does not overflow the
98 * DRAM allocation.
99 *
100 ********************************************************************/
101#define WLAN_EXP_ETH_BUFFERS_SECTION_BASE   (DRAM_BASE)
102#define WLAN_EXP_ETH_BUFFERS_SECTION_SIZE   (1024 * 1024)
103#define WLAN_EXP_ETH_BUFFERS_SECTION_HIGH   CALC_HIGH_ADDR(WLAN_EXP_ETH_BUFFERS_SECTION_BASE, WLAN_EXP_ETH_BUFFERS_SECTION_SIZE)
104
105
106/********************************************************************
107 * TX Queue
108 *
109 * The Tx Queue consists of two pieces:
110 *     (1) dl_entry structs that live in the AUX BRAM
111 *     (2) Data buffers for the packets themselves than live in DRAM
112 *
113 * The definitions below reserve memory for these two pieces.  The default
114 * value of 40 kB do the dl_entry memory space was chosen. Because each dl_entry has a
115 * size of 12 bytes, this space allows for a potential of 3413 dl_entry structs describing
116 * Tx queue elements.
117 *
118 * As far as the actual payload space in DRAM, 14000 kB was chosen because this is enough
119 * to store each of the 3413 Tx queue elements. Each queue element points to a unique 4KB-sized
120 * buffer.
121 *
122 ********************************************************************/
123
124#define TX_QUEUE_DL_ENTRY_MEM_BASE         (AUX_BRAM_BASE)
125#define TX_QUEUE_DL_ENTRY_MEM_SIZE         (40 * 1024)
126#define TX_QUEUE_DL_ENTRY_MEM_HIGH          CALC_HIGH_ADDR(TX_QUEUE_DL_ENTRY_MEM_BASE, TX_QUEUE_DL_ENTRY_MEM_SIZE)
127
128#define TX_QUEUE_BUFFER_BASE               (WLAN_EXP_ETH_BUFFERS_SECTION_HIGH + 1)
129#define TX_QUEUE_BUFFER_SIZE               (14000 * 1024)
130#define TX_QUEUE_BUFFER_HIGH                CALC_HIGH_ADDR(TX_QUEUE_BUFFER_BASE, TX_QUEUE_BUFFER_SIZE)
131
132
133
134/********************************************************************
135 * BSS Info
136 *
137 * The BSS Info storage consists of two pieces:
138 *     (1) dl_entry structs that live in the aux. BRAM and
139 *     (2) bss_info_t buffers with the actual content that live in DRAM
140 *
141 ********************************************************************/
142#define BSS_INFO_DL_ENTRY_MEM_BASE         (TX_QUEUE_DL_ENTRY_MEM_BASE + TX_QUEUE_DL_ENTRY_MEM_SIZE)
143#define BSS_INFO_DL_ENTRY_MEM_SIZE         (4608)
144#define BSS_INFO_DL_ENTRY_MEM_HIGH          CALC_HIGH_ADDR(BSS_INFO_DL_ENTRY_MEM_BASE, BSS_INFO_DL_ENTRY_MEM_SIZE)
145
146#define BSS_INFO_BUFFER_BASE               (TX_QUEUE_BUFFER_HIGH + 1)
147#define BSS_INFO_BUFFER_SIZE               ((BSS_INFO_DL_ENTRY_MEM_SIZE/sizeof(dl_entry))*sizeof(bss_info_t))
148#define BSS_INFO_BUFFER_HIGH                CALC_HIGH_ADDR(BSS_INFO_BUFFER_BASE, BSS_INFO_BUFFER_SIZE)
149
150
151/********************************************************************
152 * Station Info
153 *
154 * The Station Info storage consists of two pieces:
155 *     (1) dl_entry structs that live in the aux. BRAM and
156 *     (2) station_info_t buffers with the actual content that live in DRAM
157 *
158 ********************************************************************/
159#define STATION_INFO_DL_ENTRY_MEM_BASE     (BSS_INFO_DL_ENTRY_MEM_HIGH + 1)
160#define STATION_INFO_DL_ENTRY_MEM_SIZE     (4608)
161#define STATION_INFO_DL_ENTRY_MEM_NUM      (STATION_INFO_DL_ENTRY_MEM_SIZE/sizeof(dl_entry))
162#define STATION_INFO_DL_ENTRY_MEM_HIGH      CALC_HIGH_ADDR(STATION_INFO_DL_ENTRY_MEM_BASE, STATION_INFO_DL_ENTRY_MEM_SIZE)
163
164#define STATION_INFO_BUFFER_BASE          (BSS_INFO_BUFFER_HIGH + 1)
165#define STATION_INFO_BUFFER_SIZE          ((STATION_INFO_DL_ENTRY_MEM_SIZE/sizeof(dl_entry))*sizeof(station_info_t))
166#define STATION_INFO_BUFFER_HIGH           CALC_HIGH_ADDR(STATION_INFO_BUFFER_BASE, STATION_INFO_BUFFER_SIZE)
167
168
169
170/********************************************************************
171 * Ethernet TX Buffer Descriptors
172 *
173 * The current architecture blocks on Ethernet transmissions. As such, only a single
174 * Eth DMA buffer descriptor (BD) is needed. Each BD is 64 bytes in size (see
175 * XAXIDMA_BD_MINIMUM_ALIGNMENT), so we set ETH_TX_BD_SIZE to 64.
176 *
177 ********************************************************************/
178#define ETH_DMA_BD_SIZE                64 // hard-code sizeof(XAxiDma_Bd) to avoid including axi_dma header
179
180#define ETH_TX_BD_MEM_BASE                     (STATION_INFO_DL_ENTRY_MEM_HIGH + 1)
181#define ETH_TX_BD_MEM_SIZE                     (1 * ETH_DMA_BD_SIZE)
182#define ETH_TX_BD_MEM_HIGH                      CALC_HIGH_ADDR(ETH_TX_BD_MEM_BASE, ETH_TX_BD_MEM_SIZE)
183
184
185
186/********************************************************************
187 * Ethernet RX Buffer Descriptors
188 *
189 * The last section we are defining in the aux. BRAM is for ETH_RX.
190 * Like TX, each BD is 64 bytes. Unlike TX, we need more than a single
191 * BD to be able to handle bursty Ethernet receptions.
192 *
193 ********************************************************************/
194#define ETH_RX_BD_MEM_BASE                     (ETH_TX_BD_MEM_HIGH + 1)
195#define ETH_RX_BD_MEM_SIZE                     (239 * ETH_DMA_BD_SIZE)
196#define ETH_RX_BD_MEM_HIGH                      CALC_HIGH_ADDR(ETH_RX_BD_MEM_BASE, ETH_RX_BD_MEM_SIZE)
197
198
199
200/********************************************************************
201 * User Scratch Space
202 *
203 * We have set aside 10MB of space for users to use the DRAM in their applications.
204 * We do not use the below definitions in any part of the reference design.
205 *
206 ********************************************************************/
207#define USER_SCRATCH_BASE                  (STATION_INFO_BUFFER_HIGH + 1)
208#define USER_SCRATCH_SIZE                  (10000 * 1024)
209#define USER_SCRATCH_HIGH                   CALC_HIGH_ADDR(USER_SCRATCH_BASE, USER_SCRATCH_SIZE)
210
211
212/********************************************************************
213 * Event Log
214 *
215 * The remaining space in DRAM is used for the WLAN Experiment Framework event log. The above
216 * sections in DRAM are much smaller than the space set aside for the event log. In the current
217 * implementation, the event log is ~995 MB.
218 *
219 ********************************************************************/
220#define EVENT_LOG_BASE                     (USER_SCRATCH_HIGH + 1)
221#define EVENT_LOG_SIZE                     (DRAM_HIGH - EVENT_LOG_BASE + 1) // log occupies all remianing DRAM
222#define EVENT_LOG_HIGH                      CALC_HIGH_ADDR(EVENT_LOG_BASE, EVENT_LOG_SIZE)
223
224
225
226//-----------------------------------------------
227// Device IDs
228//
229// NOTE:  These are re-definitions of xparameters.h #defines so that the name of the
230//     underlying hardware component can change and it will only require modifying
231//     one line of code in the SDK project.
232//
233#define INTC_DEVICE_ID                                     XPAR_INTC_0_DEVICE_ID              ///< XParameters rename of interrupt controller device ID
234#define UARTLITE_DEVICE_ID                                 XPAR_UARTLITE_0_DEVICE_ID          ///< XParameters rename for UART
235#define GPIO_USERIO_DEVICE_ID                              XPAR_MB_HIGH_SW_GPIO_DEVICE_ID     ///< XParameters rename of device ID of GPIO
236
237//-----------------------------------------------
238// Interrupt IDs
239//
240//  These macros define the index of each interrupt signal in the axi_intc input
241//  The defines below rename macros from xparameters.h to remove instance-name-specific
242//    strings from the application code
243#define INTC_GPIO_USERIO_INTERRUPT_ID                      XPAR_MB_HIGH_INTC_MB_HIGH_SW_GPIO_IP2INTC_IRPT_INTR               ///< XParameters rename of GPIO interrupt ID
244#define UARTLITE_INT_IRQ_ID                                XPAR_INTC_0_UARTLITE_0_VEC_ID      ///< XParameters rename of UART interrupt ID
245#define TMRCTR_INTERRUPT_ID                                XPAR_INTC_0_TMRCTR_0_VEC_ID        ///< XParameters rename of timer interrupt ID
246
247
248
249//-----------------------------------------------
250// WLAN Constants
251//
252#define ENCAP_MODE_AP                                      0                                  ///< Used as a flag for AP encapsulation and de-encapsulation
253#define ENCAP_MODE_STA                                     1                                  ///< Used as a flag for STA encapsulation and de-encapsulation
254#define ENCAP_MODE_IBSS                                    2                                  ///< Used as a flag for IBSS encapsulation and de-encapsulation
255
256#define TX_BUFFER_NUM                                      2                                  ///< Number of PHY transmit buffers to use. This should remain 2 (ping/pong buffering).
257
258#define GPIO_USERIO_INPUT_CHANNEL                          1                                  ///< Channel used as input user IO inputs (buttons, DIP switch)
259#define GPIO_USERIO_INPUT_IR_CH_MASK                       XGPIO_IR_CH1_MASK                  ///< Mask for enabling interrupts on GPIO input
260
261#define GPIO_MASK_DRAM_INIT_DONE                           0x00000100                         ///< Mask for GPIO -- DRAM initialization bit
262#define GPIO_MASK_PB_U                                     0x00000040                         ///< Mask for GPIO -- "Up" Pushbutton
263#define GPIO_MASK_PB_M                                     0x00000020                         ///< Mask for GPIO -- "Middle" Pushbutton
264#define GPIO_MASK_PB_D                                     0x00000010                         ///< Mask for GPIO -- "Down" Pushbutton
265#define GPIO_MASK_DS_3                                     0x00000008                         ///< Mask for GPIO -- MSB of Dip Switch
266
267#define UART_BUFFER_SIZE                                   1                                  ///< UART is configured to read 1 byte at a time
268
269#define NUM_VALID_RATES                                    12                                 ///< Number of supported rates
270
271
272//-----------------------------------------------
273// Callback Return Flags
274//
275#define MAC_RX_CALLBACK_RETURN_FLAG_DUP                         0x00000001
276#define MAC_RX_CALLBACK_RETURN_FLAG_NO_COUNTS                   0x00000002
277#define MAC_RX_CALLBACK_RETURN_FLAG_NO_LOG_ENTRY                0x00000004
278
279
280/***************************** Include Files *********************************/
281
282/********************************************************************
283 * Include other framework headers
284 *
285 * NOTE:  Includes have to be after any #define that are needed in the typedefs within the includes.
286 *
287 ********************************************************************/
288#include "wlan_mac_queue.h"
289#include "wlan_mac_packet_types.h"
290#include "wlan_mac_mailbox_util.h"
291#include "wlan_mac_dl_list.h"
292
293
294
295/************************** Global Type Definitions **************************/
296
297typedef enum {INTERRUPTS_DISABLED, INTERRUPTS_ENABLED} interrupt_state_t;
298
299
300
301/******************** Global Structure/Enum Definitions **********************/
302
303/***************************** Global Constants ******************************/
304
305extern const  u8 bcast_addr[MAC_ADDR_LEN];
306extern const  u8 zero_addr[MAC_ADDR_LEN];
307
308
309/*************************** Function Prototypes *****************************/
310void               wlan_mac_high_init();
311void               wlan_mac_high_malloc_init();
312
313int                wlan_mac_high_interrupt_init();
314
315int                wlan_mac_high_interrupt_restore_state(interrupt_state_t new_interrupt_state);
316interrupt_state_t  wlan_mac_high_interrupt_stop();
317
318void               wlan_mac_high_uart_rx_handler(void *CallBackRef, unsigned int EventData);
319void               wlan_mac_high_userio_gpio_handler(void *InstancePtr);
320
321dl_entry*          wlan_mac_high_find_counts_ADDR(dl_list* list, u8* addr);
322
323u32                wlan_mac_high_get_user_io_state();
324
325void               wlan_mac_high_set_pb_u_callback(function_ptr_t callback);
326void               wlan_mac_high_set_pb_m_callback(function_ptr_t callback);
327void               wlan_mac_high_set_pb_d_callback(function_ptr_t callback);
328void               wlan_mac_high_set_uart_rx_callback(function_ptr_t callback);
329void               wlan_mac_high_set_mpdu_tx_high_done_callback(function_ptr_t callback);
330void               wlan_mac_high_set_mpdu_tx_low_done_callback(function_ptr_t callback);
331void               wlan_mac_high_set_beacon_tx_done_callback(function_ptr_t callback);
332void               wlan_mac_high_set_mpdu_rx_callback(function_ptr_t callback);
333void               wlan_mac_high_set_poll_tx_queues_callback(function_ptr_t callback);
334void               wlan_mac_high_set_mpdu_dequeue_callback(function_ptr_t callback);
335void               wlan_mac_high_set_cpu_low_reboot_callback(function_ptr_t callback);
336
337void*              wlan_mac_high_malloc(u32 size);
338void*              wlan_mac_high_calloc(u32 size);
339void*              wlan_mac_high_realloc(void* addr, u32 size);
340void               wlan_mac_high_free(void* addr);
341void               wlan_mac_high_display_mallinfo();
342
343int                wlan_mac_high_memory_test();
344int                wlan_mac_high_right_shift_test();
345
346int                wlan_mac_high_cdma_start_transfer(void* dest, void* src, u32 size);
347void               wlan_mac_high_cdma_finish_transfer();
348
349void               wlan_mac_high_mpdu_transmit(dl_entry* packet, int tx_pkt_buf);
350
351u8                 wlan_mac_high_valid_tagged_rate(u8 rate);
352void               wlan_mac_high_tagged_rate_to_readable_rate(u8 rate, char* str);
353
354void               wlan_mac_high_setup_tx_header( mac_header_80211_common * header, u8 * addr_1, u8 * addr_3 );
355void               wlan_mac_high_setup_tx_frame_info(mac_header_80211_common * header, dl_entry * curr_tx_queue_element, u32 tx_length, u8 flags, u8 queue_id, pkt_buf_group_t pkt_buf_group);
356
357void               wlan_mac_high_ipc_rx();
358void               wlan_mac_high_process_ipc_msg(wlan_ipc_msg_t * msg);
359
360void               wlan_mac_high_set_srand(u32 seed);
361u8                 wlan_mac_high_bss_channel_spec_to_radio_chan(chan_spec_t chan_spec);
362void               wlan_mac_high_set_radio_channel(u32 mac_channel);
363void               wlan_mac_high_enable_mcast_buffering(u8 enable);
364void               wlan_mac_high_config_txrx_beacon(beacon_txrx_configure_t* beacon_txrx_configure);
365void               wlan_mac_high_set_rx_ant_mode(u8 ant_mode);
366void               wlan_mac_high_set_tx_ctrl_pow(s8 pow);
367void               wlan_mac_high_set_rx_filter_mode(u32 filter_mode);
368void               wlan_mac_high_set_dsss(u32 dsss_value);
369
370int                wlan_mac_high_write_low_mem(u32 num_words, u32* payload);
371int                wlan_mac_high_read_low_mem(u32 num_words, u32 baseaddr, u32* payload);
372int                wlan_mac_high_write_low_param(u32 num_words, u32* payload);
373
374void               wlan_mac_high_request_low_state();
375int                wlan_mac_high_is_cpu_low_initialized();
376int                wlan_mac_high_is_dequeue_allowed(pkt_buf_group_t pkt_buf_group);
377int                wlan_mac_high_get_empty_tx_packet_buffer();
378u8                 wlan_mac_high_is_pkt_ltg(void* mac_payload, u16 length);
379
380
381int                wlan_mac_high_configure_beacon_tx_template(mac_header_80211_common* tx_header_common_ptr, bss_info_t* bss_info, tx_params_t* tx_params_ptr, u8 flags);
382int                wlan_mac_high_update_beacon_tx_params(tx_params_t* tx_params_ptr);
383
384
385void               wlan_mac_high_print_station_infos(dl_list* assoc_tbl);
386
387
388// Common functions that must be implemented by users of the framework
389// TODO: Make these into callback. We should not require these implementations
390dl_list*          get_bss_member_list();
391
392#endif /* WLAN_MAC_HIGH_H_ */
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