1 | addpath('./mcode_blocks'); |
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2 | |
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3 | %Maximum interval values in usec |
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4 | % These determine bit widths of counters |
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5 | MAX_SLOT = 63; |
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6 | MAX_DIFS = 63; |
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7 | MAX_EIFS = 255; |
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8 | MAX_NAV = 4095; |
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9 | MAX_NUM_SLOTS = 2^16-1; |
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10 | |
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11 | %Calculate bit widths |
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12 | % All counters run at 160MHz (1/160 usec) |
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13 | NB_CNTR_SLOT = ceil(log2(MAX_SLOT * 160)); |
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14 | NB_CNTR_DIFS = max(ceil(log2(MAX_DIFS * 160)), ceil(log2(MAX_EIFS * 160))); |
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15 | NB_CNTR_NAV = ceil(log2(MAX_NAV * 160)); |
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16 | NB_CNTR_NUM_SLOTS = ceil(log2(MAX_NUM_SLOTS)); |
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17 | NB_CNTR_POSTRX = 19; %big enough for SIFS and timeout |
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18 | |
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19 | %Max hardware latencies, used to calculate various MAC intervals |
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20 | PHY_RX_START_DLY = 25; |
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21 | |
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22 | %Actual hardware latencies, used to calibrate MAC intervals |
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23 | |
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24 | %D1: RxRfDelay + RxPLCPDelay |
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25 | % After pkt reception, D1 is delay from actual medium IDLE to PHY_RX_END |
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26 | hw_time_D1 = 1; |
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27 | |
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28 | %RxTx Turnaround |
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29 | % Time from PHY_TX_START.IND to PHY_TX_START.CONFIRM |
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30 | % (delay from "transmit now" signal to first energy on medium) |
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31 | hw_time_rxtx_turnaround = 1; |
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32 | |
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33 | |
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34 | ticks_per_usec = 10; |
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35 | |
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36 | %%%%%%%%%%%%%%%%%%%%%%%%% |
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37 | % MAC timing parameters |
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38 | INTERVAL_SIFS = 10; |
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39 | INTERVAL_SLOT = 9; |
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40 | INTERVAL_DIFS = INTERVAL_SIFS + 2*INTERVAL_SLOT; |
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41 | INTERVAL_EIFS = INTERVAL_SIFS + INTERVAL_DIFS + 100; %guess TACK_slow for now |
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42 | INTERVAL_ACKTIMEOUT = INTERVAL_SIFS + INTERVAL_SLOT + PHY_RX_START_DLY; |
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43 | |
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44 | %%%%%%%%%%%%%%%%%%%%%%%%% |
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45 | % Calibrated MAC times |
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46 | |
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47 | %TxDIFS: instant to sample medium status after successful Rx |
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48 | calib_time_TxDIFS = INTERVAL_DIFS - hw_time_D1 - hw_time_rxtx_turnaround; |
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49 | |
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50 | %Adjustment for NAV times, to compensate dealy from actual idle to RX_END+FCS |
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51 | calib_time_NAV_adj = 0; |
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52 | |
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53 | REG_MAC_Intervals_1 = ... |
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54 | 2^0 * (10*INTERVAL_SLOT) + ... %b[9:0] |
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55 | 2^20 * (10*INTERVAL_DIFS) + ... %b[29:20] |
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56 | 0; |
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57 | |
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58 | REG_MAC_Intervals_2 = ... |
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59 | 2^0 * (10*INTERVAL_EIFS) + ... %b[15:0] |
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60 | 2^16 * (10*INTERVAL_ACKTIMEOUT) + ... %b[31:16] |
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61 | 0; |
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62 | |
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63 | REG_MAC_Calib_Times = ... |
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64 | 2^0 * (10*calib_time_TxDIFS) + ... %b[9:0] |
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65 | 2^24 * (10*calib_time_NAV_adj) + ... %b[31:24] |
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66 | 0; |
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67 | |
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68 | REG_MAC_Tx_Ctrl_A_Params = 0; |
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69 | |
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70 | REG_MAC_Tx_Ctrl_B_Params = 0; |
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71 | |
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72 | REG_MAC_Tx_Ctrl_C_Params = 0; |
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73 | |
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74 | REG_MAC_Tx_Ctrl_D_Params = 0; |
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75 | |
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76 | REG_MAC_PostRxTimers = ... |
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77 | 2^0 * (10*16) + ... %b[14:0] - timer 1 value |
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78 | 2^15 * (0) + ... %b[15] - enable timer 1 |
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79 | 2^16 * (10*16) + ... %b[30:16] - timer 2 value |
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80 | 2^31 * (0) + ... %b[31] - enable timer 2 |
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81 | 0; |
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82 | |
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83 | REG_MAC_PostTxTimers = ... |
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84 | 2^0 * (10*16) + ... %b[14:0] - timer 1 value |
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85 | 2^15 * (0) + ... %b[15] - enable timer 1 |
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86 | 2^16 * (10*16) + ... %b[30:16] - timer 2 value |
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87 | 2^31 * (0) + ... %b[31] - enable timer 2 |
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88 | 0; |
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89 | |
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90 | |
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91 | REG_MAC_Backoff_Control = ... |
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92 | 2^0 * (0) + ... %b[15:0] - num BO slots |
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93 | 2^31 * (0) + ... %b[31] - Start backoff period immediately |
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94 | 0; |
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95 | |
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96 | REG_MAC_Control = ... |
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97 | 2^0 * (0) + ... %b[0] Reset |
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98 | 2^1 * (0) + ... %b[1] Disable NAV |
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99 | 2^2 * (0) + ... %b[2] Reset NAV |
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100 | 2^3 * (1) + ... %b[3] Block Rx on Tx |
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101 | 2^4 * (0) + ... %b[4] Reset TU latch |
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102 | 2^5 * (0) + ... %b[5] Ignore Rx PHY for CCA |
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103 | 2^6 * (0) + ... %b[6] Ignore Tx PHY for CCA |
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104 | 2^7 * (0) + ... %b[7] Ignore NAV for CCA |
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105 | 2^8 * (0) + ... %b[8] Force CCA=BUSY |
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106 | 2^9 * (0) + ... %b[9] -- |
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107 | 2^10 * (0) + ... %b[10] Reset RX_STARTED latch |
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108 | 2^11 * (0) + ... %b[11] Reset Tx controller A |
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109 | 2^12 * (0) + ... %b[12] Reset Tx controller B |
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110 | 2^13 * (0) + ... %b[13] Reset Tx controller C |
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111 | 2^14 * (0) + ... %b[14] Reset Tx controller D |
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112 | 2^15 * (0) + ... %b[15] Reset Tx controller A backoff |
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113 | 2^16 * (0) + ... %b[16] Reset Tx controller C backoff |
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114 | 2^17 * (0) + ... %b[17] Reset Tx controller D backoff |
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115 | 2^18 * (0) + ... %b[18] Pause Tx controller A |
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116 | 2^19 * (0) + ... %b[19] Pause Tx controller C |
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117 | 2^20 * (0) + ... %b[20] Pause Tx controller D |
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118 | 2^21 * (0) + ... %b[21] Enbale ext CCA.BUSY input |
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119 | 2^22 * (0) + ... %b[22] Enable ext PostRx Timer 1 start |
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120 | 2^23 * (0) + ... %b[23] Reset Rx PHY active latches |
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121 | 2^24 * (0) + ... %b[24] Reset Tx PHY active latch |
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122 | 0; |
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123 | |
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124 | %Match 40-d8-55-04-21-4a |
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125 | %REG_NAV_Match_Addr_1 = hex2dec('0455d840'); |
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126 | %REG_NAV_Match_Addr_2 = hex2dec('00004a21'); |
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127 | |
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128 | %Default to zeros - won't match anything until overwritten by software |
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129 | REG_NAV_Match_Addr_1 = 0; |
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130 | REG_NAV_Match_Addr_2 = 0; |
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131 | |
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132 | mac_sim_rx_data_b.time = []; |
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133 | mac_sim_rx_data_b.signals.values = sscanf('48 11 2c 00 40 d8 55 04 21 4a 40 d8 55 04 21 5a 40 d8 55 04 21 4a f0 92 f7 db e5 d9 ', '%02x'); |
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134 | NUM_BYTES = length(mac_sim_rx_data_b.signals.values); |
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135 | |
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136 | mac_sim_rx_data_valid.time = []; |
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137 | mac_sim_rx_data_valid.signals.values = [zeros(1, NUM_BYTES) ones(1, NUM_BYTES) zeros(1, NUM_BYTES)].'; |
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138 | |
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139 | mac_sim_rx_data_addr.time = []; |
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140 | mac_sim_rx_data_addr.signals.values = [zeros(1, NUM_BYTES) 0:NUM_BYTES-1 zeros(1, NUM_BYTES)].'; |
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141 | |
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142 | |
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143 | |
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