1 | // This file is copyright 2013 by Rice University and was ported from the |
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2 | // original WARP OFDM Reference Design. It is distributed under the WARP license: |
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3 | // http://warpproject.org/license |
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4 | |
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5 | //***************************************************************** |
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6 | // File: vb_decoder_top.v |
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7 | // Author: Yang Sun (ysun@rice.edu) |
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8 | // Birth: $ 1/15/07 |
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9 | // Des: viterbi decoder top level |
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10 | // Take 5 bit soft value is [-16 : +15] |
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11 | // K = 3. g0 =7, g1 = 5 |
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12 | // K = 7. g0 = 133, g1 = 171 |
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13 | // History: $ 1/15/07, Init coding |
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14 | // $ 1/21/07, K = 7 |
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15 | // $ 1/27/07, Change to LLR domain |
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16 | // $ 2/4/07, Support puncture 2/3, 3/4 |
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17 | // $ 3/22/07, Remove puncture and iq buffer for WARP |
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18 | // $ 3/23/07, Fixed a naming problem for sysgen |
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19 | // Can not use VHDL reserved key world |
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20 | // $ 4/20/07, K = 7 |
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21 | // $ 4/22/07, Change quantilization to -4 ~ 4 9-level |
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22 | // $ 12/1/07: Modified for OFDM V7 |
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23 | //***************************************************************** |
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24 | module vb_decoder_top ( |
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25 | clk , // I, clock |
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26 | ce , // I, clock enable (ignored, but required for Sysgen blackbox) |
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27 | nrst , // I, n reset |
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28 | packet_start, // I, packet start pulse |
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29 | packet_end , // I, packet end pulse |
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30 | vin , // I, valid input |
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31 | llr_b1 , // I, 1st LLR |
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32 | llr_b0 , // I, 2nd LLR |
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33 | vout , // O, valid output |
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34 | dout_in_byte, // O, decoded output in byte |
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35 | done, // O, decoding done |
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36 | early_trace1, |
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37 | early_trace2 |
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38 | ) ; |
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39 | parameter SW = 4 ; // soft input precision |
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40 | //parameter M = 7 ; // Metric precision |
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41 | parameter M = 8 ; // Metric precision |
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42 | |
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43 | parameter R_EARLY1 = 24; //Early total trace depth |
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44 | parameter C_EARLY1 = 0; //Early unreliable trace |
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45 | parameter L_EARLY1 = 24; //Early reliable trace trace |
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46 | |
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47 | parameter R_EARLY2 = 48; //Early total trace depth |
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48 | parameter C_EARLY2 = 0; //Early unreliable trace |
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49 | parameter L_EARLY2 = 48; //Early reliable trace trace |
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50 | |
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51 | //parameter L = 24 ; // total trace depth //WLAN |
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52 | //parameter R = 24 ; // reliable trace |
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53 | //parameter C = 0 ; // unreliable trace |
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54 | |
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55 | parameter L = 88 ; // total trace depth |
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56 | parameter R = 48 ; // reliable trace |
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57 | parameter C = 40 ; // unreliable trace |
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58 | |
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59 | parameter LW = 7 ; // L width |
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60 | parameter K = 7 ; // constraint length |
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61 | parameter N = 64 ; // number of states |
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62 | parameter TR = 128 ; // trace buffer depth |
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63 | parameter TRW = 7 ; // trace buffer address width |
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64 | |
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65 | input clk ; // system clock |
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66 | input ce ; |
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67 | input nrst ; // active low reset |
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68 | input packet_start ; // start of packet pulse |
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69 | input packet_end ; // end of packet pulse |
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70 | input vin ; // data valid input |
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71 | input [4 -1:0] llr_b1 ; // soft value for bit1 |
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72 | input [4 -1:0] llr_b0 ; // soft value for bit0 |
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73 | |
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74 | input early_trace1; |
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75 | input early_trace2; |
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76 | |
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77 | output done ; |
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78 | output vout ; |
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79 | output [7:0] dout_in_byte ; |
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80 | |
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81 | //============================================= |
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82 | //Internal signal |
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83 | //============================================= |
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84 | wire [LW -1:0] remain ; |
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85 | wire dec_vout ; |
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86 | wire [R-1:0] dec_dout ; |
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87 | wire dec_done ; |
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88 | wire early_dec_vout; |
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89 | |
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90 | //============================================= |
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91 | // Main RTL code |
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92 | //============================================= |
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93 | |
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94 | //================================================================ |
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95 | // Viterbi decoder core logic |
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96 | //================================================================ |
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97 | //viterbi_core #(SW, M, R, C, L, LW, K, N, TR, TRW) viterbi_core ( |
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98 | viterbi_core viterbi_core ( |
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99 | .clk (clk ), //IN |
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100 | .nrst (nrst ), //IN |
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101 | .packet_start (packet_start ), //IN |
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102 | .packet_end (packet_end ), //IN |
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103 | .zero_tail (1'b1 ), |
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104 | .dv_in (vin ), //IN |
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105 | .llr1 (llr_b1 ), //IN[SW-1:0] |
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106 | .llr0 (llr_b0 ), //IN[SW-1:0] |
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107 | .remain (remain ), //OUT[LW -1:0] |
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108 | .done (dec_done ), //OUT |
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109 | .dv_out (dec_vout ), //OUT |
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110 | .dout (dec_dout ), //OUT[R -1:0] |
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111 | .early_trace1 (early_trace1), |
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112 | .early_trace2 (early_trace2) |
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113 | ) ; |
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114 | defparam viterbi_core.SW = SW; |
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115 | defparam viterbi_core.M = M; |
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116 | |
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117 | defparam viterbi_core.R = R; |
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118 | defparam viterbi_core.C = C; |
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119 | defparam viterbi_core.L = L; |
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120 | |
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121 | defparam viterbi_core.R_EARLY1 = R_EARLY1; |
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122 | defparam viterbi_core.C_EARLY1 = C_EARLY1; |
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123 | defparam viterbi_core.L_EARLY1 = L_EARLY1; |
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124 | |
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125 | defparam viterbi_core.R_EARLY2 = R_EARLY2; |
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126 | defparam viterbi_core.C_EARLY2 = C_EARLY2; |
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127 | defparam viterbi_core.L_EARLY2 = L_EARLY2; |
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128 | |
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129 | defparam viterbi_core.LW = LW; |
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130 | defparam viterbi_core.K = K; |
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131 | defparam viterbi_core.N = N; |
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132 | defparam viterbi_core.TR = TR; |
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133 | defparam viterbi_core.TRW = TRW; |
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134 | |
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135 | //============================================= |
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136 | // x to 8bit unpacking |
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137 | //============================================= |
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138 | unpack_m2n unpack_Rto8 ( |
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139 | .clk (clk ), //IN |
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140 | .nrst (nrst ), //IN |
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141 | .start (packet_start ), //IN |
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142 | .din (dec_dout ), //IN[R -1:0] |
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143 | .vin (dec_vout ), //IN |
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144 | .last (dec_done ), //IN |
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145 | .remain (remain ), //IN[LW -1:0] |
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146 | .dout (dout_in_byte ), //OUT |
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147 | .vout (vout ), //OUT |
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148 | .done (done ), //OUT |
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149 | .early_trace( early_trace1 ) //IN |
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150 | ) ; |
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151 | |
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152 | defparam unpack_Rto8.BITM = R; |
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153 | defparam unpack_Rto8.BITM_EARLY = R_EARLY1; |
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154 | defparam unpack_Rto8.BITN = 8; |
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155 | defparam unpack_Rto8.LW = LW; |
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156 | |
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157 | endmodule |
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