function fec_decoder_config(this_block)

  % Revision History:
  %
  %   12-Oct-2010  (03:00 hours):
  %     Original code was machine generated by Xilinx's System Generator after parsing
  %     E:\My Dropbox\Project\WARP\Sysgen\Rev5\fec_decoder.v
  %
  %

  this_block.setTopLevelLanguage('Verilog');

  this_block.setEntityName('fec_decoder');

  % System Generator has to assume that your entity  has a combinational feed through; 
  %   if it  doesn't, then comment out the following line:
  this_block.tagAsCombinational;

  this_block.addSimulinkInport('nrst');
  this_block.addSimulinkInport('fec_reg');
  this_block.addSimulinkInport('start');
  this_block.addSimulinkInport('vin');
  this_block.addSimulinkInport('xk_index');
  this_block.addSimulinkInport('mod_level');
  this_block.addSimulinkInport('rx_i');
  this_block.addSimulinkInport('rx_q');

  this_block.addSimulinkOutport('rx_we');
  this_block.addSimulinkOutport('rx_addr');
  this_block.addSimulinkOutport('rx_data');
  this_block.addSimulinkOutport('rx_done');
  this_block.addSimulinkOutport('rx_we_2');
  this_block.addSimulinkOutport('rx_addr_2');
  this_block.addSimulinkOutport('rx_data_2');
  this_block.addSimulinkOutport('rx_done_2');

  rx_we_port = this_block.port('rx_we');
  % rx_we_port.setType('UFix_1_0');
  rx_we_port.setType('UFix_1_0');
  rx_we_port.useHDLVector(false);
  rx_addr_port = this_block.port('rx_addr');
  rx_addr_port.setType('UFix_14_0');
  rx_data_port = this_block.port('rx_data');
  rx_data_port.setType('UFix_8_0');
  rx_done_port = this_block.port('rx_done');
  % rx_done_port.setType('UFix_1_0');
  rx_done_port.setType('UFix_1_0');
  rx_done_port.useHDLVector(false);
  rx_we_2_port = this_block.port('rx_we_2');
  % rx_we_2_port.setType('UFix_1_0');
  rx_we_2_port.setType('Bool');
  rx_we_2_port.useHDLVector(false);
  rx_addr_2_port = this_block.port('rx_addr_2');
  rx_addr_2_port.setType('UFix_14_0');
  rx_data_2_port = this_block.port('rx_data_2');
  rx_data_2_port.setType('UFix_8_0');
  rx_done_2_port = this_block.port('rx_done_2');
  % rx_done_2_port.setType('UFix_1_0');
  rx_done_2_port.setType('Bool');
  rx_done_2_port.useHDLVector(false);

  % -----------------------------
  if (this_block.inputTypesKnown)
    % do input type checking, dynamic output type and generic setup in this code block.

    if (this_block.port('nrst').width ~= 1);
      this_block.setError('Input data type for port "nrst" must have width=1.');
    end

    this_block.port('nrst').useHDLVector(false);

    if (this_block.port('fec_reg').width ~= 32);
      this_block.setError('Input data type for port "fec_reg" must have width=32.');
    end

    if (this_block.port('start').width ~= 1);
      this_block.setError('Input data type for port "start" must have width=1.');
    end

    this_block.port('start').useHDLVector(false);

    if (this_block.port('vin').width ~= 1);
      this_block.setError('Input data type for port "vin" must have width=1.');
    end

    this_block.port('vin').useHDLVector(false);

    if (this_block.port('xk_index').width ~= 6);
      this_block.setError('Input data type for port "xk_index" must have width=6.');
    end

    if (this_block.port('mod_level').width ~= 4);
      this_block.setError('Input data type for port "mod_level" must have width=4.');
    end

    if (this_block.port('rx_i').width ~= 16);
      this_block.setError('Input data type for port "rx_i" must have width=16.');
    end

    if (this_block.port('rx_q').width ~= 16);
      this_block.setError('Input data type for port "rx_q" must have width=16.');
    end

  end  % if(inputTypesKnown)
  % -----------------------------

  % -----------------------------
   if (this_block.inputRatesKnown)
     setup_as_single_rate(this_block,'clk','ce')
   end  % if(inputRatesKnown)
  % -----------------------------

    % (!) Set the inout port rate to be the same as the first input 
    %     rate. Change the following code if this is untrue.
    uniqueInputRates = unique(this_block.getInputRates);


  % Add addtional source files as needed.
  %  |-------------
  %  | Add files in the order in which they should be compiled.
  %  | If two files "a.vhd" and "b.vhd" contain the entities
  %  | entity_a and entity_b, and entity_a contains a
  %  | component of type entity_b, the correct sequence of
  %  | addFile() calls would be:
  %  |    this_block.addFile('b.vhd');
  %  |    this_block.addFile('a.vhd');
  %  |-------------

  %    this_block.addFile('');
  %    this_block.addFile('');
  this_block.addFile('fec_decoder.v');

return;


% ------------------------------------------------------------

function setup_as_single_rate(block,clkname,cename) 
  inputRates = block.inputRates; 
  uniqueInputRates = unique(inputRates); 
  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
    block.addError('The inputs to this block cannot all be constant.'); 
    return; 
  end 
  if (uniqueInputRates(end) == Inf) 
     hasConstantInput = true; 
     uniqueInputRates = uniqueInputRates(1:end-1); 
  end 
  if (length(uniqueInputRates) ~= 1) 
    block.addError('The inputs to this block must run at a single rate.'); 
    return; 
  end 
  theInputRate = uniqueInputRates(1); 
  for i = 1:block.numSimulinkOutports 
     block.outport(i).setRate(theInputRate); 
  end 
  block.addClkCEPair(clkname,cename,theInputRate); 
  return; 

% ------------------------------------------------------------