source: ResearchApps/PHY/MIMO_OFDM/fec_decoder_simOnly_config.m

Last change on this file was 1733, checked in by murphpo, 12 years ago

Updated PHY model with two fec_decoder black boxes and sim mux to select between them for sim/implementation. Also added script for generating simulation-only verilog for fec_decoder. All this is workaround for MATLAB crashing during simulation due to a bug in isim/Sysgen 13.4 that's under investigation by Xilinx.

File size: 5.2 KB
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1
2function fec_decoder_simOnly_config(this_block)
3
4  % Revision History:
5  %
6  %   20-Apr-2012  (12:19 hours):
7  %     Original code was machine generated by Xilinx's System Generator after parsing
8  %     C:\work\PHY\MIMO_OFDM\sysgen13p4\fec_decoder_simOnly.v
9  %
10  %
11
12  this_block.setTopLevelLanguage('Verilog');
13
14  this_block.setEntityName('fec_decoder_simOnly');
15
16  % System Generator has to assume that your entity  has a combinational feed through;
17  %   if it  doesn't, then comment out the following line:
18  this_block.tagAsCombinational;
19
20  this_block.addSimulinkInport('nrst');
21  this_block.addSimulinkInport('fec_reg');
22  this_block.addSimulinkInport('start');
23  this_block.addSimulinkInport('vin');
24  this_block.addSimulinkInport('xk_index');
25  this_block.addSimulinkInport('mod_level');
26  this_block.addSimulinkInport('rx_i');
27  this_block.addSimulinkInport('rx_q');
28
29  this_block.addSimulinkOutport('rx_we');
30  this_block.addSimulinkOutport('rx_addr');
31  this_block.addSimulinkOutport('rx_data');
32  this_block.addSimulinkOutport('rx_done');
33  this_block.addSimulinkOutport('rx_we_2');
34  this_block.addSimulinkOutport('rx_addr_2');
35  this_block.addSimulinkOutport('rx_data_2');
36  this_block.addSimulinkOutport('rx_done_2');
37
38  rx_we_port = this_block.port('rx_we');
39  rx_we_port.setType('UFix_1_0');
40  rx_we_port.useHDLVector(false);
41  rx_addr_port = this_block.port('rx_addr');
42  rx_addr_port.setType('UFix_14_0');
43  rx_data_port = this_block.port('rx_data');
44  rx_data_port.setType('UFix_8_0');
45  rx_done_port = this_block.port('rx_done');
46  rx_done_port.setType('UFix_1_0');
47  rx_done_port.useHDLVector(false);
48  rx_we_2_port = this_block.port('rx_we_2');
49  rx_we_2_port.setType('UFix_1_0');
50  rx_we_2_port.useHDLVector(false);
51  rx_addr_2_port = this_block.port('rx_addr_2');
52  rx_addr_2_port.setType('UFix_14_0');
53  rx_data_2_port = this_block.port('rx_data_2');
54  rx_data_2_port.setType('UFix_8_0');
55  rx_done_2_port = this_block.port('rx_done_2');
56  rx_done_2_port.setType('UFix_1_0');
57  rx_done_2_port.useHDLVector(false);
58
59  % -----------------------------
60  if (this_block.inputTypesKnown)
61    % do input type checking, dynamic output type and generic setup in this code block.
62
63    if (this_block.port('nrst').width ~= 1);
64      this_block.setError('Input data type for port "nrst" must have width=1.');
65    end
66
67    this_block.port('nrst').useHDLVector(false);
68
69    if (this_block.port('fec_reg').width ~= 32);
70      this_block.setError('Input data type for port "fec_reg" must have width=32.');
71    end
72
73    if (this_block.port('start').width ~= 1);
74      this_block.setError('Input data type for port "start" must have width=1.');
75    end
76
77    this_block.port('start').useHDLVector(false);
78
79    if (this_block.port('vin').width ~= 1);
80      this_block.setError('Input data type for port "vin" must have width=1.');
81    end
82
83    this_block.port('vin').useHDLVector(false);
84
85    if (this_block.port('xk_index').width ~= 6);
86      this_block.setError('Input data type for port "xk_index" must have width=6.');
87    end
88
89    if (this_block.port('mod_level').width ~= 4);
90      this_block.setError('Input data type for port "mod_level" must have width=4.');
91    end
92
93    if (this_block.port('rx_i').width ~= 16);
94      this_block.setError('Input data type for port "rx_i" must have width=16.');
95    end
96
97    if (this_block.port('rx_q').width ~= 16);
98      this_block.setError('Input data type for port "rx_q" must have width=16.');
99    end
100
101  end  % if(inputTypesKnown)
102  % -----------------------------
103
104  % -----------------------------
105   if (this_block.inputRatesKnown)
106     setup_as_single_rate(this_block,'clk','ce')
107   end  % if(inputRatesKnown)
108  % -----------------------------
109
110    % (!) Set the inout port rate to be the same as the first input
111    %     rate. Change the following code if this is untrue.
112    uniqueInputRates = unique(this_block.getInputRates);
113
114
115  % Add addtional source files as needed.
116  %  |-------------
117  %  | Add files in the order in which they should be compiled.
118  %  | If two files "a.vhd" and "b.vhd" contain the entities
119  %  | entity_a and entity_b, and entity_a contains a
120  %  | component of type entity_b, the correct sequence of
121  %  | addFile() calls would be:
122  %  |    this_block.addFile('b.vhd');
123  %  |    this_block.addFile('a.vhd');
124  %  |-------------
125
126  %    this_block.addFile('');
127  %    this_block.addFile('');
128  this_block.addFile('fec_decoder_simOnly.v');
129%  this_block.addFile('fec_decoder_rest.v');
130return;
131
132
133% ------------------------------------------------------------
134
135function setup_as_single_rate(block,clkname,cename) 
136  inputRates = block.inputRates; 
137  uniqueInputRates = unique(inputRates); 
138  if (length(uniqueInputRates)==1 & uniqueInputRates(1)==Inf) 
139    block.addError('The inputs to this block cannot all be constant.'); 
140    return; 
141  end 
142  if (uniqueInputRates(end) == Inf) 
143     hasConstantInput = true; 
144     uniqueInputRates = uniqueInputRates(1:end-1); 
145  end 
146  if (length(uniqueInputRates) ~= 1) 
147    block.addError('The inputs to this block must run at a single rate.'); 
148    return; 
149  end 
150  theInputRate = uniqueInputRates(1); 
151  for i = 1:block.numSimulinkOutports
152     block.outport(i).setRate(theInputRate); 
153  end 
154  block.addClkCEPair(clkname,cename,theInputRate); 
155  return; 
156
157% ------------------------------------------------------------
158
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