[4196] | 1 | /** @file wl_baseband.h |
---|
| 2 | * @brief WARPLab Framework (Baseband) |
---|
| 3 | * |
---|
| 4 | * This contains the code for WARPLab Framework. |
---|
| 5 | * |
---|
| 6 | * @copyright Copyright 2013, Mango Communications. All rights reserved. |
---|
| 7 | * Distributed under the WARP license (http://warpproject.org/license) |
---|
| 8 | * |
---|
| 9 | * @author Chris Hunter (chunter [at] mangocomm.com) |
---|
| 10 | * @author Patrick Murphy (murphpo [at] mangocomm.com) |
---|
| 11 | * @author Erik Welsh (welsh [at] mangocomm.com) |
---|
| 12 | */ |
---|
[1995] | 13 | |
---|
[4453] | 14 | /**********************************************************************************************************************/ |
---|
| 15 | /** |
---|
| 16 | * @brief Common Functions (WARP v2 and WARP v3) |
---|
| 17 | * |
---|
| 18 | **********************************************************************************************************************/ |
---|
| 19 | |
---|
[4196] | 20 | /***************************** Include Files *********************************/ |
---|
| 21 | |
---|
| 22 | // Xilinx / Standard library includes |
---|
[1994] | 23 | #include <xparameters.h> |
---|
[1915] | 24 | |
---|
[4196] | 25 | // WARPLab includes |
---|
| 26 | #include "wl_common.h" |
---|
| 27 | |
---|
| 28 | |
---|
| 29 | /*************************** Constant Definitions ****************************/ |
---|
[1915] | 30 | #ifndef WL_BASEBAND_H_ |
---|
| 31 | #define WL_BASEBAND_H_ |
---|
| 32 | |
---|
[4196] | 33 | // ********************************************************************** |
---|
[4184] | 34 | // Command IDs (must match the CMD_ properties in wl_baseband_buffers.m) |
---|
[4196] | 35 | // |
---|
[4811] | 36 | #define CMDID_BASEBAND_TX_DELAY 0x000001 |
---|
| 37 | #define CMDID_BASEBAND_TX_LENGTH 0x000002 |
---|
| 38 | #define CMDID_BASEBAND_TX_MODE 0x000003 |
---|
| 39 | #define CMDID_BASEBAND_TX_BUFF_EN 0x000004 |
---|
| 40 | #define CMDID_BASEBAND_RX_BUFF_EN 0x000005 |
---|
| 41 | #define CMDID_BASEBAND_TXRX_BUFF_DIS 0x000006 |
---|
| 42 | #define CMDID_BASEBAND_TXRX_BUFF_STATE 0x000007 |
---|
| 43 | #define CMDID_BASEBAND_WRITE_IQ 0x000008 |
---|
| 44 | #define CMDID_BASEBAND_READ_IQ 0x000009 |
---|
| 45 | #define CMDID_BASEBAND_READ_RSSI 0x00000A |
---|
| 46 | #define CMDID_BASEBAND_RX_LENGTH 0x00000B |
---|
| 47 | #define CMDID_BASEBAND_WRITE_IQ_CHECKSUM 0x00000C |
---|
| 48 | #define CMDID_BASEBAND_MAX_NUM_SAMPLES 0x00000D |
---|
[2852] | 49 | |
---|
[4811] | 50 | #define CMDID_BASEBAND_TXRX_COUNT_RESET 0x000010 |
---|
| 51 | #define CMDID_BASEBAND_TXRX_COUNT_GET 0x000011 |
---|
[4184] | 52 | |
---|
[4811] | 53 | #define CMDID_BASEBAND_AGC_STATE 0x000100 |
---|
| 54 | #define CMDID_BASEBAND_AGC_DONE_ADDR 0x000101 |
---|
| 55 | #define CMDID_BASEBAND_AGC_RESET 0x000102 |
---|
| 56 | #define CMDID_BASEBAND_AGC_RESET_MODE 0x000103 |
---|
[1915] | 57 | |
---|
[4811] | 58 | #define CMDID_BASEBAND_AGC_TARGET 0x000110 |
---|
| 59 | #define CMDID_BASEBAND_AGC_DCO_EN_DIS 0x000111 |
---|
[4783] | 60 | |
---|
[4811] | 61 | #define CMDID_BASEBAND_AGC_CONFIG 0x000120 |
---|
| 62 | #define CMDID_BASEBAND_AGC_IIR_HPF 0x000121 |
---|
| 63 | #define CMDID_BASEBAND_AGC_RF_GAIN_THRESHOLD 0x000122 |
---|
| 64 | #define CMDID_BASEBAND_AGC_TIMING 0x000123 |
---|
| 65 | #define CMDID_BASEBAND_AGC_DCO_TIMING 0x000124 |
---|
[4783] | 66 | |
---|
| 67 | |
---|
[4331] | 68 | |
---|
[4811] | 69 | // #define CMDID_BASEBAND_DEBUG_TX_OUTPUT_CONFIGURE 0x000080 |
---|
[4331] | 70 | |
---|
[4811] | 71 | |
---|
[4196] | 72 | // ********************************************************************** |
---|
[4333] | 73 | // WARPLab Buffers core debug parameters |
---|
[4310] | 74 | // |
---|
[4321] | 75 | #define USE_GENERATED_RX_DATA 0 |
---|
[4333] | 76 | #define USE_TX_RX_LOOPBACK 0 |
---|
[4310] | 77 | |
---|
| 78 | |
---|
| 79 | // ********************************************************************** |
---|
[4196] | 80 | // Samples Constants |
---|
| 81 | // |
---|
| 82 | #define BYTES_PER_SAMP 4 |
---|
[1915] | 83 | |
---|
| 84 | |
---|
| 85 | |
---|
[4196] | 86 | // ********************************************************************** |
---|
| 87 | // Misc Constants |
---|
| 88 | // |
---|
| 89 | #define INIT_TX_DELAY 0 |
---|
[4284] | 90 | #define WL_BUF_DEBUG_4RF_ON_2RF 0 |
---|
[2162] | 91 | |
---|
| 92 | |
---|
[4284] | 93 | |
---|
[4196] | 94 | // ********************************************************************** |
---|
[4811] | 95 | // Command Parameter Constants |
---|
| 96 | // |
---|
| 97 | #define CMD_PARAM_BASEBAND_TXRX_COUNT_GET_TX 0 |
---|
| 98 | #define CMD_PARAM_BASEBAND_TXRX_COUNT_GET_RX 1 |
---|
| 99 | |
---|
| 100 | #define CMD_PARAM_BASEBAND_TXRX_COUNT_GET_COUNT_RSVD 0xFFFFFFFF |
---|
| 101 | |
---|
| 102 | |
---|
| 103 | |
---|
| 104 | |
---|
| 105 | // ********************************************************************** |
---|
[4453] | 106 | // Common memory defines for BRAM sample buffers |
---|
| 107 | // - ASSUME: all BRAM memories are the same size |
---|
[4284] | 108 | // |
---|
| 109 | #define WARPLAB_IQ_RX_BUF_SIZE WARPLAB_IQ_RX_BUF_A_SIZE |
---|
| 110 | #define WARPLAB_IQ_TX_BUF_SIZE WARPLAB_IQ_TX_BUF_A_SIZE |
---|
| 111 | #define WARPLAB_RSSI_BUF_SIZE WARPLAB_RSSI_BUF_A_SIZE |
---|
[2162] | 112 | |
---|
[4783] | 113 | #define WL_BUF_DEFAULT_RX_NUM_SAMPLES ((WARPLAB_IQ_RX_BUF_A_SIZE >> 2) - 1) |
---|
| 114 | #define WL_BUF_DEFAULT_TX_NUM_SAMPLES ((WARPLAB_IQ_TX_BUF_A_SIZE >> 2) - 1) |
---|
[2162] | 115 | |
---|
[4284] | 116 | |
---|
| 117 | |
---|
[4196] | 118 | // ********************************************************************** |
---|
| 119 | // Defines for WARPLab Buffers Core |
---|
| 120 | // - Renamed from XPAR* here for easier maintenance |
---|
| 121 | // |
---|
[2162] | 122 | |
---|
[4184] | 123 | // Buffers Register definitions |
---|
| 124 | #define WL_BUF_REG_DESIGN_VER XPAR_WARPLAB_BUFFERS_MEMMAP_DESIGN_VER |
---|
[4234] | 125 | #define WL_BUF_REG_BUF_SIZES XPAR_WARPLAB_BUFFERS_MEMMAP_BUFF_SIZES |
---|
[4184] | 126 | #define WL_BUF_REG_CONFIG XPAR_WARPLAB_BUFFERS_MEMMAP_CONFIG |
---|
| 127 | #define WL_BUF_REG_STATUS XPAR_WARPLAB_BUFFERS_MEMMAP_STATUS |
---|
[2162] | 128 | |
---|
[4234] | 129 | #define WL_BUF_REG_TX_DELAY XPAR_WARPLAB_BUFFERS_MEMMAP_TX_DELAY |
---|
| 130 | #define WL_BUF_REG_RX_LENGTH XPAR_WARPLAB_BUFFERS_MEMMAP_RX_LENGTH |
---|
| 131 | #define WL_BUF_REG_TX_LENGTH XPAR_WARPLAB_BUFFERS_MEMMAP_TX_LENGTH |
---|
[2162] | 132 | |
---|
[4184] | 133 | #define WL_BUF_REG_RF_BUFFER_SEL XPAR_WARPLAB_BUFFERS_MEMMAP_RF_BUFFER_SEL |
---|
[4234] | 134 | #define WL_BUF_REG_RX_BUF_EN XPAR_WARPLAB_BUFFERS_MEMMAP_RX_BUF_EN |
---|
| 135 | #define WL_BUF_REG_TX_BUF_EN XPAR_WARPLAB_BUFFERS_MEMMAP_TX_BUF_EN |
---|
[2162] | 136 | |
---|
[4234] | 137 | #define WL_BUF_REG_AGC_DONE_ADDR XPAR_WARPLAB_BUFFERS_MEMMAP_AGC_DONE_ADDR |
---|
| 138 | #define WL_BUF_REG_RF_AB_AGC_DONE_RSSI XPAR_WARPLAB_BUFFERS_MEMMAP_RFAB_AGC_DONE_RSSI |
---|
| 139 | #define WL_BUF_REG_RF_CD_AGC_DONE_RSSI XPAR_WARPLAB_BUFFERS_MEMMAP_RFCD_AGC_DONE_RSSI |
---|
[2162] | 140 | |
---|
[4184] | 141 | #define WL_BUF_REG_RF_RX_IQ_BUF_RD_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_RD_BYTE_OFFSET |
---|
| 142 | #define WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_WR_BYTE_OFFSET |
---|
| 143 | #define WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET_UPDATE XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_WR_BYTE_OFFSET_UPDATE |
---|
| 144 | #define WL_BUF_REG_RF_RX_IQ_THRESHOLD XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_THRESHOLD |
---|
| 145 | #define WL_BUF_REG_RF_RX_IQ_BUF_OCCUPANCY XPAR_WARPLAB_BUFFERS_MEMMAP_RF_RX_IQ_BUF_OCCUPANCY |
---|
[2162] | 146 | |
---|
[4234] | 147 | #define WL_BUF_REG_RF_TX_IQ_BUF_RD_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_BUF_RD_BYTE_OFFSET |
---|
| 148 | #define WL_BUF_REG_RF_TX_IQ_BUF_WR_BYTE_OFFSET XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_BUF_WR_BYTE_OFFSET |
---|
| 149 | #define WL_BUF_REG_RF_TX_IQ_THRESHOLD XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_THRESHOLD |
---|
| 150 | #define WL_BUF_REG_RF_TX_IQ_BUF_OCCUPANCY XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_BUF_OCCUPANCY |
---|
| 151 | #define WL_BUF_REG_RF_TX_IQ_STATUS XPAR_WARPLAB_BUFFERS_MEMMAP_RF_TX_IQ_STATUS |
---|
| 152 | |
---|
| 153 | #define WL_BUF_REG_RF_ERROR_CLR XPAR_WARPLAB_BUFFERS_MEMMAP_RF_ERROR_CLR |
---|
[4184] | 154 | #define WL_BUF_REG_INT_STATUS XPAR_WARPLAB_BUFFERS_MEMMAP_INT_STATUS |
---|
[2162] | 155 | |
---|
[4811] | 156 | #define WL_BUF_REG_TXRX_COUNTER_RESET XPAR_WARPLAB_BUFFERS_MEMMAP_TXRX_COUNTER_RESET |
---|
| 157 | |
---|
| 158 | #define WL_BUF_REG_RFA_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFA_TX_COUNTER |
---|
| 159 | #define WL_BUF_REG_RFB_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFB_TX_COUNTER |
---|
| 160 | #define WL_BUF_REG_RFC_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFC_TX_COUNTER |
---|
| 161 | #define WL_BUF_REG_RFD_TX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFD_TX_COUNTER |
---|
| 162 | #define WL_BUF_REG_RFA_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFA_RX_COUNTER |
---|
| 163 | #define WL_BUF_REG_RFB_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFB_RX_COUNTER |
---|
| 164 | #define WL_BUF_REG_RFC_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFC_RX_COUNTER |
---|
| 165 | #define WL_BUF_REG_RFD_RX_COUNTER XPAR_WARPLAB_BUFFERS_MEMMAP_RFD_RX_COUNTER |
---|
| 166 | |
---|
[4196] | 167 | #define WL_LOAD_TIMER_64_LSB XPAR_WARPLAB_BUFFERS_MEMMAP_LOAD_TIMER_64_LSB |
---|
| 168 | #define WL_LOAD_TIMER_64_MSB XPAR_WARPLAB_BUFFERS_MEMMAP_LOAD_TIMER_64_MSB |
---|
| 169 | #define WL_TIMER_64_LSB XPAR_WARPLAB_BUFFERS_MEMMAP_TIMER_64_LSB |
---|
| 170 | #define WL_TIMER_64_MSB XPAR_WARPLAB_BUFFERS_MEMMAP_TIMER_64_MSB |
---|
[2162] | 171 | |
---|
[4196] | 172 | |
---|
[4184] | 173 | // Masks for CONFIG register |
---|
| 174 | #define WL_BUF_REG_CONFIG_CONT_TX 0x00000001 |
---|
| 175 | #define WL_BUF_REG_CONFIG_STOP_TX 0x00000002 |
---|
[4684] | 176 | #define WL_BUF_REG_CONFIG_PROC_ALL_TRIGGERS 0x00000004 |
---|
[4184] | 177 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFA 0x00000010 |
---|
| 178 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFB 0x00000020 |
---|
| 179 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFC 0x00000040 |
---|
| 180 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RFD 0x00000080 |
---|
| 181 | #define WL_BUF_REG_CONFIG_RSSI_CLK_SEL 0x00000300 |
---|
[4234] | 182 | #define WL_BUF_REG_CONFIG_LOAD_TIMER_64 0x00001000 |
---|
[4184] | 183 | #define WL_BUF_REG_CONFIG_RX_WORD_ORDER 0x00010000 |
---|
| 184 | #define WL_BUF_REG_CONFIG_RX_BYTE_ORDER 0x00020000 |
---|
| 185 | #define WL_BUF_REG_CONFIG_TX_WORD_ORDER 0x00040000 |
---|
| 186 | #define WL_BUF_REG_CONFIG_TX_BYTE_ORDER 0x00080000 |
---|
| 187 | #define WL_BUF_REG_CONFIG_COUNTER_DATA_SEL 0x00100000 |
---|
[4333] | 188 | #define WL_BUF_REG_CONFIG_TX_RX_LOOPBACK_SEL 0x00200000 |
---|
[4234] | 189 | #define WL_BUF_REG_CONFIG_DEBUG_TX_OUTPUT_SEL 0x10000000 |
---|
[4328] | 190 | #define WL_BUF_REG_CONFIG_DEBUG_TX_BUF_SEL 0xE0000000 |
---|
[2162] | 191 | |
---|
[4234] | 192 | |
---|
[4184] | 193 | #define WL_BUF_REG_CONFIG_AGC_IQ_SEL_RF_ALL 0x000000F0 |
---|
[1915] | 194 | |
---|
[1994] | 195 | |
---|
[4184] | 196 | // Masks for Status register |
---|
[4684] | 197 | #define WL_BUF_REG_STATUS_TX_RUNNING 0x0000000F |
---|
| 198 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_A 0x00000001 |
---|
| 199 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_B 0x00000002 |
---|
| 200 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_C 0x00000004 |
---|
| 201 | #define WL_BUF_REG_STATUS_TX_RUNNING_RF_D 0x00000008 |
---|
| 202 | #define WL_BUF_REG_STATUS_RX_RUNNING 0x00000F00 |
---|
| 203 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_A 0x00000100 |
---|
| 204 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_B 0x00000200 |
---|
| 205 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_C 0x00000400 |
---|
| 206 | #define WL_BUF_REG_STATUS_RX_RUNNING_RF_D 0x00000800 |
---|
[4196] | 207 | #define WL_BUF_REG_STATUS_DRAM_INIT_DONE 0x00010000 |
---|
[2149] | 208 | |
---|
| 209 | |
---|
[4184] | 210 | // Mask for RF output selection register |
---|
| 211 | // NOTE: The defines for ANT_* in wl_interface.h should be used as values for the antenna arguments |
---|
| 212 | #define RFA_BUF_SEL 0x00000003 |
---|
| 213 | #define RFB_BUF_SEL 0x00000300 |
---|
| 214 | #define RFC_BUF_SEL 0x00030000 |
---|
| 215 | #define RFD_BUF_SEL 0x03000000 |
---|
[1994] | 216 | |
---|
| 217 | |
---|
[4184] | 218 | // Masks for RF enable registers |
---|
| 219 | #define RF_SEL_A 0x00000001 |
---|
| 220 | #define RF_SEL_B 0x00000002 |
---|
| 221 | #define RF_SEL_C 0x00000004 |
---|
| 222 | #define RF_SEL_D 0x00000008 |
---|
[1915] | 223 | |
---|
[4196] | 224 | #if WARPLAB_CONFIG_4RF |
---|
| 225 | #define NUM_RF_INF 4 |
---|
[4234] | 226 | #define RF_SEL_ALL 0x0000000F |
---|
| 227 | |
---|
[4196] | 228 | #else |
---|
| 229 | #define NUM_RF_INF 2 |
---|
[4234] | 230 | #define RF_SEL_ALL 0x00000003 |
---|
[4196] | 231 | #endif |
---|
[1994] | 232 | |
---|
[4684] | 233 | // Buffer state variables |
---|
| 234 | #define BUF_STATE_STANDBY 0 |
---|
| 235 | #define BUF_STATE_RX 1 |
---|
| 236 | #define BUF_STATE_TX 2 |
---|
[4196] | 237 | |
---|
[4184] | 238 | // Masks for interrupt status register |
---|
[4234] | 239 | #define WL_BUF_INT_ALL 0x00000003 |
---|
| 240 | #define RF_RX_IQ_RSSI_ERROR 0x01000000 |
---|
| 241 | #define RF_TX_IQ_ERROR 0x01000000 |
---|
[2162] | 242 | |
---|
[4234] | 243 | #define RF_RX_IQ_RSSI_ERROR_CLR 0x00000001 |
---|
| 244 | #define RF_TX_IQ_ERROR_CLR 0x00000100 |
---|
[2162] | 245 | |
---|
[4234] | 246 | |
---|
[4196] | 247 | // Masks for transfer calculations |
---|
[4284] | 248 | // Currently, these are defined as the BRAM size / 2 (ie we have a "ping" and "pong" buffer for storage) |
---|
[4668] | 249 | // |
---|
| 250 | // NOTE: We looked at |
---|
| 251 | // |
---|
| 252 | // |
---|
[4290] | 253 | #define WL_BUF_RX_TRANSFER_THRESHOLD_SAMPLES 0x00004000 |
---|
| 254 | #define WL_BUF_RX_TRANSFER_THRESHOLD_BYTES 0x00010000 |
---|
| 255 | #define WL_BUF_RX_TRANSFER_BYTE_ALIGNMENT_MASK 0xFFFF0000 |
---|
[2162] | 256 | |
---|
[4290] | 257 | #define WL_BUF_TX_TRANSFER_THRESHOLD_SAMPLES 0x00004000 |
---|
| 258 | #define WL_BUF_TX_TRANSFER_THRESHOLD_BYTES 0x00010000 |
---|
| 259 | #define WL_BUF_TX_TRANSFER_BYTE_ALIGNMENT_MASK 0xFFFF0000 |
---|
[4196] | 260 | |
---|
[4234] | 261 | |
---|
[4284] | 262 | // Masks for RX / TX sample length calculations |
---|
| 263 | // NOTE: This is based on the TX/RX_TRANSFER_THRESHOLD |
---|
[4668] | 264 | // |
---|
[4310] | 265 | #define WL_BUF_RX_SAMPLE_ALIGNMENT_MASK 0xFFFFC000 |
---|
| 266 | #define WL_BUF_TX_SAMPLE_ALIGNMENT_MASK 0xFFFFC000 |
---|
[4284] | 267 | |
---|
| 268 | |
---|
[4234] | 269 | // Defines for TX IQ status register |
---|
| 270 | #define WL_BUF_TX_IQ_STATUS_WR_DONE 0x00000001 |
---|
| 271 | |
---|
[4811] | 272 | // Defines for TX/RX counter reset |
---|
| 273 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFA 0x00000001 |
---|
| 274 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFB 0x00000002 |
---|
| 275 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFC 0x00000004 |
---|
| 276 | #define WL_BUF_TXRX_COUNTER_RESET_TX_RFD 0x00000008 |
---|
| 277 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFA 0x00000100 |
---|
| 278 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFB 0x00000200 |
---|
| 279 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFC 0x00000400 |
---|
| 280 | #define WL_BUF_TXRX_COUNTER_RESET_RX_RFD 0x00000800 |
---|
[4234] | 281 | |
---|
[4811] | 282 | #define WL_BUF_TXRX_COUNTER_RESET_TXRX_ALL 0x00000F0F |
---|
| 283 | |
---|
| 284 | |
---|
| 285 | |
---|
[4184] | 286 | // Baseband Macros |
---|
| 287 | #define wl_get_design_ver() XIo_In32(WL_BUF_REG_DESIGN_VER) |
---|
[2162] | 288 | |
---|
[4234] | 289 | #define wl_bb_get_buffer_sizes() XIo_In32(WL_BUF_REG_BUF_SIZES) |
---|
| 290 | #define wl_bb_get_rx_buffer_size() (XIo_In32(WL_BUF_REG_BUF_SIZES) & 0x0000FFFF) |
---|
| 291 | #define wl_bb_get_tx_buffer_size() ((XIo_In32(WL_BUF_REG_BUF_SIZES) & 0xFFFF0000) >> 16) |
---|
[4184] | 292 | |
---|
[4707] | 293 | #define wl_bb_get_raw_status() (XIo_In32(WL_BUF_REG_STATUS)) |
---|
[4184] | 294 | #define wl_bb_get_tx_status() (XIo_In32(WL_BUF_REG_STATUS) & WL_BUF_REG_STATUS_TX_RUNNING) |
---|
[4196] | 295 | #define wl_bb_get_rx_status() ((XIo_In32(WL_BUF_REG_STATUS) & WL_BUF_REG_STATUS_RX_RUNNING) >> 8) |
---|
[4184] | 296 | |
---|
| 297 | #define wl_bb_get_config() XIo_In32(WL_BUF_REG_CONFIG) |
---|
| 298 | #define wl_bb_set_config(mask) XIo_Out32(WL_BUF_REG_CONFIG, (XIo_In32(WL_BUF_REG_CONFIG) | (mask))) |
---|
| 299 | #define wl_bb_clear_config(mask) XIo_Out32(WL_BUF_REG_CONFIG, (XIo_In32(WL_BUF_REG_CONFIG) & ~(mask))) |
---|
| 300 | |
---|
| 301 | #define wl_bb_set_rssi_clk(value) XIo_Out32(WL_BUF_REG_CONFIG, ((XIo_In32(WL_BUF_REG_CONFIG) & ~WL_BUF_REG_CONFIG_RSSI_CLK_SEL) | ((value << 8) & WL_BUF_REG_CONFIG_RSSI_CLK_SEL))) |
---|
| 302 | |
---|
| 303 | #define wl_bb_get_tx_delay() XIo_In32(WL_BUF_REG_TX_DELAY) |
---|
| 304 | #define wl_bb_set_tx_delay(delay) XIo_Out32(WL_BUF_REG_TX_DELAY, delay) |
---|
| 305 | |
---|
| 306 | #define wl_bb_get_rx_length() XIo_In32(WL_BUF_REG_RX_LENGTH) |
---|
| 307 | #define wl_bb_set_rx_length(length) XIo_Out32(WL_BUF_REG_RX_LENGTH, length) |
---|
| 308 | |
---|
| 309 | #define wl_bb_get_tx_length() XIo_In32(WL_BUF_REG_TX_LENGTH) |
---|
| 310 | #define wl_bb_set_tx_length(length) XIo_Out32(WL_BUF_REG_TX_LENGTH, length) |
---|
| 311 | |
---|
| 312 | #define wl_bb_get_rf_buffer_sel() XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) |
---|
[4234] | 313 | #define wl_bb_set_rf_buffer_sel_rfa(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFA_BUF_SEL) | ((ant ) & RFA_BUF_SEL))) |
---|
[4184] | 314 | #define wl_bb_set_rf_buffer_sel_rfb(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFB_BUF_SEL) | ((ant << 8) & RFB_BUF_SEL))) |
---|
| 315 | #define wl_bb_set_rf_buffer_sel_rfc(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFC_BUF_SEL) | ((ant << 16) & RFC_BUF_SEL))) |
---|
| 316 | #define wl_bb_set_rf_buffer_sel_rfd(ant) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, ((XIo_In32(WL_BUF_REG_RF_BUFFER_SEL) & ~RFD_BUF_SEL) | ((ant << 24) & RFD_BUF_SEL))) |
---|
[4234] | 317 | #define wl_bb_set_rf_buffer_sel(rfa, rfb, rfc, rfd) XIo_Out32(WL_BUF_REG_RF_BUFFER_SEL, (((rfa) & RFA_BUF_SEL) | ((rfb << 8) & RFB_BUF_SEL) | ((rfc << 16) & RFC_BUF_SEL) | ((rfd << 24) & RFD_BUF_SEL))) |
---|
[4184] | 318 | |
---|
[4234] | 319 | #define wl_bb_get_rx_buffer_en() XIo_In32(WL_BUF_REG_RX_BUF_EN) |
---|
[4684] | 320 | #define wl_bb_set_rx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_RX_BUF_EN, (XIo_In32(WL_BUF_REG_RX_BUF_EN) | rf_sel)) |
---|
[4234] | 321 | #define wl_bb_clear_rx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_RX_BUF_EN, (XIo_In32(WL_BUF_REG_RX_BUF_EN) & ~(rf_sel))) |
---|
[4184] | 322 | |
---|
[4234] | 323 | #define wl_bb_get_tx_buffer_en() XIo_In32(WL_BUF_REG_TX_BUF_EN) |
---|
[4684] | 324 | #define wl_bb_set_tx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_TX_BUF_EN, (XIo_In32(WL_BUF_REG_TX_BUF_EN) | rf_sel)) |
---|
[4234] | 325 | #define wl_bb_clear_tx_buffer_en(rf_sel) XIo_Out32(WL_BUF_REG_TX_BUF_EN, (XIo_In32(WL_BUF_REG_TX_BUF_EN) & ~(rf_sel))) |
---|
[4184] | 326 | |
---|
| 327 | #define wl_bb_get_agc_done_addr() XIo_In32(WL_BUF_REG_AGC_DONE_ADDR) |
---|
| 328 | #define wl_bb_get_rfa_agc_done_rssi() (XIo_In32(WL_BUF_REG_RF_AB_AGC_DONE_RSSI) & 0x000003FF) |
---|
| 329 | #define wl_bb_get_rfb_agc_done_rssi() ((XIo_In32(WL_BUF_REG_RF_AB_AGC_DONE_RSSI) & 0x03FF0000) >> 16) |
---|
| 330 | #define wl_bb_get_rfc_agc_done_rssi() (XIo_In32(WL_BUF_REG_RF_CD_AGC_DONE_RSSI) & 0x000003FF) |
---|
| 331 | #define wl_bb_get_rfd_agc_done_rssi() ((XIo_In32(WL_BUF_REG_RF_CD_AGC_DONE_RSSI) & 0x03FF0000) >> 16) |
---|
| 332 | |
---|
| 333 | #define wl_bb_get_rf_rx_iq_buf_rd_byte_offset() XIo_In32(WL_BUF_REG_RF_RX_IQ_BUF_RD_BYTE_OFFSET) |
---|
| 334 | #define wl_bb_set_rf_rx_iq_buf_rd_byte_offset(offset) XIo_Out32(WL_BUF_REG_RF_RX_IQ_BUF_RD_BYTE_OFFSET, offset) |
---|
| 335 | |
---|
| 336 | #define wl_bb_get_rf_rx_iq_buf_wr_byte_offset() XIo_In32(WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET_UPDATE) |
---|
| 337 | #define wl_bb_set_rf_rx_iq_buf_wr_byte_offset(offset) XIo_Out32(WL_BUF_REG_RF_RX_IQ_BUF_WR_BYTE_OFFSET, offset) |
---|
| 338 | |
---|
| 339 | #define wl_bb_get_rf_rx_iq_threshold() XIo_In32(WL_BUF_REG_RF_RX_IQ_THRESHOLD) |
---|
| 340 | #define wl_bb_set_rf_rx_iq_threshold(num_samples) XIo_Out32(WL_BUF_REG_RF_RX_IQ_THRESHOLD, num_samples) |
---|
| 341 | |
---|
| 342 | #define wl_bb_get_rf_rx_iq_buf_occupancy() XIo_In32(WL_BUF_REG_RF_RX_IQ_BUF_OCCUPANCY) |
---|
| 343 | |
---|
[4234] | 344 | #define wl_bb_get_rf_tx_iq_buf_rd_byte_offset() XIo_In32(WL_BUF_REG_RF_TX_IQ_BUF_RD_BYTE_OFFSET) |
---|
[4184] | 345 | |
---|
[4234] | 346 | #define wl_bb_get_rf_tx_iq_buf_wr_byte_offset() XIo_In32(WL_BUF_REG_RF_TX_IQ_BUF_WR_BYTE_OFFSET) |
---|
| 347 | #define wl_bb_set_rf_tx_iq_buf_wr_byte_offset(offset) XIo_Out32(WL_BUF_REG_RF_TX_IQ_BUF_WR_BYTE_OFFSET, offset) |
---|
| 348 | |
---|
| 349 | #define wl_bb_get_rf_tx_iq_threshold() XIo_In32(WL_BUF_REG_RF_TX_IQ_THRESHOLD) |
---|
| 350 | #define wl_bb_set_rf_tx_iq_threshold(num_samples) XIo_Out32(WL_BUF_REG_RF_TX_IQ_THRESHOLD, num_samples) |
---|
| 351 | |
---|
| 352 | #define wl_bb_get_rf_tx_iq_buf_occupancy() XIo_In32(WL_BUF_REG_RF_TX_IQ_BUF_OCCUPANCY) |
---|
| 353 | #define wl_bb_get_rf_tx_iq_status() XIo_In32(WL_BUF_REG_RF_TX_IQ_STATUS) |
---|
| 354 | |
---|
| 355 | #define wl_bb_get_rf_rx_iq_rssi_error() ((XIo_In32(WL_BUF_REG_INT_STATUS) & RF_RX_IQ_RSSI_ERROR) >> 24) |
---|
| 356 | #define wl_bb_clear_rf_rx_iq_rssi_error() XIo_Out32(WL_BUF_REG_RF_ERROR_CLR, RF_RX_IQ_RSSI_ERROR_CLR) |
---|
| 357 | |
---|
| 358 | #define wl_bb_get_rf_tx_iq_error() ((XIo_In32(WL_BUF_REG_INT_STATUS) & RF_TX_IQ_ERROR) >> 25) |
---|
| 359 | #define wl_bb_clear_rf_tx_iq_error() XIo_Out32(WL_BUF_REG_RF_ERROR_CLR, RF_TX_IQ_ERROR_CLR) |
---|
| 360 | |
---|
[4184] | 361 | #define wl_bb_get_int_status() (XIo_In32(WL_BUF_REG_INT_STATUS) & WL_BUF_INT_ALL) |
---|
| 362 | |
---|
[4811] | 363 | #define wl_bb_get_rfa_tx_count() XIo_In32(WL_BUF_REG_RFA_TX_COUNTER) |
---|
| 364 | #define wl_bb_get_rfb_tx_count() XIo_In32(WL_BUF_REG_RFB_TX_COUNTER) |
---|
| 365 | #define wl_bb_get_rfc_tx_count() XIo_In32(WL_BUF_REG_RFC_TX_COUNTER) |
---|
| 366 | #define wl_bb_get_rfd_tx_count() XIo_In32(WL_BUF_REG_RFD_TX_COUNTER) |
---|
| 367 | #define wl_bb_get_rfa_rx_count() XIo_In32(WL_BUF_REG_RFA_RX_COUNTER) |
---|
| 368 | #define wl_bb_get_rfb_rx_count() XIo_In32(WL_BUF_REG_RFB_RX_COUNTER) |
---|
| 369 | #define wl_bb_get_rfc_rx_count() XIo_In32(WL_BUF_REG_RFC_RX_COUNTER) |
---|
| 370 | #define wl_bb_get_rfd_rx_count() XIo_In32(WL_BUF_REG_RFD_RX_COUNTER) |
---|
[4184] | 371 | |
---|
[4811] | 372 | #define wl_bb_set_txrx_counter_reset(rf) XIo_Out32(WL_BUF_REG_TXRX_COUNTER_RESET, (rf & WL_BUF_TXRX_COUNTER_RESET_TXRX_ALL)) |
---|
| 373 | #define wl_bb_clear_txrx_counter_reset() XIo_Out32(WL_BUF_REG_TXRX_COUNTER_RESET, 0) |
---|
| 374 | |
---|
| 375 | |
---|
| 376 | |
---|
[4196] | 377 | // Macros for other values from the buffers core |
---|
| 378 | #define wl_get_dram_init_done() ((XIo_In32(WL_BUF_REG_STATUS) & WL_BUF_REG_STATUS_DRAM_INIT_DONE) >> 16) |
---|
| 379 | |
---|
| 380 | #define wl_get_timer_64_MSB() XIo_In32(WL_TIMER_64_MSB) |
---|
| 381 | #define wl_get_timer_64_LSB() XIo_In32(WL_TIMER_64_LSB) |
---|
| 382 | |
---|
| 383 | |
---|
| 384 | |
---|
[4783] | 385 | // **************************************************************************** |
---|
| 386 | // AGC Defines |
---|
| 387 | // |
---|
| 388 | #define AGC_A 0x10000000 |
---|
| 389 | #define AGC_B 0x20000000 |
---|
| 390 | #define AGC_C 0x40000000 |
---|
| 391 | #define AGC_D 0x80000000 |
---|
[4196] | 392 | |
---|
[4783] | 393 | |
---|
| 394 | // AGC Register definitions |
---|
| 395 | #define WL_AGC_REG_RESET XPAR_WARPLAB_AGC_MEMMAP_RESET |
---|
| 396 | #define WL_AGC_REG_TIMING_AGC XPAR_WARPLAB_AGC_MEMMAP_TIMING_AGC |
---|
| 397 | #define WL_AGC_REG_TIMING_DCO XPAR_WARPLAB_AGC_MEMMAP_TIMING_DCO |
---|
| 398 | #define WL_AGC_REG_TARGET XPAR_WARPLAB_AGC_MEMMAP_TARGET |
---|
| 399 | #define WL_AGC_REG_CONFIG XPAR_WARPLAB_AGC_MEMMAP_CONFIG |
---|
| 400 | #define WL_AGC_REG_RSSI_PWR_CALIB XPAR_WARPLAB_AGC_MEMMAP_RSSI_PWR_CALIB |
---|
| 401 | #define WL_AGC_REG_IIR_COEF_B0 XPAR_WARPLAB_AGC_MEMMAP_IIR_COEF_B0 |
---|
| 402 | #define WL_AGC_REG_IIR_COEF_A1 XPAR_WARPLAB_AGC_MEMMAP_IIR_COEF_A1 |
---|
| 403 | #define WL_AGC_TIMING_RESET XPAR_WARPLAB_AGC_MEMMAP_TIMING_RESET |
---|
| 404 | #define WL_AGC_SW_RESET XPAR_WARPLAB_AGC_MEMMAP_SW_RESET |
---|
[4805] | 405 | #define WL_AGC_RESET_MODE XPAR_WARPLAB_AGC_MEMMAP_RESET_MODE |
---|
| 406 | #define WL_AGC_RX_LENGTH XPAR_WARPLAB_AGC_MEMMAP_RX_LENGTH |
---|
[4783] | 407 | #define WL_AGC_OVERRIDE XPAR_WARPLAB_AGC_MEMMAP_AGC_OVERRIDE |
---|
| 408 | |
---|
| 409 | #define WL_AGC_GAINS XPAR_WARPLAB_BUFFERS_MEMMAP_AGC_GAINS |
---|
| 410 | |
---|
| 411 | |
---|
[4805] | 412 | #define WL_AGC_RESET_MODE_RESET_PER_RX_MASK 0x00000001 |
---|
[4783] | 413 | |
---|
[4805] | 414 | #define WL_AGC_RX_LENGTH_VALUE_MASK 0xFFFFFFFF |
---|
[4783] | 415 | |
---|
| 416 | |
---|
| 417 | // AGC gains reg: |
---|
| 418 | // [ 4: 0]: RF A BBG |
---|
| 419 | // [ 6: 5]: RF A RFG |
---|
| 420 | // [7]: RF A RXHP |
---|
| 421 | // [12: 8]: RF B BBG |
---|
| 422 | // [14:13]: RF B RFG |
---|
| 423 | // [15]: RF B RXHP |
---|
| 424 | // [20:16]: RF C BBG |
---|
| 425 | // [22:21]: RF C RFG |
---|
| 426 | // [23]: RF C RXHP |
---|
| 427 | // [28:24]: RF D BBG |
---|
| 428 | // [30:29]: RF D RFG |
---|
| 429 | // [31]: RF D RXHP |
---|
| 430 | // |
---|
| 431 | #define wl_get_agc_gains_raw() XIo_In32(WL_AGC_GAINS) |
---|
| 432 | |
---|
| 433 | #define wl_get_agc_RFG(ant) (((ant==0) ? (Xil_In32(WL_AGC_GAINS) >> 5) : \ |
---|
| 434 | (ant==1) ? (Xil_In32(WL_AGC_GAINS) >> 13) : \ |
---|
| 435 | (ant==2) ? (Xil_In32(WL_AGC_GAINS) >> 21) : \ |
---|
| 436 | (Xil_In32(WL_AGC_GAINS) >> 29)) & 0x3) |
---|
| 437 | |
---|
| 438 | #define wl_get_agc_BBG(ant) (((ant==0) ? (Xil_In32(WL_AGC_GAINS) >> 0) : \ |
---|
| 439 | (ant==1) ? (Xil_In32(WL_AGC_GAINS) >> 8) : \ |
---|
| 440 | (ant==2) ? (Xil_In32(WL_AGC_GAINS) >> 16) : \ |
---|
| 441 | (Xil_In32(WL_AGC_GAINS) >> 24)) & 0x1F) |
---|
| 442 | |
---|
| 443 | #define wl_get_agc_RXHP(ant) (((ant==0) ? (Xil_In32(WL_AGC_GAINS) >> 7) : \ |
---|
| 444 | (ant==1) ? (Xil_In32(WL_AGC_GAINS) >> 15) : \ |
---|
| 445 | (ant==2) ? (Xil_In32(WL_AGC_GAINS) >> 23) : \ |
---|
| 446 | (Xil_In32(WL_AGC_GAINS) >> 31)) & 0x1) |
---|
| 447 | |
---|
| 448 | |
---|
| 449 | // AGC Macros |
---|
| 450 | #define wl_agc_get_reset() XIo_In32(WL_AGC_REG_RESET) |
---|
| 451 | #define wl_agc_set_reset(data) XIo_Out32(WL_AGC_REG_RESET, (data & 0x1)) |
---|
| 452 | |
---|
| 453 | #define wl_agc_get_AGC_timing() XIo_In32(WL_AGC_REG_TIMING_AGC) |
---|
| 454 | #define wl_agc_set_AGC_timing(capt_rssi_1, capt_rssi_2, capt_v_db, agc_done) \ |
---|
| 455 | Xil_Out32(WL_AGC_REG_TIMING_AGC, ((capt_rssi_1 & 0xFF) | ((capt_rssi_2 & 0xFF) << 8) | \ |
---|
| 456 | ((capt_v_db & 0xFF) << 16) | ((agc_done & 0xFF) << 24))) |
---|
| 457 | |
---|
| 458 | #define wl_agc_get_DCO_timing() XIo_In32(WL_AGC_REG_TIMING_DCO) |
---|
| 459 | #define wl_agc_set_DCO_timing(start_dco, en_iir_filt) \ |
---|
| 460 | Xil_Out32(WL_AGC_REG_TIMING_DCO, ((start_dco & 0xFF) | ((en_iir_filt & 0xFF) << 8))) |
---|
| 461 | |
---|
| 462 | #define wl_agc_get_target() XIo_In32(WL_AGC_REG_TARGET) |
---|
| 463 | #define wl_agc_set_target(target_pwr) Xil_Out32(WL_AGC_REG_TARGET, (target_pwr & 0x3F)) |
---|
| 464 | |
---|
| 465 | #define wl_agc_get_config() XIo_In32(WL_AGC_REG_CONFIG) |
---|
| 466 | #define wl_agc_set_config_all(thresh32, thresh21, avg_len, v_db_adj, init_g_bb) \ |
---|
| 467 | Xil_Out32(WL_AGC_REG_CONFIG, (((thresh32 & 0xFF) << 0) | \ |
---|
| 468 | ((thresh21 & 0xFF) << 8) | \ |
---|
| 469 | ((avg_len & 0x03) << 16) | \ |
---|
| 470 | ((v_db_adj & 0x3F) << 18) | \ |
---|
| 471 | ((init_g_bb & 0x1F) << 24))) |
---|
| 472 | |
---|
| 473 | #define wl_agc_set_config(avg_len, v_db_adj, init_g_bb) \ |
---|
| 474 | Xil_Out32(WL_AGC_REG_CONFIG, ((XIo_In32(WL_AGC_REG_CONFIG) & 0x0000FFFF) | \ |
---|
| 475 | ((avg_len & 0x03) << 16) | \ |
---|
| 476 | ((v_db_adj & 0x3F) << 18) | \ |
---|
| 477 | ((init_g_bb & 0x1F) << 24))) |
---|
| 478 | |
---|
| 479 | #define wl_agc_set_config_thresh(thresh32, thresh21) \ |
---|
| 480 | Xil_Out32(WL_AGC_REG_CONFIG, ((XIo_In32(WL_AGC_REG_CONFIG) & 0xFFFF0000) | \ |
---|
| 481 | ((thresh32 & 0xFF) << 0) | \ |
---|
| 482 | ((thresh21 & 0xFF) << 8))) |
---|
| 483 | |
---|
| 484 | #define wl_agc_get_RSSI_pwr_calib() XIo_In32(WL_AGC_REG_RSSI_PWR_CALIB) |
---|
| 485 | #define wl_agc_set_RSSI_pwr_calib(g3, g2, g1) Xil_Out32(WL_AGC_REG_RSSI_PWR_CALIB, ((g3 & 0xFF) | ((g2 & 0xFF)<<8) | ((g1 & 0xFF)<<16))) |
---|
| 486 | |
---|
| 487 | #define wl_agc_get_reset_timing() XIo_In32(WL_AGC_TIMING_RESET) |
---|
| 488 | #define wl_agc_set_reset_timing(rxhp, g_rf, g_bb) Xil_Out32(WL_AGC_TIMING_RESET, ((rxhp & 0xFF) | ((g_rf & 0xFF)<<8) | ( (g_bb & 0xFF)<<16))) |
---|
| 489 | |
---|
[4805] | 490 | #define wl_agc_get_rx_length() XIo_In32(WL_AGC_RX_LENGTH) |
---|
| 491 | #define wl_agc_set_rx_length(data) XIo_Out32(WL_AGC_RX_LENGTH, data) |
---|
[4783] | 492 | |
---|
[4805] | 493 | #define wl_agc_get_reset_mode() XIo_In32(WL_AGC_RESET_MODE) |
---|
| 494 | #define wl_agc_enable_reset_per_rx() XIo_Out32(WL_AGC_RESET_MODE, (XIo_In32(WL_AGC_RESET_MODE) | WL_AGC_RESET_MODE_RESET_PER_RX_MASK)) |
---|
| 495 | #define wl_agc_disable_reset_per_rx() XIo_Out32(WL_AGC_RESET_MODE, (XIo_In32(WL_AGC_RESET_MODE) & ~WL_AGC_RESET_MODE_RESET_PER_RX_MASK)) |
---|
| 496 | |
---|
[4783] | 497 | #define wl_agc_get_override() XIo_In32(WL_AGC_OVERRIDE) |
---|
| 498 | #define wl_agc_set_override(data) Xil_Out32(WL_AGC_OVERRIDE, data) |
---|
| 499 | |
---|
| 500 | #define wl_agc_get_iir_coef_a1() XIo_In32(WL_AGC_REG_IIR_COEF_A1) |
---|
| 501 | #define wl_agc_set_iir_coef_a1(data) Xil_Out32(WL_AGC_REG_IIR_COEF_A1, data) |
---|
| 502 | |
---|
| 503 | #define wl_agc_get_iir_coef_b0() XIo_In32(WL_AGC_REG_IIR_COEF_B0) |
---|
| 504 | #define wl_agc_set_iir_coef_b0(data) Xil_Out32(WL_AGC_REG_IIR_COEF_B0, data) |
---|
| 505 | |
---|
| 506 | |
---|
| 507 | |
---|
[4196] | 508 | /*********************** Global Structure Definitions ************************/ |
---|
| 509 | |
---|
| 510 | typedef u32 wl_samp; |
---|
| 511 | |
---|
[4284] | 512 | // Common sample header flags between Read IQ / Write IQ |
---|
| 513 | #define SAMPLE_HDR_FLAG_IQ_ERROR 0x01 |
---|
| 514 | #define SAMPLE_HDR_FLAG_IQ_NOT_READY 0x02 |
---|
[4196] | 515 | |
---|
[4284] | 516 | |
---|
| 517 | // Write IQ sample header flags |
---|
[4783] | 518 | #define SAMPLE_HDR_FLAG_CHKSUM_RESET 0x10 |
---|
[4284] | 519 | #define SAMPLE_HDR_FLAG_LAST_WRITE 0x20 |
---|
| 520 | |
---|
| 521 | |
---|
| 522 | // Sample header |
---|
[4196] | 523 | typedef struct{ |
---|
[4783] | 524 | u16 buff_sel; |
---|
| 525 | u8 flags; |
---|
| 526 | u8 sample_iq_id; |
---|
| 527 | u32 start_samp; |
---|
| 528 | u32 num_samp; |
---|
[4284] | 529 | } wl_bb_samp_hdr; |
---|
[4196] | 530 | |
---|
| 531 | |
---|
| 532 | |
---|
| 533 | |
---|
[4184] | 534 | /******************************** Functions **********************************/ |
---|
| 535 | |
---|
[4196] | 536 | int baseband_init(u8 dram_present, u8 configure_buffers); |
---|
[4514] | 537 | int baseband_process_cmd(int socket_index, void * from, wl_cmd_resp * command, wl_cmd_resp * response); |
---|
[4284] | 538 | |
---|
| 539 | u32 wl_bb_get_supported_tx_length(); |
---|
| 540 | u32 wl_bb_get_supported_rx_length(); |
---|
| 541 | |
---|
[4453] | 542 | u32 baseband_get_checksum(); |
---|
| 543 | u32 baseband_update_checksum(u16 newdata, u8 reset ); |
---|
[1915] | 544 | |
---|
[4453] | 545 | // AGC Functions |
---|
[2162] | 546 | void warplab_agc_init(); |
---|
[4783] | 547 | void warplab_agc_enable_DCO(u32 enable); |
---|
[2162] | 548 | void warplab_agc_reset(); |
---|
| 549 | inline void warplab_agc_setNoiseEstimate(short int noiseEst); |
---|
[4805] | 550 | void warplab_set_agc_rx_length(u32 num_samples); |
---|
[1915] | 551 | |
---|
[4453] | 552 | |
---|
| 553 | |
---|
| 554 | /**********************************************************************************************************************/ |
---|
| 555 | /** |
---|
| 556 | * @brief WARP v3 Specific Functions |
---|
| 557 | * |
---|
| 558 | **********************************************************************************************************************/ |
---|
| 559 | |
---|
| 560 | #ifdef WARP_HW_VER_v3 |
---|
| 561 | |
---|
| 562 | /***************************** Include Files *********************************/ |
---|
| 563 | #include <xintc.h> |
---|
| 564 | |
---|
| 565 | /*************************** Constant Definitions ****************************/ |
---|
| 566 | |
---|
| 567 | // ********************************************************************** |
---|
| 568 | // Memory defines for DDR sample buffers |
---|
| 569 | // |
---|
| 570 | // Currently, the RX buffer must be 8x the size of the RSSI buffer. In order to |
---|
| 571 | // minimize the unused space, we are allocating the buffers in the ratio: |
---|
| 572 | // |
---|
| 573 | // 2RF / 4RF (2GB DDR) |
---|
| 574 | // RX - 8x --> 512 / 256 MB |
---|
| 575 | // TX - 7x --> 448 / 224 MB |
---|
| 576 | // RSSI - 1x --> 64 / 32 MB |
---|
| 577 | // |
---|
| 578 | // NOTE: Buffers must be allocated on temporary buffer size boundaries (ie WARPLAB_IQ_TX_BUF_SIZE) |
---|
| 579 | // NOTE: These values will not be use if DRAM is not available. Instead, the buffers will default |
---|
| 580 | // back to WARPLab 7.4.0 sizes |
---|
| 581 | // |
---|
| 582 | |
---|
| 583 | #if 1 |
---|
| 584 | |
---|
| 585 | // To make it easier to define the buffers, we should allocate the space for the buffers in chunks |
---|
| 586 | // For 4 RF interfaces: 32 MB / increment (ie 2^23 samples) |
---|
| 587 | // For 2 RF interfaces: 64 MB / increment (ie 2^24 samples) |
---|
| 588 | // |
---|
| 589 | #if WARPLAB_CONFIG_4RF |
---|
| 590 | #define WL_BUF_DEFAULT_CHUNK_SIZE (DDR_SIZE / 64) |
---|
| 591 | #else |
---|
| 592 | #define WL_BUF_DEFAULT_CHUNK_SIZE (DDR_SIZE / 32) |
---|
| 593 | #endif |
---|
| 594 | |
---|
| 595 | // Define the maximum number of sample supported base on the "chunk" size |
---|
| 596 | #define WL_BUF_DEFAULT_RX_MAX_SAMPLES (((8 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
---|
| 597 | #define WL_BUF_DEFAULT_TX_MAX_SAMPLES (((7 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
---|
| 598 | |
---|
| 599 | // Define RF A Buffer addresses / sizes |
---|
| 600 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR (DRAM_BASEADDR + ( 0 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 601 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR (DRAM_BASEADDR + ( 8 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 602 | #define WL_BUF_DEFAULT_RSSI_BUF_A_ADDR (DRAM_BASEADDR + (15 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 603 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 604 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 605 | #define WL_BUF_DEFAULT_RSSI_BUF_A_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 606 | |
---|
| 607 | // Define RF B Buffer addresses / sizes |
---|
| 608 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_ADDR (DRAM_BASEADDR + (16 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 609 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_ADDR (DRAM_BASEADDR + (24 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 610 | #define WL_BUF_DEFAULT_RSSI_BUF_B_ADDR (DRAM_BASEADDR + (31 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 611 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 612 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 613 | #define WL_BUF_DEFAULT_RSSI_BUF_B_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 614 | |
---|
| 615 | #if WARPLAB_CONFIG_4RF |
---|
[4783] | 616 | // Define RF C Buffer addresses / sizes |
---|
| 617 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR (DRAM_BASEADDR + (32 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 618 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR (DRAM_BASEADDR + (40 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 619 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR (DRAM_BASEADDR + (47 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 620 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 621 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 622 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
[4453] | 623 | |
---|
[4783] | 624 | // Define RF D Buffer addresses / sizes |
---|
| 625 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR (DRAM_BASEADDR + (48 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 626 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR (DRAM_BASEADDR + (56 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 627 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR (DRAM_BASEADDR + (63 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 628 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 629 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 630 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
[4453] | 631 | #else |
---|
[4783] | 632 | #if WL_BUF_DEBUG_4RF_ON_2RF |
---|
| 633 | // In the case we want to debug the 4RF buffers on a 2RF design, |
---|
| 634 | // map RFC -> RFA and RFD -> RFB |
---|
[4453] | 635 | |
---|
[4783] | 636 | // Define RF C Buffer addresses / sizes |
---|
| 637 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR (DRAM_BASEADDR + ( 0 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 638 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR (DRAM_BASEADDR + ( 8 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 639 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR (DRAM_BASEADDR + (15 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 640 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 641 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 642 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
[4453] | 643 | |
---|
[4783] | 644 | // Define RF D Buffer addresses / sizes |
---|
| 645 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR (DRAM_BASEADDR + (16 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 646 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR (DRAM_BASEADDR + (24 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 647 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR (DRAM_BASEADDR + (31 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 648 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 649 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 650 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 651 | #else |
---|
| 652 | // Define RF C Buffer addresses / sizes |
---|
| 653 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR 0 |
---|
| 654 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR 0 |
---|
| 655 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR 0 |
---|
| 656 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE 0 |
---|
| 657 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE 0 |
---|
| 658 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE 0 |
---|
[4453] | 659 | |
---|
[4783] | 660 | // Define RF D Buffer addresses / sizes |
---|
| 661 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR 0 |
---|
| 662 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR 0 |
---|
| 663 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR 0 |
---|
| 664 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE 0 |
---|
| 665 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE 0 |
---|
| 666 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE 0 |
---|
| 667 | #endif |
---|
[4453] | 668 | #endif |
---|
| 669 | |
---|
| 670 | #endif // #if 1 |
---|
| 671 | |
---|
| 672 | |
---|
| 673 | // ********************************************************************** |
---|
| 674 | // Alternate Example Memory defines for DDR sample buffers |
---|
| 675 | // |
---|
| 676 | // Currently, the RX buffer must be 8x the size of the RSSI buffer. In order to |
---|
| 677 | // minimize the unused space, we are allocating the buffers in the ratio: |
---|
| 678 | // |
---|
| 679 | // (2GB DDR) Max Tx / Max RX / 1RF / 2RF / 4RF |
---|
| 680 | // RX - 8x --> 128 kB / 1820 MB / 1024 MB / 512 MB / 256 MB |
---|
| 681 | // TX - 7x --> 2048 MB / 128 kB / 896 MB / 448 MB / 224 MB |
---|
| 682 | // RSSI - 1x --> 16 kB / 228 MB / 128 MB / 64 MB / 32 MB |
---|
| 683 | // |
---|
| 684 | // NOTE: Buffers must be allocated on temporary buffer size boundaries (ie WARPLAB_IQ_TX_BUF_SIZE) |
---|
| 685 | // NOTE: These values will not be use if DRAM is not available. Instead, the buffers will default |
---|
| 686 | // back to WARPLab 7.4.0 sizes |
---|
| 687 | // |
---|
| 688 | |
---|
| 689 | #if 0 |
---|
| 690 | |
---|
| 691 | //------------------------------------------------------------------------ |
---|
| 692 | // 1RF Case |
---|
| 693 | //------------------------------------------------------------------------ |
---|
| 694 | |
---|
| 695 | #define WL_BUF_DEFAULT_CHUNK_SIZE (DDR_SIZE / 16) |
---|
| 696 | |
---|
| 697 | // Define the maximum number of sample supported base on the "chunk" size |
---|
| 698 | #define WL_BUF_DEFAULT_RX_MAX_SAMPLES (((8 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
---|
| 699 | #define WL_BUF_DEFAULT_TX_MAX_SAMPLES (((7 * WL_BUF_DEFAULT_CHUNK_SIZE) >> 2) - 1) |
---|
| 700 | |
---|
| 701 | // Define RF A Buffer addresses / sizes |
---|
| 702 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR (DRAM_BASEADDR + ( 0 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 703 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR (DRAM_BASEADDR + ( 8 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 704 | #define WL_BUF_DEFAULT_RSSI_BUF_A_ADDR (DRAM_BASEADDR + (15 * WL_BUF_DEFAULT_CHUNK_SIZE)) |
---|
| 705 | #define WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE (8 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 706 | #define WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE (7 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 707 | #define WL_BUF_DEFAULT_RSSI_BUF_A_SIZE (1 * WL_BUF_DEFAULT_CHUNK_SIZE) |
---|
| 708 | |
---|
| 709 | |
---|
| 710 | #if WL_BUF_DEBUG_4RF_ON_2RF |
---|
[4783] | 711 | // In the case we want to debug the 4RF buffers on a 1RF design, |
---|
| 712 | // map RFB -> RFA, RFC -> RFA and RFD -> RFA |
---|
[4453] | 713 | |
---|
[4783] | 714 | // Define RF B Buffer addresses / sizes |
---|
| 715 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_ADDR WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR |
---|
| 716 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_ADDR WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR |
---|
| 717 | #define WL_BUF_DEFAULT_RSSI_BUF_B_ADDR WL_BUF_DEFAULT_RSSI_BUF_A_ADDR |
---|
| 718 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_SIZE WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE |
---|
| 719 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_SIZE WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE |
---|
| 720 | #define WL_BUF_DEFAULT_RSSI_BUF_B_SIZE WL_BUF_DEFAULT_RSSI_BUF_A_SIZE |
---|
[4453] | 721 | |
---|
[4783] | 722 | // Define RF C Buffer addresses / sizes |
---|
| 723 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR |
---|
| 724 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR |
---|
| 725 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR WL_BUF_DEFAULT_RSSI_BUF_A_ADDR |
---|
| 726 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE |
---|
| 727 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE |
---|
| 728 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE WL_BUF_DEFAULT_RSSI_BUF_A_SIZE |
---|
[4453] | 729 | |
---|
[4783] | 730 | // Define RF D Buffer addresses / sizes |
---|
| 731 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR WL_BUF_DEFAULT_IQ_RX_BUF_A_ADDR |
---|
| 732 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR WL_BUF_DEFAULT_IQ_TX_BUF_A_ADDR |
---|
| 733 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR WL_BUF_DEFAULT_RSSI_BUF_A_ADDR |
---|
| 734 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE WL_BUF_DEFAULT_IQ_RX_BUF_A_SIZE |
---|
| 735 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE WL_BUF_DEFAULT_IQ_TX_BUF_A_SIZE |
---|
| 736 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE WL_BUF_DEFAULT_RSSI_BUF_A_SIZE |
---|
[4453] | 737 | #else |
---|
[4783] | 738 | // Define RF B Buffer addresses / sizes |
---|
| 739 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_ADDR 0 |
---|
| 740 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_ADDR 0 |
---|
| 741 | #define WL_BUF_DEFAULT_RSSI_BUF_B_ADDR 0 |
---|
| 742 | #define WL_BUF_DEFAULT_IQ_RX_BUF_B_SIZE 0 |
---|
| 743 | #define WL_BUF_DEFAULT_IQ_TX_BUF_B_SIZE 0 |
---|
| 744 | #define WL_BUF_DEFAULT_RSSI_BUF_B_SIZE 0 |
---|
[4453] | 745 | |
---|
[4783] | 746 | // Define RF C Buffer addresses / sizes |
---|
| 747 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_ADDR 0 |
---|
| 748 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_ADDR 0 |
---|
| 749 | #define WL_BUF_DEFAULT_RSSI_BUF_C_ADDR 0 |
---|
| 750 | #define WL_BUF_DEFAULT_IQ_RX_BUF_C_SIZE 0 |
---|
| 751 | #define WL_BUF_DEFAULT_IQ_TX_BUF_C_SIZE 0 |
---|
| 752 | #define WL_BUF_DEFAULT_RSSI_BUF_C_SIZE 0 |
---|
[4453] | 753 | |
---|
[4783] | 754 | // Define RF D Buffer addresses / sizes |
---|
| 755 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_ADDR 0 |
---|
| 756 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_ADDR 0 |
---|
| 757 | #define WL_BUF_DEFAULT_RSSI_BUF_D_ADDR 0 |
---|
| 758 | #define WL_BUF_DEFAULT_IQ_RX_BUF_D_SIZE 0 |
---|
| 759 | #define WL_BUF_DEFAULT_IQ_TX_BUF_D_SIZE 0 |
---|
| 760 | #define WL_BUF_DEFAULT_RSSI_BUF_D_SIZE 0 |
---|
[4453] | 761 | #endif |
---|
| 762 | |
---|
| 763 | #endif // #if 0 |
---|
| 764 | |
---|
| 765 | |
---|
| 766 | |
---|
| 767 | // ********************************************************************** |
---|
| 768 | // Memory defines for BRAM sample buffers |
---|
| 769 | // - Renamed from XPAR* here for easier maintenance |
---|
| 770 | // |
---|
| 771 | #define WARPLAB_IQ_RX_BUF_A XPAR_RFA_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 772 | #define WARPLAB_IQ_TX_BUF_A XPAR_RFA_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 773 | #define WARPLAB_RSSI_BUF_A XPAR_RFA_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 774 | |
---|
| 775 | #define WARPLAB_IQ_RX_BUF_A_SIZE (XPAR_RFA_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFA_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 776 | #define WARPLAB_IQ_TX_BUF_A_SIZE (XPAR_RFA_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFA_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 777 | #define WARPLAB_RSSI_BUF_A_SIZE (XPAR_RFA_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFA_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 778 | |
---|
| 779 | #define WARPLAB_IQ_RX_BUF_B XPAR_RFB_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 780 | #define WARPLAB_IQ_TX_BUF_B XPAR_RFB_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 781 | #define WARPLAB_RSSI_BUF_B XPAR_RFB_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 782 | |
---|
| 783 | #define WARPLAB_IQ_RX_BUF_B_SIZE (XPAR_RFB_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFB_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 784 | #define WARPLAB_IQ_TX_BUF_B_SIZE (XPAR_RFB_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFB_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 785 | #define WARPLAB_RSSI_BUF_B_SIZE (XPAR_RFB_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFB_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 786 | |
---|
| 787 | |
---|
| 788 | // NOTE: Since the 2RF design does not contain memories for the RFC and RFD buffers |
---|
| 789 | // we will map RFC and RFD to 0 and set the buffer size to 0 so there are no issues |
---|
| 790 | // since there is no physical memory allocated (unlike previous revisions |
---|
| 791 | // where the memory was still allocated even though it wasn't used). |
---|
| 792 | // |
---|
| 793 | #if WARPLAB_CONFIG_4RF |
---|
[4783] | 794 | #define WARPLAB_IQ_RX_BUF_C XPAR_RFC_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 795 | #define WARPLAB_IQ_TX_BUF_C XPAR_RFC_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 796 | #define WARPLAB_RSSI_BUF_C XPAR_RFC_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
---|
[4453] | 797 | |
---|
[4783] | 798 | #define WARPLAB_IQ_RX_BUF_C_SIZE (XPAR_RFC_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFC_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 799 | #define WARPLAB_IQ_TX_BUF_C_SIZE (XPAR_RFC_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFC_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 800 | #define WARPLAB_RSSI_BUF_C_SIZE (XPAR_RFC_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFC_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
[4453] | 801 | |
---|
[4783] | 802 | #define WARPLAB_IQ_RX_BUF_D XPAR_RFD_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 803 | #define WARPLAB_IQ_TX_BUF_D XPAR_RFD_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR |
---|
| 804 | #define WARPLAB_RSSI_BUF_D XPAR_RFD_RSSI_BUFFER_CTRL_S_AXI_BASEADDR |
---|
[4453] | 805 | |
---|
[4783] | 806 | #define WARPLAB_IQ_RX_BUF_D_SIZE (XPAR_RFD_IQ_RX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFD_IQ_RX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 807 | #define WARPLAB_IQ_TX_BUF_D_SIZE (XPAR_RFD_IQ_TX_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFD_IQ_TX_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
| 808 | #define WARPLAB_RSSI_BUF_D_SIZE (XPAR_RFD_RSSI_BUFFER_CTRL_S_AXI_HIGHADDR - XPAR_RFD_RSSI_BUFFER_CTRL_S_AXI_BASEADDR + 1) |
---|
[4453] | 809 | #else |
---|
[4783] | 810 | #if WL_BUF_DEBUG_4RF_ON_2RF |
---|
| 811 | // In the case we want to debug the 4RF buffers on a 2RF design, |
---|
| 812 | // map RFC -> RFA and RFD -> RFB |
---|
| 813 | #define WARPLAB_IQ_RX_BUF_C WARPLAB_IQ_RX_BUF_A |
---|
| 814 | #define WARPLAB_IQ_TX_BUF_C WARPLAB_IQ_TX_BUF_A |
---|
| 815 | #define WARPLAB_RSSI_BUF_C WARPLAB_RSSI_BUF_A |
---|
[4453] | 816 | |
---|
[4783] | 817 | #define WARPLAB_IQ_RX_BUF_C_SIZE WARPLAB_IQ_RX_BUF_A_SIZE |
---|
| 818 | #define WARPLAB_IQ_TX_BUF_C_SIZE WARPLAB_IQ_TX_BUF_A_SIZE |
---|
| 819 | #define WARPLAB_RSSI_BUF_C_SIZE WARPLAB_RSSI_BUF_A_SIZE |
---|
[4453] | 820 | |
---|
[4783] | 821 | #define WARPLAB_IQ_RX_BUF_D WARPLAB_IQ_RX_BUF_B |
---|
| 822 | #define WARPLAB_IQ_TX_BUF_D WARPLAB_IQ_TX_BUF_B |
---|
| 823 | #define WARPLAB_RSSI_BUF_D WARPLAB_RSSI_BUF_B |
---|
[4453] | 824 | |
---|
[4783] | 825 | #define WARPLAB_IQ_RX_BUF_D_SIZE WARPLAB_IQ_RX_BUF_B_SIZE |
---|
| 826 | #define WARPLAB_IQ_TX_BUF_D_SIZE WARPLAB_IQ_TX_BUF_B_SIZE |
---|
| 827 | #define WARPLAB_RSSI_BUF_D_SIZE WARPLAB_RSSI_BUF_B_SIZE |
---|
| 828 | #else |
---|
| 829 | #define WARPLAB_IQ_RX_BUF_C 0 |
---|
| 830 | #define WARPLAB_IQ_TX_BUF_C 0 |
---|
| 831 | #define WARPLAB_RSSI_BUF_C 0 |
---|
[4453] | 832 | |
---|
[4783] | 833 | #define WARPLAB_IQ_RX_BUF_C_SIZE 0 |
---|
| 834 | #define WARPLAB_IQ_TX_BUF_C_SIZE 0 |
---|
| 835 | #define WARPLAB_RSSI_BUF_C_SIZE 0 |
---|
[4453] | 836 | |
---|
[4783] | 837 | #define WARPLAB_IQ_RX_BUF_D 0 |
---|
| 838 | #define WARPLAB_IQ_TX_BUF_D 0 |
---|
| 839 | #define WARPLAB_RSSI_BUF_D 0 |
---|
[4453] | 840 | |
---|
[4783] | 841 | #define WARPLAB_IQ_RX_BUF_D_SIZE 0 |
---|
| 842 | #define WARPLAB_IQ_TX_BUF_D_SIZE 0 |
---|
| 843 | #define WARPLAB_RSSI_BUF_D_SIZE 0 |
---|
| 844 | #endif |
---|
[4453] | 845 | #endif |
---|
| 846 | |
---|
| 847 | |
---|
| 848 | |
---|
| 849 | // ********************************************************************** |
---|
| 850 | // Defines for WARPLab Buffers Core |
---|
| 851 | // - Renamed from XPAR* here for easier maintenance |
---|
| 852 | // |
---|
| 853 | |
---|
| 854 | // Interupt ID |
---|
| 855 | #define WL_BUF_RX_INTERRUPT_ID XPAR_INTC_0_W3_WARPLAB_BUFFERS_AXIW_0_RF_RX_IQ_RSSI_INT_VEC_ID ///< XParameters rename of buffers core rx interrupt |
---|
| 856 | #define WL_BUF_TX_INTERRUPT_ID XPAR_INTC_0_W3_WARPLAB_BUFFERS_AXIW_0_RF_TX_IQ_INT_VEC_ID ///< XParameters rename of buffers core tx interrupt |
---|
| 857 | |
---|
| 858 | |
---|
| 859 | |
---|
| 860 | |
---|
| 861 | /*********************** Global Structure Definitions ************************/ |
---|
| 862 | |
---|
| 863 | /******************************** Functions **********************************/ |
---|
| 864 | |
---|
| 865 | int wl_baseband_setup_interrupt(XIntc* intc); |
---|
| 866 | |
---|
| 867 | #endif |
---|
| 868 | |
---|
[1915] | 869 | #endif /* WL_BASEBAND_H_ */ |
---|