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wl_trigger_manager.h

Last change on this file was 4927, checked in by welsh, 8 years ago
Cleaned up trigger manager command names: Instead of set_reset / clear_reset, changed to trig_disable / trig_enable; Formalized hold mode using defines. Increased trigger output delay for all outputs to conform to trigger manager v1.07.g.
File size: 38.2 KB

Line
1	/** @file wl_trigger_manager.h
2	* @brief WARPLab Framework (Trigger Manager)
3	*
4	* This contains the code for WARPLab Framework.
5	*
6	* @copyright Copyright 2013, Mango Communications. All rights reserved.
7	* Distributed under the WARP license (http://warpproject.org/license)
8	*
9	* @author Chris Hunter (chunter [at] mangocomm.com)
10	* @author Patrick Murphy (murphpo [at] mangocomm.com)
11	* @author Erik Welsh (welsh [at] mangocomm.com)
12	*/
13
14	/*************************** Include Files *******************************/
15
16	// WARPLab includes
17	#include "wl_common.h"
18
19
20
21	/************************* Constant Definitions **************************/
22	#ifndef TRIGCONF_H_
23	#define TRIGCONF_H_
24
25
26	// **********************************************************************
27	// Command IDs (must match the CMD_ properties in wl_transport_*.m)
28	//
29	#define CMDID_TRIG_MNGR_ADD_ETHERNET_TRIG 0x000001
30	#define CMDID_TRIG_MNGR_DEL_ETHERNET_TRIG 0x000002
31	#define CMDID_TRIG_MNGR_CLR_ETHERNET_TRIGS 0x000003
32	#define CMDID_TRIG_MNGR_HW_SW_ETHERNET_TRIG 0x000004
33
34	#define CMDID_TRIG_MNGR_INPUT_SEL 0x000010
35	#define CMDID_TRIG_MNGR_OUTPUT_DELAY 0x000011
36	#define CMDID_TRIG_MNGR_OUTPUT_HOLD 0x000012
37	#define CMDID_TRIG_MNGR_OUTPUT_READ 0x000013
38	#define CMDID_TRIG_MNGR_OUTPUT_CLEAR 0x000014
39
40	#define CMDID_TRIG_MNGR_INPUT_ENABLE 0x000020
41	#define CMDID_TRIG_MNGR_INPUT_DEBOUNCE 0x000021
42	#define CMDID_TRIG_MNGR_INPUT_DELAY 0x000022
43	#define CMDID_TRIG_MNGR_IDELAY 0x000023
44	#define CMDID_TRIG_MNGR_ODELAY 0x000024
45
46	#define CMDID_TRIG_MNGR_ENERGY_BUSY_THRESHOLD 0x000030
47	#define CMDID_TRIG_MNGR_ENERGY_RSSI_AVG_LEN 0x000031
48	#define CMDID_TRIG_MNGR_ENERGY_BUSY_MIN_LEN 0x000032
49	#define CMDID_TRIG_MNGR_ENERGY_IFC_SEL 0x000033
50
51	#define CMDID_TRIG_MNGR_TEST_TRIGGER 0x000080
52
53
54
55	// ----------------------------------------------------------------------------
56	// Misc Defines
57	//
58	#define NUM_INPUT_TRIGGERS 9
59	#define NUM_OUTPUT_TRIGGERS 6
60
61	#define ETH_TRIG_HW 0
62	#define ETH_TRIG_SW 1
63	#define ETH_TRIG_INVALID 0xFFFFFFFF
64
65
66
67	// ----------------------------------------------------------------------------
68	// Register Name Mapping
69	//
70	#define TRIG_MNGR_REG_CORE_INFO XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_CORE_INFO
71
72	#define TRIG_MNGR_REG_TRIG_OUTPUT XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT
73
74	#define TRIG_MNGR_REG_TRIG_IN_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_0
75	#define TRIG_MNGR_REG_TRIG_IN_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_1
76	#define TRIG_MNGR_REG_TRIG_IN_CONF_2 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_2
77	#define TRIG_MNGR_REG_TRIG_IN_CONF_3 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_3
78	#define TRIG_MNGR_REG_TRIG_IN_CONF_4 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_4
79	#define TRIG_MNGR_REG_TRIG_IN_CONF_5 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_5
80	#define TRIG_MNGR_REG_TRIG_IN_CONF_6 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_6
81	#define TRIG_MNGR_REG_TRIG_IN_CONF_7 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_7
82	#define TRIG_MNGR_REG_TRIG_IN_CONF_8 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IN_CONF_8
83
84	#define TRIG_MNGR_REG_TRIG_OUT_0_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_0_CONF_0
85	#define TRIG_MNGR_REG_TRIG_OUT_0_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_0_CONF_1
86	#define TRIG_MNGR_REG_TRIG_OUT_1_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_1_CONF_0
87	#define TRIG_MNGR_REG_TRIG_OUT_1_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_1_CONF_1
88	#define TRIG_MNGR_REG_TRIG_OUT_2_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_2_CONF_0
89	#define TRIG_MNGR_REG_TRIG_OUT_2_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_2_CONF_1
90	#define TRIG_MNGR_REG_TRIG_OUT_3_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_3_CONF_0
91	#define TRIG_MNGR_REG_TRIG_OUT_3_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_3_CONF_1
92	#define TRIG_MNGR_REG_TRIG_OUT_4_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_4_CONF_0
93	#define TRIG_MNGR_REG_TRIG_OUT_4_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_4_CONF_1
94	#define TRIG_MNGR_REG_TRIG_OUT_5_CONF_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_5_CONF_0
95	#define TRIG_MNGR_REG_TRIG_OUT_5_CONF_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_OUT_5_CONF_1
96
97	#define TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IODELAYS_CONTROL
98	#define TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_ODELAY_CFG_CMPLL
99	#define TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_ODELAY_CFG_DEBUG_HDR
100	#define TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IDELAY_CFG_CMPLL
101	#define TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_TRIG_IDELAY_CFG_DEBUG_HDR
102
103	#define TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_RSSI_PKT_DET_CONFIG
104	#define TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_RSSI_PKT_DET_DURATIONS
105	#define TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_RSSI_PKT_DET_THRESHOLDS
106
107	#define TRIG_MNGR_REG_PKT_OPS_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTOPS0
108	#define TRIG_MNGR_REG_PKT_OPS_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTOPS1
109	#define TRIG_MNGR_REG_PKT_TEMPLATE_0 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTTEMPLATE0
110	#define TRIG_MNGR_REG_PKT_TEMPLATE_1 XPAR_WARPLAB_TRIGGER_PROC_MEMMAP_PKTTEMPLATE1
111
112
113
114	// ----------------------------------------------------------------------------
115	// INPUT TRIGGER CONFIGURATION
116	//
117	//
118	// --------------------------------------------------------
119	// Configuration Register 0
120	// [ 4: 0] - Input Delay
121	// [29] - Use SW / HW for trigger (Ethernet triggers only)
122	// [30] - Raise Trigger (Ethernet and software triggers only)
123	// [30] - Debounce (External pin input triggers only)
124	// [31] - Reset
125	//
126	#define INPUT_DELAY_MASK 0x0000001F
127
128	#define INPUT_ETH_TRIGGER_SW_HW_MASK 0x20000000
129
130	#define INPUT_RAISE_TRIGGER_MASK 0x40000000
131	#define INPUT_EXT_TRIGGER_DEBOUNCE_MASK 0x40000000
132
133	#define INPUT_DISABLE_MASK 0x80000000
134
135
136	// --------------------------------------------------------
137	// Macros
138	//
139	#define trigger_proc_in_eth_A_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
140	#define trigger_proc_in_eth_A_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & INPUT_DELAY_MASK)
141	#define trigger_proc_in_eth_A_use_sw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) \| (INPUT_ETH_TRIGGER_SW_HW_MASK)))
142	#define trigger_proc_in_eth_A_use_hw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_ETH_TRIGGER_SW_HW_MASK)))
143	#define trigger_proc_in_eth_A_raise_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) \| (INPUT_RAISE_TRIGGER_MASK)))
144	#define trigger_proc_in_eth_A_lower_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_RAISE_TRIGGER_MASK)))
145	#define trigger_proc_in_eth_A_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) \| (INPUT_DISABLE_MASK)))
146	#define trigger_proc_in_eth_A_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_0) & (~INPUT_DISABLE_MASK)))
147
148	#define trigger_proc_in_energy_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_1) \| (INPUT_DISABLE_MASK)))
149	#define trigger_proc_in_energy_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_1) & (~INPUT_DISABLE_MASK)))
150
151	#define trigger_proc_in_agc_done_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_2, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
152	#define trigger_proc_in_agc_done_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) & INPUT_DELAY_MASK)
153	#define trigger_proc_in_agc_done_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_2, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) \| (INPUT_DISABLE_MASK)))
154	#define trigger_proc_in_agc_done_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_2, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_2) & (~INPUT_DISABLE_MASK)))
155
156	#define trigger_proc_in_software_raise_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) \| (INPUT_RAISE_TRIGGER_MASK)))
157	#define trigger_proc_in_software_lower_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) & (~INPUT_RAISE_TRIGGER_MASK)))
158	#define trigger_proc_in_software_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) \| (INPUT_DISABLE_MASK)))
159	#define trigger_proc_in_software_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_3, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_3) & (~INPUT_DISABLE_MASK)))
160
161	#define trigger_proc_in_ext_P0_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
162	#define trigger_proc_in_ext_P0_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & INPUT_DELAY_MASK)
163	#define trigger_proc_in_ext_P0_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) \| ((val & 1) << 30))
164	#define trigger_proc_in_ext_P0_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) \| (INPUT_DISABLE_MASK)))
165	#define trigger_proc_in_ext_P0_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_4, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_4) & (~INPUT_DISABLE_MASK)))
166
167	#define trigger_proc_in_ext_P1_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
168	#define trigger_proc_in_ext_P1_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & INPUT_DELAY_MASK)
169	#define trigger_proc_in_ext_P1_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) \| ((val & 1) << 30))
170	#define trigger_proc_in_ext_P1_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) \| (INPUT_DISABLE_MASK)))
171	#define trigger_proc_in_ext_P1_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_5, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_5) & (~INPUT_DISABLE_MASK)))
172
173	#define trigger_proc_in_ext_P2_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
174	#define trigger_proc_in_ext_P2_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & INPUT_DELAY_MASK)
175	#define trigger_proc_in_ext_P2_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) \| ((val & 1) << 30))
176	#define trigger_proc_in_ext_P2_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) \| (INPUT_DISABLE_MASK)))
177	#define trigger_proc_in_ext_P2_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_6, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_6) & (~INPUT_DISABLE_MASK)))
178
179	#define trigger_proc_in_ext_P3_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
180	#define trigger_proc_in_ext_P3_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & INPUT_DELAY_MASK)
181	#define trigger_proc_in_ext_P3_debounce_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & (~INPUT_EXT_TRIGGER_DEBOUNCE_MASK)) \| ((val & 1) << 30))
182	#define trigger_proc_in_ext_P3_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) \| (INPUT_DISABLE_MASK)))
183	#define trigger_proc_in_ext_P3_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_7, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_7) & (~INPUT_DISABLE_MASK)))
184
185	#define trigger_proc_in_eth_B_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_DELAY_MASK)) \| (val & INPUT_DELAY_MASK))
186	#define trigger_proc_in_eth_B_get_delay() (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & INPUT_DELAY_MASK)
187	#define trigger_proc_in_eth_B_use_sw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) \| (INPUT_ETH_TRIGGER_SW_HW_MASK)))
188	#define trigger_proc_in_eth_B_use_hw_trig() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_ETH_TRIGGER_SW_HW_MASK)))
189	#define trigger_proc_in_eth_B_raise_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) \| (INPUT_RAISE_TRIGGER_MASK)))
190	#define trigger_proc_in_eth_B_lower_trigger() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_RAISE_TRIGGER_MASK)))
191	#define trigger_proc_in_eth_B_trig_disable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) \| (INPUT_DISABLE_MASK)))
192	#define trigger_proc_in_eth_B_trig_enable() XIo_Out32(TRIG_MNGR_REG_TRIG_IN_CONF_8, (XIo_In32(TRIG_MNGR_REG_TRIG_IN_CONF_8) & (~INPUT_DISABLE_MASK)))
193
194
195
196	// ----------------------------------------------------------------------------
197	// IDELAY / ODELAY CONFIGURATION
198	//
199	//
200	#define IO_DELAY_MASK 0x0000001F
201
202	#define IO_DELAY_TYPE_PIN 0x00000000
203	#define IO_DELAY_TYPE_CM_PLL 0x00000001
204
205
206	// --------------------------------------------------------
207	// IDELAY / ODELAY Config register (CM-PLL and PIN registers)
208	// [ 4: 0] - External Pin 0 IDELAY / ODELAY value
209	// [12: 8] - External Pin 1 IDELAY / ODELAY value
210	// [20:16] - External Pin 2 IDELAY / ODELAY value
211	// [28:24] - External Pin 3 IDELAY / ODELAY value
212	//
213	#define EXT_P0_IO_DELAY_MASK 0x0000001F
214	#define EXT_P1_IO_DELAY_MASK 0x00001F00
215	#define EXT_P2_IO_DELAY_MASK 0x001F0000
216	#define EXT_P3_IO_DELAY_MASK 0x1F000000
217
218	#define EXT_P0_IO_DELAY_BIT_SHIFT 0
219	#define EXT_P1_IO_DELAY_BIT_SHIFT 8
220	#define EXT_P2_IO_DELAY_BIT_SHIFT 16
221	#define EXT_P3_IO_DELAY_BIT_SHIFT 24
222
223
224	// --------------------------------------------------------
225	// IDELAY / ODELAY Control register
226	// [0] - IDELAY update
227	// [1] - ODELAY update
228	//
229	#define IDELAY_UPDATE_MASK 0x00000001
230	#define ODELAY_UPDATE_MASK 0x00000002
231
232
233	// --------------------------------------------------------
234	// Macros
235	//
236	#define trigger_proc_in_ext_P0_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P0_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT)))
237	#define trigger_proc_in_ext_P0_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P0_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT)))
238	#define trigger_proc_in_ext_P0_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P0_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT)))
239	#define trigger_proc_in_ext_P0_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P0_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P0_IO_DELAY_BIT_SHIFT)))
240	#define trigger_proc_in_ext_P0_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT)
241	#define trigger_proc_in_ext_P0_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT)
242	#define trigger_proc_in_ext_P0_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT)
243	#define trigger_proc_in_ext_P0_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P0_IO_DELAY_MASK) >> EXT_P0_IO_DELAY_BIT_SHIFT)
244
245	#define trigger_proc_in_ext_P1_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P1_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT)))
246	#define trigger_proc_in_ext_P1_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P1_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT)))
247	#define trigger_proc_in_ext_P1_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P1_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT)))
248	#define trigger_proc_in_ext_P1_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P1_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P1_IO_DELAY_BIT_SHIFT)))
249	#define trigger_proc_in_ext_P1_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT)
250	#define trigger_proc_in_ext_P1_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT)
251	#define trigger_proc_in_ext_P1_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT)
252	#define trigger_proc_in_ext_P1_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P1_IO_DELAY_MASK) >> EXT_P1_IO_DELAY_BIT_SHIFT)
253
254	#define trigger_proc_in_ext_P2_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P2_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT)))
255	#define trigger_proc_in_ext_P2_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P2_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT)))
256	#define trigger_proc_in_ext_P2_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P2_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT)))
257	#define trigger_proc_in_ext_P2_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P2_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P2_IO_DELAY_BIT_SHIFT)))
258	#define trigger_proc_in_ext_P2_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT)
259	#define trigger_proc_in_ext_P2_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT)
260	#define trigger_proc_in_ext_P2_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT)
261	#define trigger_proc_in_ext_P2_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P2_IO_DELAY_MASK) >> EXT_P2_IO_DELAY_BIT_SHIFT)
262
263	#define trigger_proc_in_ext_P3_set_idelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & (~EXT_P3_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT)))
264	#define trigger_proc_in_ext_P3_set_idelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & (~EXT_P3_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT)))
265	#define trigger_proc_in_ext_P3_set_odelay_pin(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & (~EXT_P3_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT)))
266	#define trigger_proc_in_ext_P3_set_odelay_cm_pll(val) XIo_Out32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL, ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & (~EXT_P3_IO_DELAY_MASK)) \| ((val & IO_DELAY_MASK) << EXT_P3_IO_DELAY_BIT_SHIFT)))
267	#define trigger_proc_in_ext_P3_get_idelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_PIN) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT)
268	#define trigger_proc_in_ext_P3_get_idelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_IDELAY_CFG_CMPLL) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT)
269	#define trigger_proc_in_ext_P3_get_odelay_pin() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_PIN) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT)
270	#define trigger_proc_in_ext_P3_get_odelay_cm_pll() ((XIo_In32(TRIG_MNGR_REG_TRIG_ODELAY_CFG_CMPLL) & EXT_P3_IO_DELAY_MASK) >> EXT_P3_IO_DELAY_BIT_SHIFT)
271
272
273	#define trigger_proc_idelay_update_set() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~IDELAY_UPDATE_MASK)) \| IDELAY_UPDATE_MASK))
274	#define trigger_proc_idelay_update_clear() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, (XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~IDELAY_UPDATE_MASK)))
275
276	#define trigger_proc_odelay_update_set() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, ((XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~ODELAY_UPDATE_MASK)) \| ODELAY_UPDATE_MASK))
277	#define trigger_proc_odelay_update_clear() XIo_Out32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL, (XIo_In32(TRIG_MNGR_REG_TRIG_IODELAYS_CONTROL) & (~ODELAY_UPDATE_MASK)))
278
279
280
281	// ----------------------------------------------------------------------------
282	// OUTPUT TRIGGER CONFIGURATION
283	//
284	// The output triggers are:
285	// OUT0 - Baseband
286	// OUT1 - AGC
287	// OUT2 - External output pin 0
288	// OUT3 - External output pin 1
289	// OUT4 - External output pin 2
290	// OUT5 - External output pin 3
291	//
292	// --------------------------------------------------------
293	// Configuration Register 0
294	// [ 8: 0] - AND terms used to trigger output
295	// [15: 9] - Reserved
296	// [24:16] - OR terms used to trigger output
297	// [31:25] - Reserved
298	//
299	#define AND_OFFSET_BITS 0
300
301	#define AND_ETH_A 0x00000001
302	#define AND_ENERGY 0x00000002
303	#define AND_AGC_DONE 0x00000004
304	#define AND_SOFTWARE 0x00000008
305	#define AND_DEBUG0 0x00000010
306	#define AND_DEBUG1 0x00000020
307	#define AND_DEBUG2 0x00000040
308	#define AND_DEBUG3 0x00000080
309	#define AND_ETH_B 0x00000100
310	#define AND_ALL 0x000001FF
311
312	#define OR_OFFSET_BITS 16
313
314	#define OR_ETH_A 0x00010000
315	#define OR_ENERGY 0x00020000
316	#define OR_AGC_DONE 0x00040000
317	#define OR_SOFTWARE 0x00080000
318	#define OR_DEBUG0 0x00100000
319	#define OR_DEBUG1 0x00200000
320	#define OR_DEBUG2 0x00400000
321	#define OR_DEBUG3 0x00800000
322	#define OR_ETH_B 0x01000000
323	#define OR_ALL 0x01FF0000
324
325
326	// --------------------------------------------------------
327	// Configuration Register 1
328	// [15: 0] - Output Trigger Delay
329	// [29:16] - Reserved
330	// [30] - Output Trigger Pulse Extender Bypass
331	// [31] - Reset
332	//
333	// NOTE: The AGC output trigger has an extended delay to allow for more flexibility about when to
334	// start the AGC. The Delay value for the AGC is 16 bits.
335	//
336	//
337	#define OUT_DELAY_MASK 0x0000FFFF
338
339	#define OUT_PULSE_EXTENDER_BYPASS_MASK 0x40000000
340	#define OUT_HOLD_MODE_MASK 0x80000000
341
342	#define OUT_HOLD_MODE_ENABLE 0
343	#define OUT_HOLD_MODE_DISABLE 1
344
345
346	// --------------------------------------------------------
347	// Register Macros
348
349	#define trigger_proc_out0_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0) \| (mask)))
350	#define trigger_proc_out0_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0) & (~(mask))))
351	#define trigger_proc_out0_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) & OUT_HOLD_MODE_MASK) >> 31)
352	#define trigger_proc_out0_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) & (~(OUT_HOLD_MODE_MASK))) \| ((val << 31) & OUT_HOLD_MODE_MASK))
353	#define trigger_proc_out0_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1) & (~(OUT_DELAY_MASK ))) \| (val & OUT_DELAY_MASK ))
354	#define trigger_proc_out0_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_0)
355	#define trigger_proc_out0_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_0_CONF_1)
356
357	#define trigger_proc_out1_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0) \| (mask)))
358	#define trigger_proc_out1_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0) & (~(mask))))
359	#define trigger_proc_out1_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) & OUT_HOLD_MODE_MASK) >> 31)
360	#define trigger_proc_out1_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) & (~(OUT_HOLD_MODE_MASK))) \| ((val << 31) & OUT_HOLD_MODE_MASK))
361	#define trigger_proc_out1_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1) & (~(OUT_DELAY_MASK ))) \| (val & OUT_DELAY_MASK ))
362	#define trigger_proc_out1_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_0)
363	#define trigger_proc_out1_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_1_CONF_1)
364
365	#define trigger_proc_out2_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0) \| (mask)))
366	#define trigger_proc_out2_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0) & (~(mask))))
367	#define trigger_proc_out2_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) & OUT_HOLD_MODE_MASK) >> 31)
368	#define trigger_proc_out2_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) & (~(OUT_HOLD_MODE_MASK))) \| ((val << 31) & OUT_HOLD_MODE_MASK))
369	#define trigger_proc_out2_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1) & (~(OUT_DELAY_MASK ))) \| (val & OUT_DELAY_MASK ))
370	#define trigger_proc_out2_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_0)
371	#define trigger_proc_out2_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_2_CONF_1)
372
373	#define trigger_proc_out3_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0) \| (mask)))
374	#define trigger_proc_out3_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0) & (~(mask))))
375	#define trigger_proc_out3_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) & OUT_HOLD_MODE_MASK) >> 31)
376	#define trigger_proc_out3_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) & (~(OUT_HOLD_MODE_MASK))) \| ((val << 31) & OUT_HOLD_MODE_MASK))
377	#define trigger_proc_out3_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1) & (~(OUT_DELAY_MASK ))) \| (val & OUT_DELAY_MASK ))
378	#define trigger_proc_out3_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_0)
379	#define trigger_proc_out3_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_3_CONF_1)
380
381	#define trigger_proc_out4_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0) \| (mask)))
382	#define trigger_proc_out4_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0) & (~(mask))))
383	#define trigger_proc_out4_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) & OUT_HOLD_MODE_MASK) >> 31)
384	#define trigger_proc_out4_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) & (~(OUT_HOLD_MODE_MASK))) \| ((val << 31) & OUT_HOLD_MODE_MASK))
385	#define trigger_proc_out4_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1) & (~(OUT_DELAY_MASK ))) \| (val & OUT_DELAY_MASK ))
386	#define trigger_proc_out4_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_0)
387	#define trigger_proc_out4_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_4_CONF_1)
388
389	#define trigger_proc_out5_set_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0) \| (mask)))
390	#define trigger_proc_out5_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0) & (~(mask))))
391	#define trigger_proc_out5_get_hold_mode() ((XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) & OUT_HOLD_MODE_MASK) >> 31)
392	#define trigger_proc_out5_set_hold_mode(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) & (~(OUT_HOLD_MODE_MASK))) \| ((val << 31) & OUT_HOLD_MODE_MASK))
393	#define trigger_proc_out5_set_delay(val) XIo_Out32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1, (XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1) & (~(OUT_DELAY_MASK ))) \| (val & OUT_DELAY_MASK ))
394	#define trigger_proc_out5_get_reg_0() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_0)
395	#define trigger_proc_out5_get_reg_1() XIo_In32(TRIG_MNGR_REG_TRIG_OUT_5_CONF_1)
396
397
398
399	// ----------------------------------------------------------------------------
400	// Misc Registers
401	//
402	// --------------------------------------------------------
403	// Trigger Output Value Register:
404	// [ 7: 0] - Number of Trigger Inputs
405	// [15: 8] - Number of Trigger Outputs
406	// [23:16] - Core ID
407	// [31:24] - Reserved
408	//
409	#define trigger_proc_get_core_info() (XIo_In32(TRIG_MNGR_REG_CORE_INFO))
410
411
412
413	// --------------------------------------------------------
414	// Trigger Output Value Register:
415	// [ 0] - Value of Output Trigger 0
416	// [ 1] - Value of Output Trigger 1
417	// [ 2] - Value of Output Trigger 2
418	// [ 3] - Value of Output Trigger 3
419	// [ 4] - Value of Output Trigger 4
420	// [ 5] - Value of Output Trigger 5
421	// [31: 6] - Reserved
422	//
423	#define OUT0 0x00000001
424	#define OUT1 0x00000002
425	#define OUT2 0x00000004
426	#define OUT3 0x00000008
427	#define OUT4 0x00000010
428	#define OUT5 0x00000020
429
430
431	// --------------------------------------------------------
432	// Macros
433	//
434	#define trigger_proc_get_output_values() (XIo_In32(TRIG_MNGR_REG_TRIG_OUTPUT))
435
436
437
438	// ----------------------------------------------------------------------------
439	// Energy Detection Registers
440	//
441	// --------------------------------------------------------
442	// Configuration Register:
443	// [ 0] - Detect energy on RFA
444	// [ 1] - Detect energy on RFB
445	// [ 2] - Detect energy on RFC
446	// [ 3] - Detect energy on RFD
447	// [30: 4] - Reserved
448	// [31] - Reset
449	//
450	#define WL_PACKET_DETECT_CONFIG_REG_RESET 0x80000000
451	#define WL_PACKET_DETECT_CONFIG_REG_MASK_A 0x00000001
452	#define WL_PACKET_DETECT_CONFIG_REG_MASK_B 0x00000002
453	#define WL_PACKET_DETECT_CONFIG_REG_MASK_C 0x00000004
454	#define WL_PACKET_DETECT_CONFIG_REG_MASK_D 0x00000008
455	#define WL_PACKET_DETECT_CONFIG_REG_MASK_ALL 0x0000000F
456
457
458	// --------------------------------------------------------
459	// Macros
460	//
461
462	// Convert interface masks to packet detect mask
463	#define IFC_TO_PACKET_DETECT_MASK(val) (val >> 28)
464
465	#define wl_packet_detect_set_config(mask) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG) \| (mask)))
466	#define wl_packet_detect_clear_config(mask) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_CONFIG) & (~(mask))))
467
468	#define wl_packet_detect_set_idle_threshold(idle) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS) & (~0x0000FFFF)) \| (idle & 0x0000FFFF))
469	#define wl_packet_detect_set_busy_threshold(busy) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_THRESHOLDS) & (~0xFFFF0000)) \| ((busy << 16)& 0xFFFF0000))
470
471	#define wl_packet_detect_set_RSSI_duration(rssi) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS) & (~0x1F0000)) \| ((rssi <<16)& 0x1F0000))
472	#define wl_packet_detect_set_idle_duration(idle) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS) & (~0x0000FF)) \| (idle & 0x0000FF))
473	#define wl_packet_detect_set_busy_duration(busy) XIo_Out32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS, (XIo_In32(TRIG_MNGR_REG_RSSI_PKT_DET_DURATIONS) & (~0x00FF00)) \| ((busy << 8)& 0x00FF00))
474
475
476
477	// ----------------------------------------------------------------------------
478	// Defines for warplab_trigger_proc core operators
479
480	// Equals
481	#define U8_OP_EQ 0x01
482	#define U16_OP_EQ ((U8_OP_EQ << 8) \| U8_OP_EQ)
483	#define U32_OP_EQ ((U8_OP_EQ << 24) \| (U8_OP_EQ << 16) \| (U8_OP_EQ << 8) \| U8_OP_EQ)
484
485	// Not-equals
486	#define U8_OP_NEQ 0x02
487	#define U16_OP_NEQ ((U8_OP_NEQ << 8) \| U8_OP_NEQ)
488	#define U32_OP_NEQ ((U8_OP_NEQ << 24) \| (U8_OP_NEQ << 16) \| (U8_OP_NEQ << 8) \| U8_OP_NEQ)
489
490	// No care (byte is ignored)
491	#define U8_OP_NC 0x00
492	#define U16_OP_NC ((U8_OP_NC << 8) \| U8_OP_NC)
493	#define U32_OP_NC ((U8_OP_NC << 24) \| (U8_OP_NC << 16) \| (U8_OP_NC << 8) \| U8_OP_NC)
494
495	// Any-of-and (and(x,y) > 0)
496	#define U8_OP_AA 0x03
497	#define U16_OP_AA ((U8_OP_AA << 8) \| U8_OP_AA)
498	#define U32_OP_AA ((U8_OP_AA << 24) \| (U8_OP_AA << 16) \| (U8_OP_AA << 8) \| U8_OP_AA)
499
500
501
502	/********************* Global Structure Definitions **********************/
503
504
505
506	/************************* Function Prototypes ***************************/
507	int trigmngr_init();
508
509	int trigmngr_process_cmd(int socket_index, void * from, wl_cmd_resp * command, wl_cmd_resp * response);
510
511	void trigmngr_trigger_in(u32 trig_id, u32 eth_dev_num);
512
513
514	#endif /* TRIGCONF_H_ */

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source: ResearchApps/PHY/WARPLAB/WARPLab7/C_Code_Reference/include/wl_trigger_manager.h

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