source: ResearchApps/PHY/WARPLAB/WARPLab7/XPS_Reference/w3_2RF/data/system.ucf

Last change on this file was 4710, checked in by welsh, 9 years ago

Updating UCF file for CM-PLL rev 1.1
File size: 34.2 KB
RevLine 
[4647]1# ##############################################################################
2# WARPLab Reference Design
3# XPS Constraint Specification (system.ucf)
4# Copyright 2013 Mango Communications
5# Distributed under the WARP license  (http://warpproject.org/license)
6# WARPLab version:  7.6.0
7# Family:           virtex6
8# Device:           xc6vlx240t
9# Package:          ff1156
10# Speed Grade:      -1
11# ##############################################################################
[1918]12
13
[4647]14# ###################################################################
15# Debug Header Ports
16# ###################################################################
17
18NET "DEBUGHDR<0>"                 LOC = "AG27" | IOSTANDARD = "LVCMOS25";                # pin 0
19NET "DEBUGHDR<1>"                 LOC = "AE26" | IOSTANDARD = "LVCMOS25";                # pin 1
20NET "debug_sw_gpio<0>"            LOC = "AF26" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 2
21NET "debug_sw_gpio<1>"            LOC = "AD25" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 3
22
[4185]23# NOTE:  As of WARPLab 7.5.0, pins 4 - 7 are used as duplicate trigger_out[3:0] ports.  To change
24#     them back to software GPIO pins, please uncomment the following lines and comment out the
25#     first set of trigger_out pins.
26#
[4647]27# NET "debug_sw_gpio<2>"            LOC = "V24"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 4
28# NET "debug_sw_gpio<3>"            LOC = "AA23" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 5
29# NET "debug_sw_gpio<4>"            LOC = "AH30" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 6
30# NET "debug_sw_gpio<5>"            LOC = "AK31" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 7
[4185]31
[4647]32NET "trigger_1_out<0>"            LOC = "V24"  | IOSTANDARD = "LVCMOS25";                # pin 4
33NET "trigger_1_out<1>"            LOC = "AA23" | IOSTANDARD = "LVCMOS25";                # pin 5
34NET "trigger_1_out<2>"            LOC = "AH30" | IOSTANDARD = "LVCMOS25";                # pin 6
35NET "trigger_1_out<3>"            LOC = "AK31" | IOSTANDARD = "LVCMOS25";                # pin 7
[4185]36
[4647]37NET "trigger_0_out<0>"            LOC = "AG28" | IOSTANDARD = "LVCMOS25";                # pin 8
38NET "trigger_0_out<1>"            LOC = "AE27" | IOSTANDARD = "LVCMOS25";                # pin 9
39NET "trigger_0_out<2>"            LOC = "AF28" | IOSTANDARD = "LVCMOS25";                # pin 10
40NET "trigger_0_out<3>"            LOC = "AJ29" | IOSTANDARD = "LVCMOS25";                # pin 11
[1918]41
[4647]42NET "trigger_in<0>"               LOC = "AH29" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 12
43NET "trigger_in<1>"               LOC = "AL30" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 13
44NET "trigger_in<2>"               LOC = "AM31" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 14
45NET "trigger_in<3>"               LOC = "AP32" | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # pin 15
[2033]46
[4647]47
48# ###################################################################
49# Clock & Reset Ports / Definitions
50# ###################################################################
51
52# System clock (80MHz, from sampling clock buffer)
53NET "samp_clk_n"                  LOC = "V23"  | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
54NET "samp_clk_p"                  LOC = "U23"  | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
55
56NET "samp_clk_p"                  TNM_NET = "samp_clk";
57TIMESPEC "TS_samp_clk" = PERIOD "samp_clk" 80000 kHz;
58
59
60# System clock (200MHz, from LVDS oscillator)
61NET "osc200_p"                    LOC = "A10"  | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
62NET "osc200_n"                    LOC = "B10"  | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
63
64NET "osc200_p"                    TNM_NET = "osc200_p";
65TIMESPEC "TS_osc200_p" = PERIOD "osc200_p" 200000 kHz;
66
67# System reset
68NET "RESET"                       LOC = "AH13" | IOSTANDARD = "LVCMOS15" | TIG;
69
70
71# ###################################################################
72# Clock Module Header Ports
73# ###################################################################
74
[4710]75# Trigger in/out via CM-PLL daisy chain headers - CM-PLL rev 1.1
[4647]76NET "cm_pll_hdr_in_d<0>"          LOC = "V28"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL3  in W3 schematics
77NET "cm_pll_hdr_in_d<1>"          LOC = "V27"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL2  in W3 schematics
78NET "cm_pll_hdr_in_d<2>"          LOC = "V33"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL1  in W3 schematics
79NET "cm_pll_hdr_in_d<3>"          LOC = "V34"  | IOSTANDARD = "LVCMOS25" | PULLDOWN;     # CLKHDR_CTRL0  in W3 schematics
[4307]80
[4710]81NET "cm_pll_hdr_out_d<0>"         LOC = "V32"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL4  in W3 schematics
[4647]82NET "cm_pll_hdr_out_d<1>"         LOC = "W34"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL5  in W3 schematics
[4710]83NET "cm_pll_hdr_out_d<2>"         LOC = "W30"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL6  in W3 schematics
[4647]84NET "cm_pll_hdr_out_d<3>"         LOC = "W29"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL7  in W3 schematics
[4307]85
[4647]86# SIP switch on clock module
87NET "cm_switch<0>"                LOC = "V30"  | IOSTANDARD = "LVCMOS25" | PULLUP;       # CLKHDR_CTRL12 in W3 schematics
88NET "cm_switch<1>"                LOC = "R34"  | IOSTANDARD = "LVCMOS25" | PULLUP;       # CLKHDR_CTRL13 in W3 schematics
89NET "cm_switch<2>"                LOC = "W26"  | IOSTANDARD = "LVCMOS25" | PULLUP;       # CLKHDR_CTRL14 in W3 schematics
[1918]90
[4647]91# SPI on clock module
92NET "cm_spi_sclk"                 LOC = "Y34"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL8  in W3 schematics (CM hdr p25)
93NET "cm_spi_mosi"                 LOC = "Y31"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL10 in W3 schematics (CM hdr p29)
94NET "cm_spi_miso"                 LOC = "Y33"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL9  in W3 schematics (CM hdr p27)
95NET "cm_spi_cs_n"                 LOC = "Y32"  | IOSTANDARD = "LVCMOS25";                # CLKHDR_CTRL11 in W3 schematics (CM hdr p31)
96NET "cm_pll_status"               LOC = "V29"  | IOSTANDARD = "LVCMOS25" | PULLUP;       # CLKHDR_CTRL15 in W3 schematics (CM hdr p14)
[1918]97
[4647]98# FPGA CC pins connected to clock module header
99#     NOTE:  CM-PLL drives these with copy of selected PLL reference clock
100#     NOTE:  Constrained to 200MHz (overkill, but easy to meet given the simple logic)
101NET "pll_refclk_p"                LOC = "AD24" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
102NET "pll_refclk_n"                LOC = "AE24" | IOSTANDARD = "LVDS_25" | DIFF_TERM = TRUE;
[4307]103
[4647]104NET "pll_refclk_p"                TNM_NET = "pll_refclk";
105TIMESPEC "TS_pll_refclk" = PERIOD "pll_refclk" 200000 kHz;
[1918]106
107
[4647]108# ###################################################################
109# User IO Ports
110# ###################################################################
[1918]111
[4647]112NET "userio_dipsw<0>"             LOC = "AM22" | IOSTANDARD = "LVCMOS15";
113NET "userio_dipsw<1>"             LOC = "AL23" | IOSTANDARD = "LVCMOS15";
114NET "userio_dipsw<2>"             LOC = "AM23" | IOSTANDARD = "LVCMOS15";
115NET "userio_dipsw<3>"             LOC = "AN23" | IOSTANDARD = "LVCMOS15";
[1918]116
[4647]117NET "userio_leds_red<0>"          LOC = "AN34" | IOSTANDARD = "LVCMOS25";
118NET "userio_leds_red<1>"          LOC = "AM33" | IOSTANDARD = "LVCMOS25";
119NET "userio_leds_red<2>"          LOC = "AN33" | IOSTANDARD = "LVCMOS25";
120NET "userio_leds_red<3>"          LOC = "AP33" | IOSTANDARD = "LVCMOS25";
[1918]121
[4647]122NET "userio_leds_green<0>"        LOC = "AD22" | IOSTANDARD = "LVCMOS25";
123NET "userio_leds_green<1>"        LOC = "AE22" | IOSTANDARD = "LVCMOS25";
124NET "userio_leds_green<2>"        LOC = "AM32" | IOSTANDARD = "LVCMOS25";
125NET "userio_leds_green<3>"        LOC = "AN32" | IOSTANDARD = "LVCMOS25";
[1918]126
[4647]127NET "userio_pb_u"                 LOC = "AM21" | IOSTANDARD = "LVCMOS15";
128NET "userio_pb_m"                 LOC = "AN22" | IOSTANDARD = "LVCMOS15";
129NET "userio_pb_d"                 LOC = "AP22" | IOSTANDARD = "LVCMOS15";
[4307]130
[4647]131NET "userio_hexdisp_left<0>"      LOC = "AL33" | IOSTANDARD = "LVCMOS25";
132NET "userio_hexdisp_left<1>"      LOC = "AK33" | IOSTANDARD = "LVCMOS25";
133NET "userio_hexdisp_left<2>"      LOC = "AH32" | IOSTANDARD = "LVCMOS25";
134NET "userio_hexdisp_left<3>"      LOC = "AF29" | IOSTANDARD = "LVCMOS25";
135NET "userio_hexdisp_left<4>"      LOC = "AE29" | IOSTANDARD = "LVCMOS25";
136NET "userio_hexdisp_left<5>"      LOC = "AK32" | IOSTANDARD = "LVCMOS25";
137NET "userio_hexdisp_left<6>"      LOC = "AF30" | IOSTANDARD = "LVCMOS25";
138NET "userio_hexdisp_left_dp"      LOC = "AG30" | IOSTANDARD = "LVCMOS25";
[1918]139
[4647]140NET "userio_hexdisp_right<0>"     LOC = "AE28" | IOSTANDARD = "LVCMOS25";
141NET "userio_hexdisp_right<1>"     LOC = "AD26" | IOSTANDARD = "LVCMOS25";
142NET "userio_hexdisp_right<2>"     LOC = "AC24" | IOSTANDARD = "LVCMOS25";
143NET "userio_hexdisp_right<3>"     LOC = "AE23" | IOSTANDARD = "LVCMOS25";
144NET "userio_hexdisp_right<4>"     LOC = "AC22" | IOSTANDARD = "LVCMOS25";
145NET "userio_hexdisp_right<5>"     LOC = "AD27" | IOSTANDARD = "LVCMOS25";
146NET "userio_hexdisp_right<6>"     LOC = "AB23" | IOSTANDARD = "LVCMOS25";
147NET "userio_hexdisp_right_dp"     LOC = "AC23" | IOSTANDARD = "LVCMOS25";
[1918]148
[4647]149NET "userio_rfa_led_red"          LOC = "AL34" | IOSTANDARD = "LVCMOS25";
150NET "userio_rfa_led_green"        LOC = "AK34" | IOSTANDARD = "LVCMOS25";
151NET "userio_rfb_led_red"          LOC = "AJ34" | IOSTANDARD = "LVCMOS25";
152NET "userio_rfb_led_green"        LOC = "AH34" | IOSTANDARD = "LVCMOS25";
[1918]153
154
[4647]155# ###################################################################
156# UART Ports
157# ###################################################################
[1918]158
[4647]159NET "usb_uart_sin"                LOC = "J9"   | IOSTANDARD = "LVCMOS25";
160NET "usb_uart_sout"               LOC = "H9"   | IOSTANDARD = "LVCMOS25";
[4307]161
[1918]162
[4647]163# ###################################################################
164# SPI Ports
165# ###################################################################
[1918]166
[4647]167# RF reference clock SPI
168NET "clk_rfref_spi_sclk"          LOC = "V25"  | IOSTANDARD = "LVCMOS25";
169NET "clk_rfref_spi_mosi"          LOC = "W25"  | IOSTANDARD = "LVCMOS25";
170NET "clk_rfref_spi_cs_n"          LOC = "W27"  | IOSTANDARD = "LVCMOS25";
171NET "clk_rfref_spi_miso"          LOC = "Y27"  | IOSTANDARD = "LVCMOS25";
172NET "clk_rfref_func"              LOC = "L26"  | IOSTANDARD = "LVCMOS25";
[1918]173
[4647]174# Sample clock SPI
175NET "clk_samp_spi_sclk"           LOC = "W32"  | IOSTANDARD = "LVCMOS25";
176NET "clk_samp_spi_mosi"           LOC = "Y29"  | IOSTANDARD = "LVCMOS25";
177NET "clk_samp_spi_cs_n"           LOC = "W31"  | IOSTANDARD = "LVCMOS25";
178NET "clk_samp_spi_miso"           LOC = "Y28"  | IOSTANDARD = "LVCMOS25";
179NET "clk_samp_func"               LOC = "R33"  | IOSTANDARD = "LVCMOS25";
[1918]180
[2080]181
[4647]182# ###################################################################
183# I2C (IIC) Ports
184# ###################################################################
[2080]185
[4647]186# IIC EEPROM
187NET "IIC_EEPROM_iic_sda"          LOC = "AG23" | IOSTANDARD = "LVCMOS25";
188NET "IIC_EEPROM_iic_scl"          LOC = "AF23" | IOSTANDARD = "LVCMOS25";
[1918]189
190
[4647]191# ###################################################################
192# Ethernet Ports / Definitions
193# ###################################################################
[1918]194
[4647]195# Ethernet A Ports
196#   NOTE: Ports are for 88e1121R (pg 9 of W3 schematics)
197NET "ETH_A_PD"                    LOC = "K9"   | IOSTANDARD = "LVCMOS25" | TIG;
198NET "ETH_A_RGMII_TXD<0>"          LOC = "AF9"  | IOSTANDARD = "LVCMOS25";
199NET "ETH_A_RGMII_TXD<1>"          LOC = "AF10" | IOSTANDARD = "LVCMOS25";
200NET "ETH_A_RGMII_TXD<2>"          LOC = "AD9"  | IOSTANDARD = "LVCMOS25";
201NET "ETH_A_RGMII_TXD<3>"          LOC = "AD10" | IOSTANDARD = "LVCMOS25";
202NET "ETH_A_RGMII_TX_CTL"          LOC = "AG8"  | IOSTANDARD = "LVCMOS25";
203NET "ETH_A_RGMII_TXC"             LOC = "AE9"  | IOSTANDARD = "LVCMOS25";
204NET "ETH_A_RGMII_RXD<0>"          LOC = "AK9"  | IOSTANDARD = "LVCMOS25";
205NET "ETH_A_RGMII_RXD<1>"          LOC = "AJ9"  | IOSTANDARD = "LVCMOS25";
206NET "ETH_A_RGMII_RXD<2>"          LOC = "AH8"  | IOSTANDARD = "LVCMOS25";
207NET "ETH_A_RGMII_RXD<3>"          LOC = "AH9"  | IOSTANDARD = "LVCMOS25";
208NET "ETH_A_RGMII_RX_CTL"          LOC = "AL9"  | IOSTANDARD = "LVCMOS25";
209NET "ETH_A_RGMII_RXC"             LOC = "AC10" | IOSTANDARD = "LVCMOS25";
210NET "ETH_A_MDC"                   LOC = "AK8"  | IOSTANDARD = "LVCMOS25";
211NET "ETH_A_MDIO"                  LOC = "AP9"  | IOSTANDARD = "LVCMOS25" | PULLUP;
212
213# Ethernet B Ports
214NET "ETH_B_PD"                    LOC = "E8"   | IOSTANDARD = "LVCMOS25" | TIG;
215NET "ETH_B_RGMII_TXD<0>"          LOC = "M10"  | IOSTANDARD = "LVCMOS25";
216NET "ETH_B_RGMII_TXD<1>"          LOC = "B8"   | IOSTANDARD = "LVCMOS25";
217NET "ETH_B_RGMII_TXD<2>"          LOC = "AC9"  | IOSTANDARD = "LVCMOS25";
218NET "ETH_B_RGMII_TXD<3>"          LOC = "E9"   | IOSTANDARD = "LVCMOS25";
219NET "ETH_B_RGMII_TX_CTL"          LOC = "D10"  | IOSTANDARD = "LVCMOS25";
220NET "ETH_B_RGMII_TXC"             LOC = "AB10" | IOSTANDARD = "LVCMOS25";
221NET "ETH_B_RGMII_RXD<0>"          LOC = "A9"   | IOSTANDARD = "LVCMOS25";
222NET "ETH_B_RGMII_RXD<1>"          LOC = "D9"   | IOSTANDARD = "LVCMOS25";
223NET "ETH_B_RGMII_RXD<2>"          LOC = "C9"   | IOSTANDARD = "LVCMOS25";
224NET "ETH_B_RGMII_RXD<3>"          LOC = "F10"  | IOSTANDARD = "LVCMOS25";
225NET "ETH_B_RGMII_RX_CTL"          LOC = "A8"   | IOSTANDARD = "LVCMOS25";
226NET "ETH_B_RGMII_RXC"             LOC = "L10"  | IOSTANDARD = "LVCMOS25";
227NET "ETH_B_MDC"                   LOC = "AN9"  | IOSTANDARD = "LVCMOS25";
228NET "ETH_B_MDIO"                  LOC = "AL8"  | IOSTANDARD = "LVCMOS25" | PULLUP;
229
230# Common Ethernet Ports
231#   NOTE:  88e1121R has a single reset port for both PHYs, so let Ethernet A do it
232NET "ETH_A_PHY_RST_N"             LOC = "L9"   | IOSTANDARD = "LVCMOS25" | TIG;
233NET "ETH_COMA"                    LOC = "C8"   | IOSTANDARD = "LVCMOS25" | TIG;
234 
235
236# ###############################################
237# Ethernet A Timing
238# ###############################################
239
240INST "*ETH_A*gmii_interface*rxdata_bus[0].delay_rgmii_rxd"           IDELAY_VALUE = 13;
241INST "*ETH_A*gmii_interface*rxdata_bus[1].delay_rgmii_rxd"           IDELAY_VALUE = 13;
242INST "*ETH_A*gmii_interface*rxdata_bus[2].delay_rgmii_rxd"           IDELAY_VALUE = 13;
243INST "*ETH_A*gmii_interface*rxdata_bus[3].delay_rgmii_rxd"           IDELAY_VALUE = 13;
244
245INST "*ETH_A*gmii_interface*delay_rgmii_rx_ctl"                      IDELAY_VALUE = 13;
246
247INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk"                      ODELAY_VALUE = 6;
248INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk"                      SIGNAL_PATTERN = CLOCK;
249
[1918]250# Group all IODELAY-related blocks to use a single IDELAYCTRL
[4647]251INST "ETH_A*dlyctrl"                                                 IODELAY_GROUP = ETH_rgmii_iodelay;
252INST "*ETH_A*gmii_interface*delay_rgmii_rx_ctl"                      IODELAY_GROUP = ETH_rgmii_iodelay;
253INST "*ETH_A*gmii_interface*rxdata_bus[?].delay_rgmii_rxd"           IODELAY_GROUP = ETH_rgmii_iodelay;
254INST "*ETH_A*gmii_interface*delay_rgmii_tx_clk"                      IODELAY_GROUP = ETH_rgmii_iodelay;
[1918]255
[4647]256# Specified Timings: 1.2ns setup time, 1.2ns hold time
257#     The internal PHY delays were not used to derive the OFFSET constraints
258#     This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
259#     Therefore the offset in constraint must have less setup time than nominal
[1918]260NET "ETH_A_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
261NET "ETH_A_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
262
[4647]263#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
264#     Therefore the offset in constraint must have more setup time than nominal
[1918]265NET "ETH_A_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
266NET "ETH_A_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
267
[4647]268#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
269#     Therefore the offset in constraint must have more setup time than nominal
[1918]270NET "ETH_A_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
271NET "ETH_A_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
272
[4647]273#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
274#     Therefore the offset in constraint must have more setup time than nominal
[1918]275NET "ETH_A_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
276NET "ETH_A_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
277
[4647]278#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
279#     Therefore the offset in constraint must have more setup time than nominal
[1918]280NET "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" RISING;
281NET "ETH_A_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC" FALLING;
282
283
[4647]284# ###############################################
285# Ethernet B Timing
286# ###############################################
[1918]287
[4647]288INST "*ETH_B*gmii_interface*rxdata_bus[0].delay_rgmii_rxd"           IDELAY_VALUE = 13;
289INST "*ETH_B*gmii_interface*rxdata_bus[1].delay_rgmii_rxd"           IDELAY_VALUE = 13;
290INST "*ETH_B*gmii_interface*rxdata_bus[2].delay_rgmii_rxd"           IDELAY_VALUE = 13;
291INST "*ETH_B*gmii_interface*rxdata_bus[3].delay_rgmii_rxd"           IDELAY_VALUE = 13;
[1918]292
[4647]293INST "*ETH_B*gmii_interface*delay_rgmii_rx_ctl"                      IDELAY_VALUE = 13;
294
295INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk"                      ODELAY_VALUE = 6;
296INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk"                      SIGNAL_PATTERN = CLOCK;
297
[1918]298# Group all IODELAY-related blocks to use a single IDELAYCTRL
[4647]299# INST "ETH_B*dlyctrl"                                                 IODELAY_GROUP = ETH_rgmii_iodelay;
300INST "*ETH_B*gmii_interface*delay_rgmii_rx_ctl"                      IODELAY_GROUP = ETH_rgmii_iodelay;
301INST "*ETH_B*gmii_interface*rxdata_bus[?].delay_rgmii_rxd"           IODELAY_GROUP = ETH_rgmii_iodelay;
302INST "*ETH_B*gmii_interface*delay_rgmii_tx_clk"                      IODELAY_GROUP = ETH_rgmii_iodelay;
[1918]303
[4647]304# Specified Timings: 1.2ns setup time, 1.2ns hold time
305#     The internal PHY delays were not used to derive the OFFSET constraints
306#     This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock
307#     Therefore the offset in constraint must have less setup time than nominal
[1918]308NET "ETH_B_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
309NET "ETH_B_RGMII_RXD[0]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
310
[4647]311#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock
312#     Therefore the offset in constraint must have more setup time than nominal
[1918]313NET "ETH_B_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
314NET "ETH_B_RGMII_RXD[1]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
315
[4647]316#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock
317#     Therefore the offset in constraint must have more setup time than nominal
[1918]318NET "ETH_B_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
319NET "ETH_B_RGMII_RXD[2]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
320
[4647]321#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock
322#     Therefore the offset in constraint must have more setup time than nominal
[1918]323NET "ETH_B_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
324NET "ETH_B_RGMII_RXD[3]" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
325
[4647]326#     This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock
327#     Therefore the offset in constraint must have more setup time than nominal
[1918]328NET "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" RISING;
329NET "ETH_B_RGMII_RX_CTL" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC" FALLING;
330
331
[4647]332# ###################################################################
333# FPGA DNA Ports
334# ###################################################################
[1918]335
[4647]336NET "*fpga_dna*"                  TIG;
[1918]337
338
[4647]339# ###################################################################
340# DDR Ports
341# ###################################################################
[1918]342
[4647]343# NOTE: DDR3 SO-DIMM constraints are not specified here!
344#       These are pulled automatically from the MIG project during implementation
[1918]345
[4647]346# However, due to a bug in XPS, we need to add this constraint to LOC the IOB
347NET "ddr_parity"                  LOC = "AL31" | IOSTANDARD = "LVCMOS25" | TIG;          # Stray PAD MIG insists on including
[1918]348
349
[4647]350# ###################################################################
351# RFA Ports
352# ###################################################################
[1918]353
[4647]354# AD9963 SPI
355NET "RFA_AD_spi_sclk"             LOC = "AB33" | IOSTANDARD = "LVCMOS25";
356NET "RFA_AD_spi_sdio"             LOC = "AC30" | IOSTANDARD = "LVCMOS25";
357NET "RFA_AD_spi_cs_n"             LOC = "AB31" | IOSTANDARD = "LVCMOS25";
358NET "RFA_AD_reset_n"              LOC = "AA34" | IOSTANDARD = "LVCMOS25";
[1918]359
[4647]360# AD9963
361NET "RFA_AD_TRXD<0>"              LOC = "AC25" | IOSTANDARD = "LVCMOS25";
362NET "RFA_AD_TRXD<1>"              LOC = "AB25" | IOSTANDARD = "LVCMOS25";
363NET "RFA_AD_TRXD<2>"              LOC = "AB32" | IOSTANDARD = "LVCMOS25";
364NET "RFA_AD_TRXD<3>"              LOC = "AC29" | IOSTANDARD = "LVCMOS25";
365NET "RFA_AD_TRXD<4>"              LOC = "AD29" | IOSTANDARD = "LVCMOS25";
366NET "RFA_AD_TRXD<5>"              LOC = "AC33" | IOSTANDARD = "LVCMOS25";
367NET "RFA_AD_TRXD<6>"              LOC = "AD34" | IOSTANDARD = "LVCMOS25";
368NET "RFA_AD_TRXD<7>"              LOC = "AC32" | IOSTANDARD = "LVCMOS25";
369NET "RFA_AD_TRXD<8>"              LOC = "AD31" | IOSTANDARD = "LVCMOS25";
370NET "RFA_AD_TRXD<9>"              LOC = "AD32" | IOSTANDARD = "LVCMOS25";
371NET "RFA_AD_TRXD<10>"             LOC = "AE31" | IOSTANDARD = "LVCMOS25";
372NET "RFA_AD_TRXD<11>"             LOC = "AE32" | IOSTANDARD = "LVCMOS25";
[1918]373
[4647]374NET "RFA_AD_TRXCLK"               LOC = "AD30" | IOSTANDARD = "LVCMOS25";
375NET "RFA_AD_TRXIQ"                LOC = "AC34" | IOSTANDARD = "LVCMOS25";
[1918]376
[4647]377NET "RFA_AD_TXCLK"                LOC = "AA31" | IOSTANDARD = "LVCMOS25";
378NET "RFA_AD_TXIQ"                 LOC = "AA33" | IOSTANDARD = "LVCMOS25";
[1918]379
[4647]380NET "RFA_AD_TXD<0>"               LOC = "AA25" | IOSTANDARD = "LVCMOS25";
381NET "RFA_AD_TXD<1>"               LOC = "AB26" | IOSTANDARD = "LVCMOS25";
382NET "RFA_AD_TXD<2>"               LOC = "Y26"  | IOSTANDARD = "LVCMOS25";
383NET "RFA_AD_TXD<3>"               LOC = "AA26" | IOSTANDARD = "LVCMOS25";
384NET "RFA_AD_TXD<4>"               LOC = "AA28" | IOSTANDARD = "LVCMOS25";
385NET "RFA_AD_TXD<5>"               LOC = "AA29" | IOSTANDARD = "LVCMOS25";
386NET "RFA_AD_TXD<6>"               LOC = "AA30" | IOSTANDARD = "LVCMOS25";
387NET "RFA_AD_TXD<7>"               LOC = "AB30" | IOSTANDARD = "LVCMOS25";
388NET "RFA_AD_TXD<8>"               LOC = "AB28" | IOSTANDARD = "LVCMOS25";
389NET "RFA_AD_TXD<9>"               LOC = "AB27" | IOSTANDARD = "LVCMOS25";
390NET "RFA_AD_TXD<10>"              LOC = "AC28" | IOSTANDARD = "LVCMOS25";
391NET "RFA_AD_TXD<11>"              LOC = "AC27" | IOSTANDARD = "LVCMOS25";
[1918]392
[2382]393
[4647]394# TRXCLK pins driven by AD9963's; assuming 80MHz worst case
395NET "RFA_AD_TRXCLK"               TNM_NET = "RFA_AD_TRXCLK";
396TIMESPEC "TS_RFA_AD_TRXCLK" = PERIOD "RFA_AD_TRXCLK" 80 MHz;
397
398
399# Define relationship of TRXD and TRXCLK, based on AD9963 specs
400#     Using worst-case output delay from AD9963 datasheet table 23
401#     TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window
402#     VALID window below assumes DDR interleaved I/Q at 40MSps rate (12.5nsec / half sample)
403INST "RFA_AD_TRXD<*>"             TNM = "RFA_AD_TRXD_group";
404
405NET "RFA_AD_TRXCLK"               TNM_NET = "RFA_AD_TRXCLK";
[2382]406TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFA_AD_TRXCLK" RISING;
407TIMEGRP "RFA_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFA_AD_TRXCLK" FALLING;
408
[4647]409
410# MAX2829 transceivers and RF front end
411NET "RFA_SPI_SCLK"                LOC = "T34"  | IOSTANDARD = "LVCMOS25";
412NET "RFA_SPI_MOSI"                LOC = "T33"  | IOSTANDARD = "LVCMOS25";
413NET "RFA_SPI_CSn"                 LOC = "U32"  | IOSTANDARD = "LVCMOS25";
414
415NET "RFA_SHDN"                    LOC = "U27"  | IOSTANDARD = "LVCMOS25";
416NET "RFA_TxEn"                    LOC = "T31"  | IOSTANDARD = "LVCMOS25";
417NET "RFA_RxEn"                    LOC = "U33"  | IOSTANDARD = "LVCMOS25";
418NET "RFA_RxHP"                    LOC = "AG32" | IOSTANDARD = "LVCMOS25";
419NET "RFA_PAEn_24"                 LOC = "U25"  | IOSTANDARD = "LVCMOS25";
420NET "RFA_PAEn_5"                  LOC = "U28"  | IOSTANDARD = "LVCMOS25";
421NET "RFA_ANTSW<0>"                LOC = "U31"  | IOSTANDARD = "LVCMOS25";
422NET "RFA_ANTSW<1>"                LOC = "U30"  | IOSTANDARD = "LVCMOS25";
423NET "RFA_LD"                      LOC = "U26"  | IOSTANDARD = "LVCMOS25";
424
425NET "RFA_B<0>"                    LOC = "AG33" | IOSTANDARD = "LVCMOS25";
426NET "RFA_B<1>"                    LOC = "AF31" | IOSTANDARD = "LVCMOS25";
427NET "RFA_B<2>"                    LOC = "AF33" | IOSTANDARD = "LVCMOS25";
428NET "RFA_B<3>"                    LOC = "AG31" | IOSTANDARD = "LVCMOS25";
429NET "RFA_B<4>"                    LOC = "AF34" | IOSTANDARD = "LVCMOS25";
430NET "RFA_B<5>"                    LOC = "AE33" | IOSTANDARD = "LVCMOS25";
431NET "RFA_B<6>"                    LOC = "AE34" | IOSTANDARD = "LVCMOS25";
432
433
434# ###################################################################
435# RFB Ports
436# ###################################################################
437
438# AD9963 SPI
439NET "RFB_AD_spi_sclk"             LOC = "P32"  | IOSTANDARD = "LVCMOS25";
440NET "RFB_AD_spi_sdio"             LOC = "P34"  | IOSTANDARD = "LVCMOS25";
441NET "RFB_AD_spi_cs_n"             LOC = "N32"  | IOSTANDARD = "LVCMOS25";
442NET "RFB_AD_reset_n"              LOC = "N34"  | IOSTANDARD = "LVCMOS25";
443
444# AD9963
445NET "RFB_AD_TRXD<0>"              LOC = "N25"  | IOSTANDARD = "LVCMOS25";
446NET "RFB_AD_TRXD<1>"              LOC = "M25"  | IOSTANDARD = "LVCMOS25";
447NET "RFB_AD_TRXD<2>"              LOC = "N28"  | IOSTANDARD = "LVCMOS25";
448NET "RFB_AD_TRXD<3>"              LOC = "N27"  | IOSTANDARD = "LVCMOS25";
449NET "RFB_AD_TRXD<4>"              LOC = "P29"  | IOSTANDARD = "LVCMOS25";
450NET "RFB_AD_TRXD<5>"              LOC = "M30"  | IOSTANDARD = "LVCMOS25";
451NET "RFB_AD_TRXD<6>"              LOC = "N30"  | IOSTANDARD = "LVCMOS25";
452NET "RFB_AD_TRXD<7>"              LOC = "N29"  | IOSTANDARD = "LVCMOS25";
453NET "RFB_AD_TRXD<8>"              LOC = "P26"  | IOSTANDARD = "LVCMOS25";
454NET "RFB_AD_TRXD<9>"              LOC = "P31"  | IOSTANDARD = "LVCMOS25";
455NET "RFB_AD_TRXD<10>"             LOC = "P25"  | IOSTANDARD = "LVCMOS25";
456NET "RFB_AD_TRXD<11>"             LOC = "P30"  | IOSTANDARD = "LVCMOS25";
457
458NET "RFB_AD_TRXCLK"               LOC = "N33"  | IOSTANDARD = "LVCMOS25";
459NET "RFB_AD_TRXIQ"                LOC = "M33"  | IOSTANDARD = "LVCMOS25";
460
461NET "RFB_AD_TXCLK"                LOC = "L28"  | IOSTANDARD = "LVCMOS25";
462NET "RFB_AD_TXIQ"                 LOC = "L29"  | IOSTANDARD = "LVCMOS25";
463
464NET "RFB_AD_TXD<0>"               LOC = "K32"  | IOSTANDARD = "LVCMOS25";
465NET "RFB_AD_TXD<1>"               LOC = "M26"  | IOSTANDARD = "LVCMOS25";
466NET "RFB_AD_TXD<2>"               LOC = "M32"  | IOSTANDARD = "LVCMOS25";
467NET "RFB_AD_TXD<3>"               LOC = "K34"  | IOSTANDARD = "LVCMOS25";
468NET "RFB_AD_TXD<4>"               LOC = "M31"  | IOSTANDARD = "LVCMOS25";
469NET "RFB_AD_TXD<5>"               LOC = "L30"  | IOSTANDARD = "LVCMOS25";
470NET "RFB_AD_TXD<6>"               LOC = "L33"  | IOSTANDARD = "LVCMOS25";
471NET "RFB_AD_TXD<7>"               LOC = "L31"  | IOSTANDARD = "LVCMOS25";
472NET "RFB_AD_TXD<8>"               LOC = "M28"  | IOSTANDARD = "LVCMOS25";
473NET "RFB_AD_TXD<9>"               LOC = "L34"  | IOSTANDARD = "LVCMOS25";
474NET "RFB_AD_TXD<10>"              LOC = "M27"  | IOSTANDARD = "LVCMOS25";
475NET "RFB_AD_TXD<11>"              LOC = "K31"  | IOSTANDARD = "LVCMOS25";
476
477
478# TRXCLK pins driven by AD9963's; assuming 80MHz worst case
479NET "RFB_AD_TRXCLK"               TNM_NET = "RFB_AD_TRXCLK";
480TIMESPEC "TS_RFB_AD_TRXCLK" = PERIOD "RFB_AD_TRXCLK" 80 MHz;
481
482
483# Define relationship of TRXD and TRXCLK, based on AD9963 specs
484#     Using worst-case output delay from AD9963 datasheet table 23
485#     TRXCLK leads TRXD transition by t_OD2; ad_bridge uses IDELAY to shift this to mid valid window
486#     VALID window below assumes DDR interleaved I/Q at 40MSps rate (12.5nsec / half sample)
487INST "RFB_AD_TRXD<*>"             TNM = "RFB_AD_TRXD_group";
488
489NET "RFB_AD_TRXCLK"               TNM_NET = "RFB_AD_TRXCLK";
[2382]490TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFB_AD_TRXCLK" RISING;
491TIMEGRP "RFB_AD_TRXD_group" OFFSET = IN 0.7 ns VALID 10 ns BEFORE "RFB_AD_TRXCLK" FALLING;
492
493
[4647]494# MAX2829 transceivers and RF front end
495NET "RFB_SPI_SCLK"                LOC = "H34"  | IOSTANDARD = "LVCMOS25";
496NET "RFB_SPI_MOSI"                LOC = "H33"  | IOSTANDARD = "LVCMOS25";
497NET "RFB_SPI_CSn"                 LOC = "J32"  | IOSTANDARD = "LVCMOS25";
[2382]498
[4647]499NET "RFB_SHDN"                    LOC = "J34"  | IOSTANDARD = "LVCMOS25";
500NET "RFB_TxEn"                    LOC = "H32"  | IOSTANDARD = "LVCMOS25";
501NET "RFB_RxEn"                    LOC = "J31"  | IOSTANDARD = "LVCMOS25";
502NET "RFB_RxHP"                    LOC = "R28"  | IOSTANDARD = "LVCMOS25";
503NET "RFB_PAEn_24"                 LOC = "T25"  | IOSTANDARD = "LVCMOS25";
504NET "RFB_PAEn_5"                  LOC = "T28"  | IOSTANDARD = "LVCMOS25";
505NET "RFB_ANTSW<0>"                LOC = "T30"  | IOSTANDARD = "LVCMOS25";
506NET "RFB_ANTSW<1>"                LOC = "T29"  | IOSTANDARD = "LVCMOS25";
507NET "RFB_LD"                      LOC = "K33"  | IOSTANDARD = "LVCMOS25";
[1918]508
[4647]509NET "RFB_B<0>"                    LOC = "P27"  | IOSTANDARD = "LVCMOS25";
510NET "RFB_B<1>"                    LOC = "R27"  | IOSTANDARD = "LVCMOS25";
511NET "RFB_B<2>"                    LOC = "R29"  | IOSTANDARD = "LVCMOS25";
512NET "RFB_B<3>"                    LOC = "R26"  | IOSTANDARD = "LVCMOS25";
513NET "RFB_B<4>"                    LOC = "R32"  | IOSTANDARD = "LVCMOS25";
514NET "RFB_B<5>"                    LOC = "T26"  | IOSTANDARD = "LVCMOS25";
515NET "RFB_B<6>"                    LOC = "R31"  | IOSTANDARD = "LVCMOS25";
[1918]516
[4647]517
518# ###################################################################
519# RFA / RFB RSSI Ports
520# ###################################################################
521
522NET "RF_RSSI_CLK"                 LOC = "B32"  | IOSTANDARD = "LVCMOS25";
523NET "RF_RSSI_PD"                  LOC = "B34"  | IOSTANDARD = "LVCMOS25";
524
525NET "RFA_RSSI_D<0>"               LOC = "E32"  | IOSTANDARD = "LVCMOS25";
526NET "RFA_RSSI_D<1>"               LOC = "E33"  | IOSTANDARD = "LVCMOS25";
527NET "RFA_RSSI_D<2>"               LOC = "E34"  | IOSTANDARD = "LVCMOS25";
528NET "RFA_RSSI_D<3>"               LOC = "F30"  | IOSTANDARD = "LVCMOS25";
529NET "RFA_RSSI_D<4>"               LOC = "F31"  | IOSTANDARD = "LVCMOS25";
530NET "RFA_RSSI_D<5>"               LOC = "F34"  | IOSTANDARD = "LVCMOS25";
531NET "RFA_RSSI_D<6>"               LOC = "F33"  | IOSTANDARD = "LVCMOS25";
532NET "RFA_RSSI_D<7>"               LOC = "G31"  | IOSTANDARD = "LVCMOS25";
533NET "RFA_RSSI_D<8>"               LOC = "G33"  | IOSTANDARD = "LVCMOS25";
534NET "RFA_RSSI_D<9>"               LOC = "G32"  | IOSTANDARD = "LVCMOS25";
535
536NET "RFB_RSSI_D<0>"               LOC = "A33"  | IOSTANDARD = "LVCMOS25";
537NET "RFB_RSSI_D<1>"               LOC = "B33"  | IOSTANDARD = "LVCMOS25";
538NET "RFB_RSSI_D<2>"               LOC = "C33"  | IOSTANDARD = "LVCMOS25";
539NET "RFB_RSSI_D<3>"               LOC = "C34"  | IOSTANDARD = "LVCMOS25";
540NET "RFB_RSSI_D<4>"               LOC = "C32"  | IOSTANDARD = "LVCMOS25";
541NET "RFB_RSSI_D<5>"               LOC = "D31"  | IOSTANDARD = "LVCMOS25";
542NET "RFB_RSSI_D<6>"               LOC = "G30"  | IOSTANDARD = "LVCMOS25";
543NET "RFB_RSSI_D<7>"               LOC = "E31"  | IOSTANDARD = "LVCMOS25";
544NET "RFB_RSSI_D<8>"               LOC = "D32"  | IOSTANDARD = "LVCMOS25";
545NET "RFB_RSSI_D<9>"               LOC = "D34"  | IOSTANDARD = "LVCMOS25";
546
547
548# ###################################################################
549# Floor planning Information
550# ###################################################################
551
552INST "microblaze_0_ilmb"          AREA_GROUP = "MB_Subsystem";
553INST "microblaze_0_dlmb"          AREA_GROUP = "MB_Subsystem";
554INST "microblaze_0"               AREA_GROUP = "MB_Subsystem";
555INST "microblaze_0_i_bram_ctrl"   AREA_GROUP = "MB_Subsystem";
556INST "microblaze_0_d_bram_ctrl"   AREA_GROUP = "MB_Subsystem";
557INST "microblaze_0_bram_block"    AREA_GROUP = "MB_Subsystem";
[4690]558AREA_GROUP "MB_Subsystem"         RANGE      = SLICE_X84Y140:SLICE_X147Y198;
[4647]559
560INST "rfa_iq_rx_buffer_ctrl"      AREA_GROUP = "IQ_Buffers_AB";
561INST "rfa_iq_rx_buffer"           AREA_GROUP = "IQ_Buffers_AB";
562INST "rfa_iq_tx_buffer_ctrl"      AREA_GROUP = "IQ_Buffers_AB";
563INST "rfa_iq_tx_buffer"           AREA_GROUP = "IQ_Buffers_AB";
564INST "rfb_iq_rx_buffer_ctrl"      AREA_GROUP = "IQ_Buffers_AB";
565INST "rfb_iq_rx_buffer"           AREA_GROUP = "IQ_Buffers_AB";
566INST "rfb_iq_tx_buffer_ctrl"      AREA_GROUP = "IQ_Buffers_AB";
567INST "rfb_iq_tx_buffer"           AREA_GROUP = "IQ_Buffers_AB";
568INST "axi_interconnect_buffers"   AREA_GROUP = "IQ_Buffers_AB";
569
570INST "axi_interconnect_core"      AREA_GROUP = "Interconnect_core";
571
572INST "axi_interconnect_dma"       AREA_GROUP = "ETH_Subsystem";
573INST "ETH_A_MAC"                  AREA_GROUP = "ETH_Subsystem";
574INST "ETH_A_DMA"                  AREA_GROUP = "ETH_Subsystem";
575INST "ETH_B_MAC"                  AREA_GROUP = "ETH_Subsystem";
576INST "ETH_B_DMA"                  AREA_GROUP = "ETH_Subsystem";
577
578INST "axi_cdma_0"                 AREA_GROUP = "CDMA";
579
580INST "warplab_buffers"            AREA_GROUP = "WL_BUFFERS";
581
582INST "warplab_agc"                AREA_GROUP = "WL_AGC";
583
584INST "warplab_trigger_proc"       AREA_GROUP = "WL_TRIGGER_PROC";
585
586INST "w3_clock_controller_0"      AREA_GROUP = "CLK_CONTROLLER";
587AREA_GROUP "CLK_CONTROLLER"       RANGE      = RAMB36_X0Y17:RAMB36_X3Y23;
588
589INST "DDR3_SODIMM"                AREA_GROUP = "DDR3_SODIMM";
590AREA_GROUP "DDR3_SODIMM"          RANGE      = SLICE_X52Y40:SLICE_X103Y80, SLICE_X0Y0:SLICE_X143Y39;
591
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