source: ResearchApps/PHY/WARPLAB/WARPLab7/XPS_Reference/w3_4RF/system.mhs

# ##############################################################################
# WARPLab Reference Design
# XPS Hardware Specification (system.mhs)
# Copyright 2013 Mango Communications
# Distributed under the WARP license  (http://warpproject.org/license)
# WARPLab version:  7.5.0
# Family:           virtex6
# Device:           xc6vlx240t
# Package:          ff1156
# Speed Grade:      -1
# ##############################################################################
 PARAMETER VERSION = 2.1.0


# ##############################################################################
# Top Level Ports
# ##############################################################################
 PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1
# USERIO
 PORT userio_pb_d = userio_pb_d, DIR = I
 PORT userio_pb_m = userio_pb_m, DIR = I
 PORT userio_pb_u = userio_pb_u, DIR = I
 PORT userio_leds_green = userio_leds_green, DIR = O, VEC = [3:0]
 PORT userio_leds_red = userio_leds_red, DIR = O, VEC = [3:0]
 PORT userio_dipsw = userio_dipsw, DIR = I, VEC = [3:0]
 PORT userio_hexdisp_left = userio_hexdisp_left, DIR = O, VEC = [6:0]
 PORT userio_hexdisp_right = userio_hexdisp_right, DIR = O, VEC = [6:0]
 PORT userio_hexdisp_left_dp = userio_hexdisp_left_dp, DIR = O
 PORT userio_hexdisp_right_dp = userio_hexdisp_right_dp, DIR = O
 PORT userio_rfa_led_red = userio_rfa_led_red, DIR = O
 PORT userio_rfa_led_green = userio_rfa_led_green, DIR = O
 PORT userio_rfb_led_red = userio_rfb_led_red, DIR = O
 PORT userio_rfb_led_green = userio_rfb_led_green, DIR = O
# Ethernet pins
 PORT ETH_COMA = net_gnd, DIR = O
# ETH_A
 PORT ETH_A_PHY_RST_N = ETH_A_PHY_RST_N, DIR = O
 PORT ETH_A_MDIO = ETH_A_MDIO, DIR = IO
 PORT ETH_A_MDC = ETH_A_MDC, DIR = O
 PORT ETH_A_RGMII_TXC = ETH_A_RGMII_TXC, DIR = O
 PORT ETH_A_RGMII_TX_CTL = ETH_A_RGMII_TX_CTL, DIR = O
 PORT ETH_A_RGMII_TXD = ETH_A_RGMII_TXD, DIR = O, VEC = [3:0]
 PORT ETH_A_RGMII_RXC = ETH_A_RGMII_RXC, DIR = I
 PORT ETH_A_RGMII_RX_CTL = ETH_A_RGMII_RX_CTL, DIR = I
 PORT ETH_A_RGMII_RXD = ETH_A_RGMII_RXD, DIR = I, VEC = [3:0]
 PORT ETH_A_PD = net_gnd, DIR = O
# ETH_B
# PORT ETH_B_PHY_RST_N = ETH_B_PHY_RST_N, DIR = O
 PORT ETH_B_MDIO = ETH_B_MDIO, DIR = IO
 PORT ETH_B_MDC = ETH_B_MDC, DIR = O
 PORT ETH_B_RGMII_TXC = ETH_B_RGMII_TXC, DIR = O
 PORT ETH_B_RGMII_TX_CTL = ETH_B_RGMII_TX_CTL, DIR = O
 PORT ETH_B_RGMII_TXD = ETH_B_RGMII_TXD, DIR = O, VEC = [3:0]
 PORT ETH_B_RGMII_RXC = ETH_B_RGMII_RXC, DIR = I
 PORT ETH_B_RGMII_RX_CTL = ETH_B_RGMII_RX_CTL, DIR = I
 PORT ETH_B_RGMII_RXD = ETH_B_RGMII_RXD, DIR = I, VEC = [3:0]
 PORT ETH_B_PD = net_gnd, DIR = O
# USB UART
 PORT usb_uart_sin = axi_uartlite_0_RX, DIR = I
 PORT usb_uart_sout = uart_tx, DIR = O
# AD9512 clock buffer control pins (RF reference & sampling clocks)
 PORT clk_rfref_spi_cs_n = clk_rfref_spi_cs_n, DIR = O
 PORT clk_rfref_spi_mosi = clk_rfref_spi_mosi, DIR = O
 PORT clk_rfref_spi_sclk = clk_rfref_spi_sclk, DIR = O
 PORT clk_rfref_spi_miso = clk_rfref_spi_miso, DIR = I
 PORT clk_rfref_func = net_vcc, DIR = O
 PORT clk_samp_spi_cs_n = clk_samp_spi_cs_n, DIR = O
 PORT clk_samp_spi_mosi = clk_samp_spi_mosi, DIR = O
 PORT clk_samp_spi_sclk = clk_samp_spi_sclk, DIR = O
 PORT clk_samp_spi_miso = clk_samp_spi_miso, DIR = I
 PORT clk_samp_func = net_vcc, DIR = O
# IIC EEPROM pins
 PORT IIC_EEPROM_iic_scl = IIC_EEPROM_iic_scl, DIR = IO
 PORT IIC_EEPROM_iic_sda = IIC_EEPROM_iic_sda, DIR = IO
 PORT FMC_IIC_EEPROM_scl = FMC_IIC_EEPROM_scl, DIR = IO
 PORT FMC_IIC_EEPROM_sda = FMC_IIC_EEPROM_sda, DIR = IO
# CM-PLL pins
 PORT cm_spi_sclk = cm_spi_sclk, DIR = O
 PORT cm_spi_mosi = cm_spi_mosi, DIR = O
 PORT cm_spi_miso = cm_spi_miso, DIR = I
 PORT cm_spi_cs_n = cm_spi_cs_n, DIR = O
 PORT cm_pll_status = cm_pll_status, DIR = I
 PORT cm_switch = cm_switch, DIR = I, VEC = [2:0]
 PORT pll_refclk_p = pll_refclk, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
 PORT pll_refclk_n = pll_refclk, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
# 80MHz sampling clock from AD9512
 PORT samp_clk_p = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
 PORT samp_clk_n = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
# 200MHz LVDS oscillator input
 PORT osc200_p = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT osc200_n = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
# AD9963 ADC/DAC control pins (RFA & RFB)
 PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n, DIR = O
 PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
 PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk, DIR = O
 PORT RFA_AD_reset_n = RFA_AD_reset_n, DIR = O
 PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n, DIR = O
 PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
 PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk, DIR = O
 PORT RFB_AD_reset_n = RFB_AD_reset_n, DIR = O
# AD9963 ADC/DAC control pins (RFC & RFD = FMC RFA & RFB))
 PORT RFC_AD_spi_cs_n = RFC_AD_spi_cs_n, DIR = O
 PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio, DIR = IO
 PORT RFC_AD_spi_sclk = RFC_AD_spi_sclk, DIR = O
 PORT RFC_AD_reset_n = RFC_AD_reset_n, DIR = O
 PORT RFD_AD_spi_cs_n = RFD_AD_spi_cs_n, DIR = O
 PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio, DIR = IO
 PORT RFD_AD_spi_sclk = RFD_AD_spi_sclk, DIR = O
 PORT RFD_AD_reset_n = RFD_AD_reset_n, DIR = O
# FMC user LEDs (tied directly to radio_controller, not w3_uesrio)
 PORT RFC_led_g = RFC_led_g, DIR = O
 PORT RFC_led_r = RFC_led_r, DIR = O
 PORT RFD_led_g = RFD_led_g, DIR = O
 PORT RFD_led_r = RFD_led_r, DIR = O
# RFA AD pins
 PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
 PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
 PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
 PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
 PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
 PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
# RFB AD pins
 PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
 PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
 PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
 PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
 PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
 PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
# RFC AD pins (FMC RFA)
 PORT RFC_AD_TRXD = RFC_trxd, DIR = I, VEC = [11:0]
 PORT RFC_AD_TRXCLK = RFC_trxclk, DIR = I
 PORT RFC_AD_TRXIQ = RFC_trxiq, DIR = I
 PORT RFC_AD_TXD = RFC_txd, DIR = O, VEC = [11:0]
 PORT RFC_AD_TXIQ = RFC_txiq, DIR = O
 PORT RFC_AD_TXCLK = RFC_txclk, DIR = O
# RFD AD pins (FMC RFB)
 PORT RFD_AD_TRXD = RFD_trxd, DIR = I, VEC = [11:0]
 PORT RFD_AD_TRXCLK = RFD_trxclk, DIR = I
 PORT RFD_AD_TRXIQ = RFD_trxiq, DIR = I
 PORT RFD_AD_TXD = RFD_txd, DIR = O, VEC = [11:0]
 PORT RFD_AD_TXIQ = RFD_txiq, DIR = O
 PORT RFD_AD_TXCLK = RFD_txclk, DIR = O
# On-board RSSI ADC pins
 PORT RFA_RSSI_D = warplab_rfa_rssi, DIR = I, VEC = [9:0]
 PORT RFB_RSSI_D = warplab_rfb_rssi, DIR = I, VEC = [9:0]
 PORT RF_RSSI_CLK = warplab_rssi_clk, DIR = O
 PORT RF_RSSI_PD = net_gnd, DIR = O
# FMC RSSI ADC pins
 PORT RFC_RSSI_D = warplab_rfc_rssi, DIR = I, VEC = [9:0]
 PORT RFD_RSSI_D = warplab_rfd_rssi, DIR = I, VEC = [9:0]
 PORT FMC_RF_RSSI_CLK = warplab_rssi_clk, DIR = O
 PORT FMC_RF_RSSI_PD = net_gnd, DIR = O
# RFA transceiver and front-end
 PORT RFA_TxEn = RFA_TxEn, DIR = O
 PORT RFA_RxEn = RFA_RxEn, DIR = O
 PORT RFA_RxHP = RFA_RxHP, DIR = O
 PORT RFA_SHDN = RFA_SHDN, DIR = O
 PORT RFA_SPI_SCLK = RFA_SPI_SCLK, DIR = O
 PORT RFA_SPI_MOSI = RFA_SPI_MOSI, DIR = O
 PORT RFA_SPI_CSn = RFA_SPI_CSn, DIR = O
 PORT RFA_B = RFA_B, DIR = O, VEC = [0:6]
 PORT RFA_LD = RFA_LD, DIR = I
 PORT RFA_PAEn_24 = RFA_PAEn_24, DIR = O
 PORT RFA_PAEn_5 = RFA_PAEn_5, DIR = O
 PORT RFA_AntSw = RFA_AntSw, DIR = O, VEC = [0:1]
# RFB transceiver and front-end
 PORT RFB_TxEn = RFB_TxEn, DIR = O
 PORT RFB_RxEn = RFB_RxEn, DIR = O
 PORT RFB_RxHP = RFB_RxHP, DIR = O
 PORT RFB_SHDN = RFB_SHDN, DIR = O
 PORT RFB_SPI_SCLK = RFB_SPI_SCLK, DIR = O
 PORT RFB_SPI_MOSI = RFB_SPI_MOSI, DIR = O
 PORT RFB_SPI_CSn = RFB_SPI_CSn, DIR = O
 PORT RFB_B = RFB_B, DIR = O, VEC = [0:6]
 PORT RFB_LD = RFB_LD, DIR = I
 PORT RFB_PAEn_24 = RFB_PAEn_24, DIR = O
 PORT RFB_PAEn_5 = RFB_PAEn_5, DIR = O
 PORT RFB_AntSw = RFB_AntSw, DIR = O, VEC = [0:1]
# RFC transceiver and front-end (FMC RFA)
 PORT RFC_TxEn = RFC_TxEn, DIR = O
 PORT RFC_RxEn = RFC_RxEn, DIR = O
 PORT RFC_RxHP = RFC_RxHP, DIR = O
 PORT RFC_SHDN = RFC_SHDN, DIR = O
 PORT RFC_SPI_SCLK = RFC_SPI_SCLK, DIR = O
 PORT RFC_SPI_MOSI = RFC_SPI_MOSI, DIR = O
 PORT RFC_SPI_CSn = RFC_SPI_CSn, DIR = O
 PORT RFC_B = RFC_B, DIR = O, VEC = [0:6]
 PORT RFC_LD = RFC_LD, DIR = I
 PORT RFC_PAEn_24 = RFC_PAEn_24, DIR = O
 PORT RFC_PAEn_5 = RFC_PAEn_5, DIR = O
 PORT RFC_AntSw = RFC_AntSw, DIR = O, VEC = [0:1]
# RFD transceiver and front-end (FMC RFB)
 PORT RFD_TxEn = RFD_TxEn, DIR = O
 PORT RFD_RxEn = RFD_RxEn, DIR = O
 PORT RFD_RxHP = RFD_RxHP, DIR = O
 PORT RFD_SHDN = RFD_SHDN, DIR = O
 PORT RFD_SPI_SCLK = RFD_SPI_SCLK, DIR = O
 PORT RFD_SPI_MOSI = RFD_SPI_MOSI, DIR = O
 PORT RFD_SPI_CSn = RFD_SPI_CSn, DIR = O
 PORT RFD_B = RFD_B, DIR = O, VEC = [0:6]
 PORT RFD_LD = RFD_LD, DIR = I
 PORT RFD_PAEn_24 = RFD_PAEn_24, DIR = O
 PORT RFD_PAEn_5 = RFD_PAEn_5, DIR = O
 PORT RFD_AntSw = RFD_AntSw, DIR = O, VEC = [0:1]
# DDR
 PORT ddr3_sodimm_ck_p = ddr3_sodimm_ck_p, DIR = O, SIGIS = CLK, VEC = [1:0]
 PORT ddr3_sodimm_ck_n = ddr3_sodimm_ck_n, DIR = O, SIGIS = CLK, VEC = [1:0]
 PORT ddr3_sodimm_cke = ddr3_sodimm_cke, DIR = O
 PORT ddr3_sodimm_cs_n = ddr3_sodimm_cs_n, DIR = O
 PORT ddr3_sodimm_odt = ddr3_sodimm_odt, DIR = O
 PORT ddr3_sodimm_ras_n = ddr3_sodimm_ras_n, DIR = O
 PORT ddr3_sodimm_cas_n = ddr3_sodimm_cas_n, DIR = O
 PORT ddr3_sodimm_we_n = ddr3_sodimm_we_n, DIR = O
 PORT ddr3_sodimm_ba = ddr3_sodimm_ba, DIR = O, VEC = [2:0]
 PORT ddr3_sodimm_addr = ddr3_sodimm_addr, DIR = O, VEC = [14:0]
 PORT ddr3_sodimm_dq = ddr3_sodimm_dq, DIR = IO, VEC = [63:0]
 PORT ddr3_sodimm_dm = ddr3_sodimm_dm, DIR = O, VEC = [7:0]
 PORT ddr3_sodimm_reset_n = ddr3_sodimm_reset_n, DIR = O
 PORT ddr3_sodimm_dqs_p = ddr3_sodimm_dqs_p, DIR = IO, VEC = [7:0]
 PORT ddr3_sodimm_dqs_n = ddr3_sodimm_dqs_n, DIR = IO, VEC = [7:0]
# PORT phy_init_done = ddr3_sodimm_phy_init_done
# Trigger in/out via CM-PLL daisy chain headers
 PORT cm_pll_hdr_in_d = cm_pll_0_in & cm_pll_1_in & cm_pll_2_in & cm_pll_3_in, DIR = I, VEC = [0:3]
 PORT cm_pll_hdr_out_d = cm_pll_0_out & cm_pll_1_out & cm_pll_2_out & cm_pll_3_out, DIR = O, VEC = [0:3]
# Debug Header
 PORT debughdr = debug_capture_running & debug_transmit_running, DIR = O, VEC = [0:1]
 PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [1:0]
 PORT trigger_in = trig_0_in & trig_1_in & trig_2_in & trig_3_in, DIR = I, VEC = [0:3]
 PORT trigger_0_out = trig_2_0_out & trig_3_0_out & trig_4_0_out & trig_5_0_out, DIR = O, VEC = [0:3]
 PORT trigger_1_out = trig_2_1_out & trig_3_1_out & trig_4_1_out & trig_5_1_out, DIR = O, VEC = [0:3]


# ##############################################################################
# Optional Debug Header functionality
# ##############################################################################
# 1) To switch to 6 SW GPIO pins on the Debug Header:
# --- Change above debug_sw_gpio line to:
# PORT debug_sw_gpio = debug_sw_gpio, DIR = IO, VEC = [5:0]
# --- Modify the axi_gpio instance and change C_GPIO_WIDTH to 6 GPIOs
# --- Comment out trigger_1_out
# --- Modify the system.ucf file to use the debug_sw_gpio pins instead of the trigger_1_out pins
# #################
# 2) To probe Ethernet TX/RX using trigger_1_out pins
# --- Change above trigger_1_out line to:
# PORT trigger_1_out = ETH_A_RGMII_TX_CTL & ETH_A_RGMII_RX_CTL & ETH_B_RGMII_TX_CTL & ETH_B_RGMII_RX_CTL, DIR = O, VEC = [0:3]
# ##############################################################################
# Local Cores
# ##############################################################################
BEGIN w3_warplab_trigger_proc_axiw
 PARAMETER INSTANCE = warplab_trigger_proc
 PARAMETER HW_VER = 1.07.g
 PARAMETER C_BASEADDR = 0x10100000
 PARAMETER C_HIGHADDR = 0x1010FFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 0
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 BUS_INTERFACE AXI_STR_ETH_A_RXD = ETH_A_MAC_AXI_STR_RXD
 BUS_INTERFACE AXI_STR_ETH_B_RXD = ETH_B_MAC_AXI_STR_RXD
 PORT axi_aclk = clk_160MHz
 PORT sysgen_clk = clk_160MHz
 PORT agc_done_in = agc_is_done
 PORT rfa_rssi = warplab_rfa_rssi
 PORT rfb_rssi = warplab_rfb_rssi
 PORT rfc_rssi = net_gnd
 PORT rfd_rssi = net_gnd
 PORT rssi_clk = warplab_rssi_clk
# Debug header trigger inputs
 PORT debug_0_in = trig_0_in
 PORT debug_1_in = trig_1_in
 PORT debug_2_in = trig_2_in
 PORT debug_3_in = trig_3_in
# CM-PLL header trigger inputs
 PORT cm_pll_0_in = cm_pll_0_in
 PORT cm_pll_1_in = cm_pll_1_in
 PORT cm_pll_2_in = cm_pll_2_in
 PORT cm_pll_3_in = cm_pll_3_in
# Trigger outputs to internal modules
 PORT trig_0_out = baseband_trigger
 PORT trig_1_out = agc_start
# Trigger outputs to the debug header
 PORT trig_2_0_out = trig_2_0_out
 PORT trig_3_0_out = trig_3_0_out
 PORT trig_4_0_out = trig_4_0_out
 PORT trig_5_0_out = trig_5_0_out
# Replicated trigger outputs to the debug header
 PORT trig_2_1_out = trig_2_1_out
 PORT trig_3_1_out = trig_3_1_out
 PORT trig_4_1_out = trig_4_1_out
 PORT trig_5_1_out = trig_5_1_out
# Replicated trigger outputs to the CM-PLL header
 PORT cm_pll_0_out = cm_pll_0_out
 PORT cm_pll_1_out = cm_pll_1_out
 PORT cm_pll_2_out = cm_pll_2_out
 PORT cm_pll_3_out = cm_pll_3_out
END

BEGIN w3_warplab_agc_axiw
 PARAMETER INSTANCE = warplab_agc
 PARAMETER HW_VER = 3.01.c
 PARAMETER C_BASEADDR = 0x10200000
 PARAMETER C_HIGHADDR = 0x1020FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 PORT AXI_ACLK = clk_160MHz
 PORT sysgen_clk = clk_160MHz
 PORT adc_rx_clk = clk_40MHz
 PORT agc_run = agc_start
 PORT agc_done = agc_is_done
 PORT rfa_agc_rxhp = agc_rxhp_a
 PORT rfa_agc_g_bb = agc_g_bb_a
 PORT rfa_agc_g_rf = agc_g_rf_a
 PORT rfa_rssi = warplab_rfa_rssi
 PORT rfa_rx_i_in = warplab_rfa_Rx_I
 PORT rfa_rx_q_in = warplab_rfa_Rx_Q
 PORT rfa_rx_i_out = dc_filtered_i_a
 PORT rfa_rx_q_out = dc_filtered_q_a
 PORT rfb_agc_rxhp = agc_rxhp_b
 PORT rfb_agc_g_bb = agc_g_bb_b
 PORT rfb_agc_g_rf = agc_g_rf_b
 PORT rfb_rssi = warplab_rfb_rssi
 PORT rfb_rx_i_in = warplab_rfb_Rx_I
 PORT rfb_rx_q_in = warplab_rfb_Rx_Q
 PORT rfb_rx_i_out = dc_filtered_i_b
 PORT rfb_rx_q_out = dc_filtered_q_b
 PORT rfc_agc_rxhp = agc_rxhp_c
 PORT rfc_agc_g_bb = agc_g_bb_c
 PORT rfc_agc_g_rf = agc_g_rf_c
 PORT rfc_rssi = warplab_rfc_rssi
 PORT rfc_rx_i_in = warplab_rfc_Rx_I
 PORT rfc_rx_q_in = warplab_rfc_Rx_Q
 PORT rfc_rx_i_out = dc_filtered_i_c
 PORT rfc_rx_q_out = dc_filtered_q_c
 PORT rfd_agc_rxhp = agc_rxhp_d
 PORT rfd_agc_g_bb = agc_g_bb_d
 PORT rfd_agc_g_rf = agc_g_rf_d
 PORT rfd_rssi = warplab_rfd_rssi
 PORT rfd_rx_i_in = warplab_rfd_Rx_I
 PORT rfd_rx_q_in = warplab_rfd_Rx_Q
 PORT rfd_rx_i_out = dc_filtered_i_d
 PORT rfd_rx_q_out = dc_filtered_q_d
END

BEGIN w3_warplab_buffers_axiw
 PARAMETER INSTANCE = warplab_buffers
 PARAMETER HW_VER = 3.01.h
 PARAMETER C_BASEADDR = 0x10300000
 PARAMETER C_HIGHADDR = 0x1030FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 BUS_INTERFACE RFA_RX_PORTB = w3_warplab_buffers_RFA_RX_PORTB
 BUS_INTERFACE RFA_TX_PORTB = w3_warplab_buffers_RFA_TX_PORTB
 BUS_INTERFACE RFA_RSSI_PORTB = w3_warplab_buffers_RFA_RSSI_PORTB
 BUS_INTERFACE RFB_RX_PORTB = w3_warplab_buffers_RFB_RX_PORTB
 BUS_INTERFACE RFB_TX_PORTB = w3_warplab_buffers_RFB_TX_PORTB
 BUS_INTERFACE RFB_RSSI_PORTB = w3_warplab_buffers_RFB_RSSI_PORTB
 BUS_INTERFACE RFC_RX_PORTB = w3_warplab_buffers_RFC_RX_PORTB
 BUS_INTERFACE RFC_TX_PORTB = w3_warplab_buffers_RFC_TX_PORTB
 BUS_INTERFACE RFC_RSSI_PORTB = w3_warplab_buffers_RFC_RSSI_PORTB
 BUS_INTERFACE RFD_RX_PORTB = w3_warplab_buffers_RFD_RX_PORTB
 BUS_INTERFACE RFD_TX_PORTB = w3_warplab_buffers_RFD_TX_PORTB
 BUS_INTERFACE RFD_RSSI_PORTB = w3_warplab_buffers_RFD_RSSI_PORTB
 PORT AXI_ACLK = clk_160MHz
 PORT sysgen_clk = clk_40MHz
 PORT rssi_adc_clk = warplab_rssi_clk
 PORT DESIGN_VER = 0x00070700
 PORT agc_done = agc_is_done
 PORT rfa_dac_i = warplab_rfa_Tx_I
 PORT rfa_dac_q = warplab_rfa_Tx_Q
 PORT rfa_adc_i = warplab_rfa_Rx_I
 PORT rfa_adc_q = warplab_rfa_Rx_Q
 PORT rfa_agc_filt_i = dc_filtered_i_a
 PORT rfa_agc_filt_q = dc_filtered_q_a
 PORT rfa_rssi = warplab_rfa_rssi
 PORT rfa_g_bb = agc_g_bb_a
 PORT rfa_g_rf = agc_g_rf_a
 PORT rfa_rxhp = agc_rxhp_a
 PORT rfb_dac_i = warplab_rfb_Tx_I
 PORT rfb_dac_q = warplab_rfb_Tx_Q
 PORT rfb_adc_i = warplab_rfb_Rx_I
 PORT rfb_adc_q = warplab_rfb_Rx_Q
 PORT rfb_agc_filt_i = dc_filtered_i_b
 PORT rfb_agc_filt_q = dc_filtered_q_b
 PORT rfb_rssi = warplab_rfb_rssi
 PORT rfb_g_bb = agc_g_bb_b
 PORT rfb_g_rf = agc_g_rf_b
 PORT rfb_rxhp = agc_rxhp_b
 PORT rfc_dac_i = warplab_rfc_Tx_I
 PORT rfc_dac_q = warplab_rfc_Tx_Q
 PORT rfc_adc_i = warplab_rfc_Rx_I
 PORT rfc_adc_q = warplab_rfc_Rx_Q
 PORT rfc_agc_filt_i = dc_filtered_i_c
 PORT rfc_agc_filt_q = dc_filtered_q_c
 PORT rfc_rssi = warplab_rfc_rssi
 PORT rfc_g_bb = agc_g_bb_c
 PORT rfc_g_rf = agc_g_rf_c
 PORT rfc_rxhp = agc_rxhp_c
 PORT rfd_dac_i = warplab_rfd_Tx_I
 PORT rfd_dac_q = warplab_rfd_Tx_Q
 PORT rfd_adc_i = warplab_rfd_Rx_I
 PORT rfd_adc_q = warplab_rfd_Rx_Q
 PORT rfd_agc_filt_i = dc_filtered_i_d
 PORT rfd_agc_filt_q = dc_filtered_q_d
 PORT rfd_rssi = warplab_rfd_rssi
 PORT rfd_g_bb = agc_g_bb_d
 PORT rfd_g_rf = agc_g_rf_d
 PORT rfd_rxhp = agc_rxhp_d
 PORT stoptx = net_gnd
 PORT trigger_in = baseband_trigger
 PORT capture_running = debug_capture_running
 PORT transmit_running = debug_transmit_running
 PORT rf_rx_iq_rssi_int = warplab_buffers_rf_rx_iq_rssi_int
 PORT rf_tx_iq_int = warplab_buffers_rf_tx_iq_int
 PORT dram_init_done = dram_init_done
END

# ##############################################################################
# Mango Cores
# ##############################################################################
BEGIN w3_iic_eeprom_axi
 PARAMETER INSTANCE = w3_iic_eeprom_onBoard
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x20900000
 PARAMETER C_HIGHADDR = 0x2090FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT iic_scl_I = axi_iic_eeprom_scl_I
 PORT iic_scl_O = axi_iic_eeprom_scl_O
 PORT iic_scl_T = axi_iic_eeprom_scl_T
 PORT iic_sda_I = axi_iic_eeprom_sda_I
 PORT iic_sda_O = axi_iic_eeprom_sda_O
 PORT iic_sda_T = axi_iic_eeprom_sda_T
END

BEGIN w3_iic_eeprom_axi
 PARAMETER INSTANCE = w3_iic_eeprom_FMC
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x20A00000
 PARAMETER C_HIGHADDR = 0x20A0FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT iic_scl_io = FMC_IIC_EEPROM_scl
 PORT iic_sda_io = FMC_IIC_EEPROM_sda
END

BEGIN w3_clock_controller_axi
 PARAMETER INSTANCE = w3_clock_controller_0
 PARAMETER HW_VER = 4.00.a
 PARAMETER C_DPHASE_TIMEOUT = 0
 PARAMETER C_BASEADDR = 0x20100000
 PARAMETER C_HIGHADDR = 0x2010FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT samp_spi_cs_n = clk_samp_spi_cs_n
 PORT samp_spi_mosi = clk_samp_spi_mosi
 PORT samp_spi_miso = clk_samp_spi_miso
 PORT samp_spi_sclk = clk_samp_spi_sclk
 PORT samp_func = samp_func
 PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
 PORT rfref_spi_mosi = clk_rfref_spi_mosi
 PORT rfref_spi_miso = clk_rfref_spi_miso
 PORT rfref_spi_sclk = clk_rfref_spi_sclk
 PORT rfref_func = rfref_func
 PORT cm_spi_cs_n = cm_spi_cs_n
 PORT cm_spi_mosi = cm_spi_mosi
 PORT cm_spi_miso = cm_spi_miso
 PORT cm_spi_sclk = cm_spi_sclk
 PORT cm_pll_status = cm_pll_status
 PORT pll_refclk = pll_refclk
 PORT usr_status = net_gnd
 PORT at_boot_clk_in = clk_200MHz
 PORT at_boot_clk_in_valid = clk_gen_1_locked
 PORT at_boot_config_sw = cm_switch
 PORT at_boot_clkbuf_clocks_invalid = mmcm_inputs_invalid
# Communication ports
 PORT uart_tx = clk_cfg_uart_tx
 PORT iic_eeprom_scl_I = clk_cfg_iic_eeprom_scl_I
 PORT iic_eeprom_scl_T = clk_cfg_iic_eeprom_scl_T
 PORT iic_eeprom_scl_O = clk_cfg_iic_eeprom_scl_O
 PORT iic_eeprom_sda_I = clk_cfg_iic_eeprom_sda_I
 PORT iic_eeprom_sda_T = clk_cfg_iic_eeprom_sda_T
 PORT iic_eeprom_sda_O = clk_cfg_iic_eeprom_sda_O
END

BEGIN w3_boot_io_mux
 PARAMETER INSTANCE = boot_io_mux
 PARAMETER HW_VER = 1.00.a
# Mux Control
 PORT iic_sel_a = mmcm_inputs_invalid
 PORT uart_sel_a = mmcm_inputs_invalid
# IOBs
 PORT iic_scl = IIC_EEPROM_iic_scl
 PORT iic_sda = IIC_EEPROM_iic_sda
 PORT uart_tx = uart_tx
# IIC Port A
 PORT iic_scl_I_a = clk_cfg_iic_eeprom_scl_I
 PORT iic_scl_O_a = clk_cfg_iic_eeprom_scl_O
 PORT iic_scl_T_a = clk_cfg_iic_eeprom_scl_T
 PORT iic_sda_I_a = clk_cfg_iic_eeprom_sda_I
 PORT iic_sda_O_a = clk_cfg_iic_eeprom_sda_O
 PORT iic_sda_T_a = clk_cfg_iic_eeprom_sda_T
# IIC Port B
 PORT iic_scl_I_b = axi_iic_eeprom_scl_I
 PORT iic_scl_O_b = axi_iic_eeprom_scl_O
 PORT iic_scl_T_b = axi_iic_eeprom_scl_T
 PORT iic_sda_I_b = axi_iic_eeprom_sda_I
 PORT iic_sda_O_b = axi_iic_eeprom_sda_O
 PORT iic_sda_T_b = axi_iic_eeprom_sda_T
# UART Ports
 PORT uart_tx_a = clk_cfg_uart_tx
 PORT uart_tx_b = axi_uart_tx
END

BEGIN w3_ad_controller_axi
 PARAMETER INSTANCE = w3_ad_controller_0
 PARAMETER HW_VER = 3.02.a
 PARAMETER C_BASEADDR = 0x20400000
 PARAMETER C_HIGHADDR = 0x2040FFFF
 PARAMETER INCLUDE_RFC_RFD_IO = 1
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT RF_AD_TXCLK_out_en = RF_AD_TXCLK_out_en
 PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
 PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
 PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
 PORT RFA_AD_reset_n = RFA_AD_reset_n
 PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
 PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
 PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
 PORT RFB_AD_reset_n = RFB_AD_reset_n
 PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio
 PORT RFC_AD_spi_sclk = RFC_AD_spi_sclk
 PORT RFC_AD_spi_cs_n = RFC_AD_spi_cs_n
 PORT RFC_AD_reset_n = RFC_AD_reset_n
 PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio
 PORT RFD_AD_spi_sclk = RFD_AD_spi_sclk
 PORT RFD_AD_spi_cs_n = RFD_AD_spi_cs_n
 PORT RFD_AD_reset_n = RFD_AD_reset_n
END

BEGIN w3_ad_bridge
 PARAMETER INSTANCE = w3_ad_bridge_onBoard
 PARAMETER HW_VER = 3.01.e
# Clock ports (inputs to w3_ad_bridge)
 PORT sys_samp_clk_Tx = clk_40MHz
 PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
 PORT sys_samp_clk_Rx = clk_40MHz
 PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en
# Top-level AD9963 ports
 PORT ad_RFA_TXD = rfa_txd
 PORT ad_RFA_TXCLK = rfa_txclk
 PORT ad_RFA_TXIQ = rfa_txiq
 PORT ad_RFA_TRXD = rfa_trxd
 PORT ad_RFA_TRXCLK = rfa_trxclk
 PORT ad_RFA_TRXIQ = rfa_trxiq
 PORT ad_RFB_TXD = rfb_txd
 PORT ad_RFB_TXCLK = rfb_txclk
 PORT ad_RFB_TXIQ = rfb_txiq
 PORT ad_RFB_TRXD = rfb_trxd
 PORT ad_RFB_TRXCLK = rfb_trxclk
 PORT ad_RFB_TRXIQ = rfb_trxiq
 PORT user_RFA_TXD_I = warplab_rfa_Tx_I
 PORT user_RFA_TXD_Q = warplab_rfa_Tx_Q
 PORT user_RFA_RXD_I = warplab_rfa_Rx_I
 PORT user_RFA_RXD_Q = warplab_rfa_Rx_Q
 PORT user_RFB_TXD_I = warplab_rfb_Tx_I
 PORT user_RFB_TXD_Q = warplab_rfb_Tx_Q
 PORT user_RFB_RXD_I = warplab_rfb_Rx_I
 PORT user_RFB_RXD_Q = warplab_rfb_Rx_Q
END

BEGIN w3_ad_bridge
 PARAMETER INSTANCE = w3_ad_bridge_FMC
 PARAMETER HW_VER = 3.01.e
# Clock ports (inputs to w3_ad_bridge)
 PORT sys_samp_clk_Tx = clk_40MHz
 PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
 PORT sys_samp_clk_Rx = clk_40MHz
 PORT ad_TXCLK_out_en = RF_AD_TXCLK_out_en
# Top-level AD9963 ports
 PORT ad_RFA_TXD = rfc_txd
 PORT ad_RFA_TXCLK = rfc_txclk
 PORT ad_RFA_TXIQ = rfc_txiq
 PORT ad_RFA_TRXD = rfc_trxd
 PORT ad_RFA_TRXCLK = rfc_trxclk
 PORT ad_RFA_TRXIQ = rfc_trxiq
 PORT ad_RFB_TXD = rfd_txd
 PORT ad_RFB_TXCLK = rfd_txclk
 PORT ad_RFB_TXIQ = rfd_txiq
 PORT ad_RFB_TRXD = rfd_trxd
 PORT ad_RFB_TRXCLK = rfd_trxclk
 PORT ad_RFB_TRXIQ = rfd_trxiq
 PORT user_RFA_TXD_I = warplab_rfc_Tx_I
 PORT user_RFA_TXD_Q = warplab_rfc_Tx_Q
 PORT user_RFA_RXD_I = warplab_rfc_Rx_I
 PORT user_RFA_RXD_Q = warplab_rfc_Rx_Q
 PORT user_RFB_TXD_I = warplab_rfd_Tx_I
 PORT user_RFB_TXD_Q = warplab_rfd_Tx_Q
 PORT user_RFB_RXD_I = warplab_rfd_Rx_I
 PORT user_RFB_RXD_Q = warplab_rfd_Rx_Q
END

BEGIN w3_userio_axi
 PARAMETER INSTANCE = W3_USERIO
 PARAMETER HW_VER = 1.01.a
 PARAMETER C_BASEADDR = 0x20200000
 PARAMETER C_HIGHADDR = 0x2020FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT leds_red = userio_leds_red
 PORT leds_green = userio_leds_green
 PORT hexdisp_left = userio_hexdisp_left
 PORT hexdisp_right = userio_hexdisp_right
 PORT hexdisp_left_dp = userio_hexdisp_left_dp
 PORT hexdisp_right_dp = userio_hexdisp_right_dp
 PORT rfa_led_red = userio_rfa_led_red
 PORT rfa_led_green = userio_rfa_led_green
 PORT rfb_led_red = userio_rfb_led_red
 PORT rfb_led_green = userio_rfb_led_green
 PORT dipsw = userio_dipsw
 PORT pb_u = userio_pb_u
 PORT pb_m = userio_pb_m
 PORT pb_d = userio_pb_d
 PORT usr_rfa_led_red = RFA_statLED_Rx
 PORT usr_rfa_led_green = RFA_statLED_Tx
 PORT usr_rfb_led_red = RFB_statLED_Rx
 PORT usr_rfb_led_green = RFB_statLED_Tx
 PORT DNA_Port_Clk = clk_40MHz
END

BEGIN radio_controller_axi
 PARAMETER INSTANCE = radio_controller_0
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_BASEADDR = 0x20300000
 PARAMETER C_HIGHADDR = 0x2030FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
# RFA
 PORT RFA_TxEn = RFA_TxEn
 PORT RFA_RxEn = RFA_RxEn
 PORT RFA_RxHP = RFA_RxHP
 PORT RFA_SHDN = RFA_SHDN
 PORT RFA_SPI_SCLK = RFA_SPI_SCLK
 PORT RFA_SPI_MOSI = RFA_SPI_MOSI
 PORT RFA_SPI_CSn = RFA_SPI_CSn
 PORT RFA_B = RFA_B
 PORT RFA_LD = RFA_LD
 PORT RFA_PAEn_24 = RFA_PAEn_24
 PORT RFA_PAEn_5 = RFA_PAEn_5
 PORT RFA_AntSw = RFA_AntSw
# RFA - User ports
 PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
 PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
 PORT usr_RFA_RxHP = agc_rxhp_a
 PORT usr_RFA_RxGainRF = agc_g_rf_a
 PORT usr_RFA_RxGainBB = agc_g_bb_a
# RFB
 PORT RFB_TxEn = RFB_TxEn
 PORT RFB_RxEn = RFB_RxEn
 PORT RFB_RxHP = RFB_RxHP
 PORT RFB_SHDN = RFB_SHDN
 PORT RFB_SPI_SCLK = RFB_SPI_SCLK
 PORT RFB_SPI_MOSI = RFB_SPI_MOSI
 PORT RFB_SPI_CSn = RFB_SPI_CSn
 PORT RFB_B = RFB_B
 PORT RFB_LD = RFB_LD
 PORT RFB_PAEn_24 = RFB_PAEn_24
 PORT RFB_PAEn_5 = RFB_PAEn_5
 PORT RFB_AntSw = RFB_AntSw
# RFB - User ports
 PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
 PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
 PORT usr_RFB_RxHP = agc_rxhp_b
 PORT usr_RFB_RxGainRF = agc_g_rf_b
 PORT usr_RFB_RxGainBB = agc_g_bb_b
# RFC
 PORT RFC_TxEn = RFC_TxEn
 PORT RFC_RxEn = RFC_RxEn
 PORT RFC_RxHP = RFC_RxHP
 PORT RFC_SHDN = RFC_SHDN
 PORT RFC_SPI_SCLK = RFC_SPI_SCLK
 PORT RFC_SPI_MOSI = RFC_SPI_MOSI
 PORT RFC_SPI_CSn = RFC_SPI_CSn
 PORT RFC_B = RFC_B
 PORT RFC_LD = RFC_LD
 PORT RFC_PAEn_24 = RFC_PAEn_24
 PORT RFC_PAEn_5 = RFC_PAEn_5
 PORT RFC_AntSw = RFC_AntSw
# RFC - User ports
 PORT usr_RFC_statLED_Tx = RFC_led_g
 PORT usr_RFC_statLED_Rx = RFC_led_r
 PORT usr_RFC_RxHP = agc_rxhp_c
 PORT usr_RFC_RxGainRF = agc_g_rf_c
 PORT usr_RFC_RxGainBB = agc_g_bb_c
# RFD
 PORT RFD_TxEn = RFD_TxEn
 PORT RFD_RxEn = RFD_RxEn
 PORT RFD_RxHP = RFD_RxHP
 PORT RFD_SHDN = RFD_SHDN
 PORT RFD_SPI_SCLK = RFD_SPI_SCLK
 PORT RFD_SPI_MOSI = RFD_SPI_MOSI
 PORT RFD_SPI_CSn = RFD_SPI_CSn
 PORT RFD_B = RFD_B
 PORT RFD_LD = RFD_LD
 PORT RFD_PAEn_24 = RFD_PAEn_24
 PORT RFD_PAEn_5 = RFD_PAEn_5
 PORT RFD_AntSw = RFD_AntSw
# RFD - User ports
 PORT usr_RFD_statLED_Tx = RFD_led_g
 PORT usr_RFD_statLED_Rx = RFD_led_r
 PORT usr_RFD_RxHP = agc_rxhp_d
 PORT usr_RFD_RxGainRF = agc_g_rf_d
 PORT usr_RFD_RxGainBB = agc_g_bb_d
END

# ##############################################################################
# Buffer core memories
# ##############################################################################
# RFA
BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfa_iq_rx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41000000
 PARAMETER C_S_AXI_HIGHADDR = 0x4101FFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_0
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfa_iq_rx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_0
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFA_RX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfa_rssi_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41020000
 PARAMETER C_S_AXI_HIGHADDR = 0x41023FFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_1
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfa_rssi_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_1
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFA_RSSI_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfa_iq_tx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41040000
 PARAMETER C_S_AXI_HIGHADDR = 0x4105FFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_2
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfa_iq_tx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_2
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFA_TX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

# RFB
BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfb_iq_rx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41080000
 PARAMETER C_S_AXI_HIGHADDR = 0x4109FFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_3
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfb_iq_rx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_3
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFB_RX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfb_rssi_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x410A0000
 PARAMETER C_S_AXI_HIGHADDR = 0x410A3FFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_4
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfb_rssi_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_4
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFB_RSSI_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfb_iq_tx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x410C0000
 PARAMETER C_S_AXI_HIGHADDR = 0x410DFFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_5
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfb_iq_tx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_5
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFB_TX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

# RFC
BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfc_iq_rx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41100000
 PARAMETER C_S_AXI_HIGHADDR = 0x4111FFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_6
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfc_iq_rx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_6
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFC_RX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfc_rssi_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41120000
 PARAMETER C_S_AXI_HIGHADDR = 0x41123FFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_7
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfc_rssi_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_7
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFC_RSSI_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfc_iq_tx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41140000
 PARAMETER C_S_AXI_HIGHADDR = 0x4115FFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_8
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfc_iq_tx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_8
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFC_TX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

# RFD
BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfd_iq_rx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x41180000
 PARAMETER C_S_AXI_HIGHADDR = 0x4119FFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_9
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfd_iq_rx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_9
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFD_RX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfd_rssi_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x411A0000
 PARAMETER C_S_AXI_HIGHADDR = 0x411A3FFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_10
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfd_rssi_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_10
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFD_RSSI_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = rfd_iq_tx_buffer_ctrl
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi2axi_connector_1.M_AXI
 PARAMETER C_S_AXI_BASEADDR = 0x411C0000
 PARAMETER C_S_AXI_HIGHADDR = 0x411DFFFF
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_SINGLE_PORT_BRAM = 1
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_buffers
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA_11
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN bram_block
 PARAMETER INSTANCE = rfd_iq_tx_buffer
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA_11
 BUS_INTERFACE PORTB = w3_warplab_buffers_RFD_TX_PORTB
 PORT BRAM_Clk_B = clk_40MHz
END

# ##############################################################################
# Clock / Reset
# ##############################################################################
BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER HW_VER = 3.00.a
 PARAMETER C_EXT_RESET_HIGH = 1
 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT Dcm_locked = clk_gen_all_locked
 PORT MB_Reset = proc_sys_reset_0_MB_Reset
 PORT Slowest_sync_clk = clk_40MHz
 PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn
 PORT Ext_Reset_In = RESET
 PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_asyncClks
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
# 200MHz clock input (driven by 200MHz LVDS oscillator)
 PARAMETER C_CLKIN_FREQ = 200000000
# TEMAC TxClk
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT0_BUF = TRUE
# IDELAYCTRL refclk
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = NONE
 PARAMETER C_CLKOUT1_BUF = TRUE
 PORT CLKIN = osc200_in
 PORT CLKOUT0 = clk_125MHz
 PORT CLKOUT1 = clk_200MHz
 PORT RST = RESET
 PORT LOCKED = clk_gen_1_locked
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_ProcBusSamp_Clocks
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
# 80MHz clock input (driven by AD9512 for sampling clock)
 PARAMETER C_CLKIN_FREQ = 80000000
# 2x Sampling clock 0 deg phase
 PARAMETER C_CLKOUT0_FREQ = 80000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
# MB and primary PLB
 PARAMETER C_CLKOUT1_FREQ = 160000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
# Sampling clock 0 deg phase
 PARAMETER C_CLKOUT2_FREQ = 40000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT2_BUF = TRUE
# Sampling clock 90 deg phase
 PARAMETER C_CLKOUT3_FREQ = 40000000
 PARAMETER C_CLKOUT3_PHASE = 90
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PORT CLKIN = ad_refclk_in
 PORT CLKOUT0 = clk_80MHz
 PORT CLKOUT1 = clk_160MHz
 PORT CLKOUT2 = clk_40MHz
 PORT CLKOUT3 = clk_40MHz_90degphase
 PORT RST = mmcm_inputs_invalid
 PORT LOCKED = clk_gen_0_locked
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_MPMC_Clocks
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
# 80MHz clock input (driven by other clock generator)
 PARAMETER C_CLKIN_FREQ = 80000000
# MPMC DRAM clock (2x bus)
 PARAMETER C_CLKOUT0_FREQ = 320000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
# MPMC DRAM clock (2x bus, variable phase)
 PARAMETER C_CLKOUT1_FREQ = 320000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT1_VARIABLE_PHASE = TRUE
 PARAMETER C_PSDONE_GROUP = MMCM0
 PORT CLKIN = clk_80MHz
 PORT PSCLK = clk_80MHz
 PORT RST = mmcm_inputs_invalid
 PORT LOCKED = clk_gen_2_locked
 PORT CLKOUT0 = clock_generator_MPMC_Clocks_CLKOUT0
 PORT CLKOUT1 = clock_generator_MPMC_Clocks_CLKOUT1
 PORT PSEN = MMCM_PSEN
 PORT PSINCDEC = MMCM_PSINCDEC
 PORT PSDONE = clock_generator_MPMC_Clocks_PSDONE
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = clk_gen_locked_AND
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = AND
 PARAMETER C_SIZE = 3
 PORT Op1 = clk_gen_0_locked & clk_gen_1_locked & clk_gen_2_locked
 PORT Res = clk_gen_all_locked
END

# ##############################################################################
# Microblaze
# ##############################################################################
BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER HW_VER = 8.40.b
 PARAMETER C_INTERCONNECT = 2
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER C_USE_DCACHE = 1
 PARAMETER C_USE_ICACHE = 0
# Little endian
 PARAMETER C_ENDIANNESS = 1
# MMU Settings
 PARAMETER C_USE_MMU = 0
 PARAMETER C_M_AXI_D_BUS_EXCEPTION = 1
 PARAMETER C_ILL_OPCODE_EXCEPTION = 1
 PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 PARAMETER C_OPCODE_0x0_ILLEGAL = 1
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_PVR = 2
 PARAMETER C_INTERCONNECT_M_AXI_DC_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_DC_B_REGISTER = 1
 PARAMETER C_NUMBER_OF_PC_BRK = 4
 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 2
 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 2
 PARAMETER C_CACHE_BYTE_SIZE = 128
 PARAMETER C_ICACHE_BASEADDR = 0x80000000
 PARAMETER C_ICACHE_HIGHADDR = 0xffffffff
 PARAMETER C_ICACHE_ALWAYS_USED = 1
 PARAMETER C_DCACHE_BYTE_SIZE = 128
 PARAMETER C_DCACHE_BASEADDR = 0x80000000
 PARAMETER C_DCACHE_HIGHADDR = 0xffffffff
 PARAMETER C_DCACHE_ALWAYS_USED = 1
 PARAMETER C_STREAM_INTERCONNECT = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_IC_B_REGISTER = 1
 PARAMETER C_ICACHE_FORCE_TAG_LUTRAM = 0
 PARAMETER C_DCACHE_FORCE_TAG_LUTRAM = 0
 PARAMETER C_USE_STACK_PROTECTION = 1
 PARAMETER C_INTERCONNECT_M_AXI_DP_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_DP_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_DP_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_DP_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_DP_B_REGISTER = 0
 BUS_INTERFACE DEBUG = microblaze_0_debug
 BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
 BUS_INTERFACE M_AXI_DP = axi_interconnect_periph_160
 BUS_INTERFACE DLMB = microblaze_0_dlmb
 BUS_INTERFACE ILMB = microblaze_0_ilmb
 BUS_INTERFACE M_AXI_DC = axi_interconnect_core
 PORT MB_RESET = proc_sys_reset_0_MB_Reset
 PORT CLK = clk_160MHz
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_ilmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_160MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_i_bram_ctrl
 PARAMETER HW_VER = 3.10.c
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0001ffff
 BUS_INTERFACE SLMB = microblaze_0_ilmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN lmb_v10
 PARAMETER INSTANCE = microblaze_0_dlmb
 PARAMETER HW_VER = 2.00.b
 PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET
 PORT LMB_CLK = clk_160MHz
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = microblaze_0_d_bram_ctrl
 PARAMETER HW_VER = 3.10.c
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0001ffff
 BUS_INTERFACE SLMB = microblaze_0_dlmb
 BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN bram_block
 PARAMETER INSTANCE = microblaze_0_bram_block
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block
 BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block
END

BEGIN mdm
 PARAMETER INSTANCE = debug_module
 PARAMETER HW_VER = 2.10.a
 PARAMETER C_USE_UART = 0
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug
 PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst
 PORT S_AXI_ACLK = clk_80MHz
 PORT Interrupt = debug_module_Interrupt
END

# ##############################################################################
# Peripherals
# ##############################################################################
BEGIN axi_uartlite
 PARAMETER INSTANCE = usb_uart
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_BASEADDR = 0x20800000
 PARAMETER C_HIGHADDR = 0x2080FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT RX = axi_uartlite_0_RX
 PORT TX = axi_uart_tx
 PORT Interrupt = usb_uart_Interrupt
END

BEGIN axi_timer
 PARAMETER INSTANCE = axi_timer_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x20700000
 PARAMETER C_HIGHADDR = 0x2070FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT Interrupt = axi_timer_0_Interrupt
END

BEGIN axi_sysmon_adc
 PARAMETER INSTANCE = axi_sysmon_adc_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_INCLUDE_INTR = 1
 PARAMETER C_BASEADDR = 0x20600000
 PARAMETER C_HIGHADDR = 0x2060FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT VAUXP = net_gnd
 PORT VAUXN = net_gnd
 PORT CONVST = net_gnd
 PORT IP2INTC_Irpt = axi_sysmon_adc_0_IP2INTC_Irpt
END

BEGIN axi_gpio
 PARAMETER INSTANCE = axi_gpio_0
 PARAMETER HW_VER = 1.01.b
# PARAMETER C_GPIO_WIDTH = 6
 PARAMETER C_GPIO_WIDTH = 2
 PARAMETER C_TRI_DEFAULT = 0x00000000
 PARAMETER C_BASEADDR = 0x20500000
 PARAMETER C_HIGHADDR = 0x2050FFFF
 BUS_INTERFACE S_AXI = axi_interconnect_periph_80
 PORT S_AXI_ACLK = clk_80MHz
 PORT GPIO_IO = debug_sw_gpio
END

BEGIN axi_intc
 PARAMETER INSTANCE = axi_intc_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_BASEADDR = 0x10000000
 PARAMETER C_HIGHADDR = 0x1000FFFF
 BUS_INTERFACE INTERRUPT = axi_intc_0_INTERRUPT
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 PORT Intr = usb_uart_Interrupt & ETH_B_DMA_s2mm_introut & ETH_B_DMA_mm2s_introut & ETH_B_MAC_INTERRUPT & ETH_A_DMA_s2mm_introut & ETH_A_DMA_mm2s_introut & ETH_A_MAC_INTERRUPT & warplab_buffers_rf_tx_iq_int & warplab_buffers_rf_rx_iq_rssi_int & axi_cdma_0_cdma_introut & axi_timer_0_Interrupt
 PORT S_AXI_ACLK = clk_160MHz
END

BEGIN axi_cdma
 PARAMETER INSTANCE = axi_cdma_0
 PARAMETER HW_VER = 3.04.a
 PARAMETER C_ENABLE_KEYHOLE = 0
 PARAMETER C_M_AXI_DATA_WIDTH = 128
 PARAMETER C_BASEADDR = 0x12000000
 PARAMETER C_HIGHADDR = 0x1200FFFF
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_B_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 1
 PARAMETER C_INCLUDE_SG = 1
 PARAMETER C_M_AXI_MAX_BURST_LEN = 64
 BUS_INTERFACE M_AXI = axi_interconnect_core
 BUS_INTERFACE M_AXI_SG = axi_interconnect_core
 BUS_INTERFACE S_AXI_LITE = axi_interconnect_periph_160
 PORT s_axi_lite_aclk = clk_160MHz
 PORT m_axi_aclk = clk_160MHz
 PORT cdma_introut = axi_cdma_0_cdma_introut
END

BEGIN bram_block
 PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block_1
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA
 BUS_INTERFACE PORTB = axi_bram_ctrl_0_BRAM_PORTB
END

BEGIN axi_bram_ctrl
 PARAMETER INSTANCE = axi_bram_0
 PARAMETER HW_VER = 1.03.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi_cdma_0.M_AXI_SG & axi_cdma_0.M_AXI & axi2axi_connector_2.M_AXI & axi2axi_connector_3.M_AXI & axi2axi_connector_4.M_AXI
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_INTERCONNECT_S_AXI_WRITE_ACCEPTANCE = 4
 PARAMETER C_INTERCONNECT_S_AXI_READ_ACCEPTANCE = 4
 PARAMETER C_S_AXI_BASEADDR = 0x50000000
 PARAMETER C_S_AXI_HIGHADDR = 0x5001FFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_core
 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA
 BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_BRAM_PORTB
 PORT S_AXI_ACLK = clk_160MHz
END

# ##############################################################################
# Ethernet / Ethernet DMAs
# ##############################################################################
BEGIN axi_ethernet
 PARAMETER INSTANCE = ETH_A_MAC
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_PHYADDR = 0B00110
 PARAMETER C_INCLUDE_IO = 1
 PARAMETER C_TYPE = 2
 PARAMETER C_PHY_TYPE = 3
 PARAMETER C_HALFDUP = 0
 PARAMETER C_TXMEM = 16384
 PARAMETER C_RXMEM = 16384
 PARAMETER C_TXCSUM = 2
 PARAMETER C_RXCSUM = 2
 PARAMETER C_TXVLAN_TRAN = 0
 PARAMETER C_RXVLAN_TRAN = 0
 PARAMETER C_TXVLAN_TAG = 0
 PARAMETER C_RXVLAN_TAG = 0
 PARAMETER C_TXVLAN_STRP = 0
 PARAMETER C_RXVLAN_STRP = 0
 PARAMETER C_MCAST_EXTEND = 0
 PARAMETER C_STATS = 0
 PARAMETER C_AVB = 0
 PARAMETER C_BASEADDR = 0x11000000
 PARAMETER C_HIGHADDR = 0x1103FFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 0
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 BUS_INTERFACE AXI_STR_RXD = ETH_A_MAC_AXI_STR_RXD
 BUS_INTERFACE AXI_STR_RXS = ETH_A_MAC_AXI_STR_RXS
 BUS_INTERFACE AXI_STR_TXC = ETH_A_DMA_M_AXIS_MM2S_CNTRL
 BUS_INTERFACE AXI_STR_TXD = ETH_A_DMA_M_AXIS_MM2S
 PORT S_AXI_ACLK = clk_160MHz
 PORT GTX_CLK = clk_125MHz
 PORT PHY_RST_N = ETH_A_PHY_RST_N
 PORT MDIO = ETH_A_MDIO
 PORT MDC = ETH_A_MDC
 PORT REF_CLK = clk_200MHz
 PORT AXI_STR_TXD_ACLK = clk_160MHz
 PORT AXI_STR_TXC_ACLK = clk_160MHz
 PORT AXI_STR_RXD_ACLK = clk_160MHz
 PORT AXI_STR_RXS_ACLK = clk_160MHz
 PORT AXI_STR_RXS_TREADY = net_vcc
 PORT RGMII_TXD = ETH_A_RGMII_TXD
 PORT RGMII_TX_CTL = ETH_A_RGMII_TX_CTL
 PORT RGMII_TXC = ETH_A_RGMII_TXC
 PORT RGMII_RXD = ETH_A_RGMII_RXD
 PORT RGMII_RX_CTL = ETH_A_RGMII_RX_CTL
 PORT RGMII_RXC = ETH_A_RGMII_RXC
 PORT INTERRUPT = ETH_A_MAC_INTERRUPT
END

BEGIN axi_dma
 PARAMETER INSTANCE = ETH_A_DMA
 PARAMETER HW_VER = 6.03.a
 PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
 PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
 PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
 PARAMETER C_BASEADDR = 0x11200000
 PARAMETER C_HIGHADDR = 0x1120FFFF
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 0
 BUS_INTERFACE S_AXI_LITE = axi_interconnect_periph_160
 BUS_INTERFACE M_AXI_SG = axi_interconnect_dma
 BUS_INTERFACE M_AXI_MM2S = axi_interconnect_dma
 BUS_INTERFACE M_AXI_S2MM = axi_interconnect_dma
 BUS_INTERFACE S_AXIS_S2MM = ETH_A_MAC_AXI_STR_RXD
 BUS_INTERFACE S_AXIS_S2MM_STS = ETH_A_MAC_AXI_STR_RXS
 BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETH_A_DMA_M_AXIS_MM2S_CNTRL
 BUS_INTERFACE M_AXIS_MM2S = ETH_A_DMA_M_AXIS_MM2S
 PORT s_axi_lite_aclk = clk_160MHz
 PORT m_axi_sg_aclk = clk_160MHz
 PORT m_axi_mm2s_aclk = clk_160MHz
 PORT m_axi_s2mm_aclk = clk_160MHz
 PORT mm2s_introut = ETH_A_DMA_mm2s_introut
 PORT s2mm_introut = ETH_A_DMA_s2mm_introut
END

BEGIN axi_ethernet
 PARAMETER INSTANCE = ETH_B_MAC
 PARAMETER HW_VER = 3.01.a
 PARAMETER C_PHYADDR = 0B00111
 PARAMETER C_INCLUDE_IO = 1
 PARAMETER C_TYPE = 2
 PARAMETER C_PHY_TYPE = 3
 PARAMETER C_HALFDUP = 0
 PARAMETER C_TXMEM = 16384
 PARAMETER C_RXMEM = 16384
 PARAMETER C_TXCSUM = 2
 PARAMETER C_RXCSUM = 2
 PARAMETER C_TXVLAN_TRAN = 0
 PARAMETER C_RXVLAN_TRAN = 0
 PARAMETER C_TXVLAN_TAG = 0
 PARAMETER C_RXVLAN_TAG = 0
 PARAMETER C_TXVLAN_STRP = 0
 PARAMETER C_RXVLAN_STRP = 0
 PARAMETER C_MCAST_EXTEND = 0
 PARAMETER C_STATS = 0
 PARAMETER C_AVB = 0
 PARAMETER C_BASEADDR = 0x11100000
 PARAMETER C_HIGHADDR = 0x1113FFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 0
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 BUS_INTERFACE AXI_STR_RXD = ETH_B_MAC_AXI_STR_RXD
 BUS_INTERFACE AXI_STR_RXS = ETH_B_MAC_AXI_STR_RXS
 BUS_INTERFACE AXI_STR_TXC = ETH_B_DMA_M_AXIS_MM2S_CNTRL
 BUS_INTERFACE AXI_STR_TXD = ETH_B_DMA_M_AXIS_MM2S
 PORT S_AXI_ACLK = clk_160MHz
 PORT GTX_CLK = clk_125MHz
# PORT PHY_RST_N = ETH_B_PHY_RST_N #88e1121R has single reset port; let ETH_A handle it
 PORT MDIO = ETH_B_MDIO
 PORT MDC = ETH_B_MDC
 PORT REF_CLK = clk_200MHz
 PORT AXI_STR_TXD_ACLK = clk_160MHz
 PORT AXI_STR_TXC_ACLK = clk_160MHz
 PORT AXI_STR_RXD_ACLK = clk_160MHz
 PORT AXI_STR_RXS_ACLK = clk_160MHz
 PORT AXI_STR_RXS_TREADY = net_vcc
 PORT RGMII_TXD = ETH_B_RGMII_TXD
 PORT RGMII_TX_CTL = ETH_B_RGMII_TX_CTL
 PORT RGMII_TXC = ETH_B_RGMII_TXC
 PORT RGMII_RXD = ETH_B_RGMII_RXD
 PORT RGMII_RX_CTL = ETH_B_RGMII_RX_CTL
 PORT RGMII_RXC = ETH_B_RGMII_RXC
 PORT INTERRUPT = ETH_B_MAC_INTERRUPT
END

BEGIN axi_dma
 PARAMETER INSTANCE = ETH_B_DMA
 PARAMETER HW_VER = 6.03.a
 PARAMETER C_SG_INCLUDE_DESC_QUEUE = 1
 PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
 PARAMETER C_M_AXI_S2MM_DATA_WIDTH = 64
 PARAMETER C_BASEADDR = 0x11300000
 PARAMETER C_HIGHADDR = 0x1130FFFF
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_S_AXI_LITE_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_SG_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_MM2S_B_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_AW_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_AR_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_W_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_R_REGISTER = 0
 PARAMETER C_INTERCONNECT_M_AXI_S2MM_B_REGISTER = 0
 BUS_INTERFACE S_AXI_LITE = axi_interconnect_periph_160
 BUS_INTERFACE M_AXI_SG = axi_interconnect_dma
 BUS_INTERFACE M_AXI_MM2S = axi_interconnect_dma
 BUS_INTERFACE M_AXI_S2MM = axi_interconnect_dma
 BUS_INTERFACE S_AXIS_S2MM = ETH_B_MAC_AXI_STR_RXD
 BUS_INTERFACE S_AXIS_S2MM_STS = ETH_B_MAC_AXI_STR_RXS
 BUS_INTERFACE M_AXIS_MM2S_CNTRL = ETH_B_DMA_M_AXIS_MM2S_CNTRL
 BUS_INTERFACE M_AXIS_MM2S = ETH_B_DMA_M_AXIS_MM2S
 PORT s_axi_lite_aclk = clk_160MHz
 PORT m_axi_sg_aclk = clk_160MHz
 PORT m_axi_mm2s_aclk = clk_160MHz
 PORT m_axi_s2mm_aclk = clk_160MHz
 PORT mm2s_introut = ETH_B_DMA_mm2s_introut
 PORT s2mm_introut = ETH_B_DMA_s2mm_introut
END

# ##############################################################################
# DDR
# ##############################################################################
BEGIN axi_v6_ddrx
 PARAMETER INSTANCE = DDR3_SODIMM
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
 PARAMETER C_CK_WIDTH = 2
 PARAMETER C_ROW_WIDTH = 15
 PARAMETER C_MMCM_EXT_LOC = MMCM_ADV_X0Y0
# Manually entered params (extracted from MIG-ISE test design that worked in hardware)
 PARAMETER C_NDQS_COL0 = 5
 PARAMETER C_NDQS_COL1 = 3
 PARAMETER C_NDQS_COL2 = 0
 PARAMETER C_NDQS_COL3 = 0
 PARAMETER C_DQS_LOC_COL0 = 0x0403020100
 PARAMETER C_DQS_LOC_COL1 = 0x0000070605
 PARAMETER C_ECC = OFF
# END Manually entered params
 PARAMETER C_TCK = 3125
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = microblaze_0.M_AXI_DC & axi_cdma_0.M_AXI & axi2axi_connector_3.M_AXI & axi2axi_connector_4.M_AXI
 PARAMETER C_S_AXI_DATA_WIDTH = 128
 PARAMETER C_S_AXI_BASEADDR = 0x80000000
 PARAMETER C_S_AXI_HIGHADDR = 0xFFFFFFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_core
 PORT clk = clk_160MHz
 PORT clk_mem = clock_generator_MPMC_Clocks_CLKOUT0
 PORT clk_rd_base = clock_generator_MPMC_Clocks_CLKOUT1
 PORT clk_ref = clk_200MHz
 PORT pd_PSEN = MMCM_PSEN
 PORT pd_PSINCDEC = MMCM_PSINCDEC
 PORT pd_PSDONE = clock_generator_MPMC_Clocks_PSDONE
 PORT ddr_ck_p = ddr3_sodimm_ck_p
 PORT ddr_ck_n = ddr3_sodimm_ck_n
 PORT ddr_cke = ddr3_sodimm_cke
 PORT ddr_cs_n = ddr3_sodimm_cs_n
 PORT ddr_odt = ddr3_sodimm_odt
 PORT ddr_ras_n = ddr3_sodimm_ras_n
 PORT ddr_cas_n = ddr3_sodimm_cas_n
 PORT ddr_we_n = ddr3_sodimm_we_n
 PORT ddr_ba = ddr3_sodimm_ba
 PORT ddr_addr = ddr3_sodimm_addr
 PORT ddr_dq = ddr3_sodimm_dq
 PORT ddr_dm = ddr3_sodimm_dm
 PORT ddr_reset_n = ddr3_sodimm_reset_n
 PORT ddr_dqs_p = ddr3_sodimm_dqs_p
 PORT ddr_dqs_n = ddr3_sodimm_dqs_n
 PORT phy_init_done = dram_init_done
END

# ##############################################################################
# Interconnect
# ##############################################################################
BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_buffers
 PARAMETER HW_VER = 1.06.a
 PORT INTERCONNECT_ACLK = clk_160MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_core
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_DATA_WIDTH = 128
 PORT INTERCONNECT_ACLK = clk_160MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_periph_160
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = clk_160MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_periph_80
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
 PORT INTERCONNECT_ACLK = clk_80MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi_interconnect
 PARAMETER INSTANCE = axi_interconnect_dma
 PARAMETER HW_VER = 1.06.a
 PARAMETER C_INTERCONNECT_DATA_WIDTH = 64
 PORT INTERCONNECT_ACLK = clk_160MHz
 PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn
END

BEGIN axi2axi_connector
 PARAMETER INSTANCE = axi2axi_connector_1
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = axi_cdma_0.M_AXI & axi2axi_connector_2.M_AXI & axi2axi_connector_3.M_AXI & axi2axi_connector_4.M_AXI
 PARAMETER C_S_AXI_RNG00_BASEADDR = 0x40000000
 PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x4FFFFFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_M_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_core
 BUS_INTERFACE M_AXI = axi_interconnect_buffers
END

BEGIN axi2axi_connector
 PARAMETER INSTANCE = axi2axi_connector_2
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_S_AXI_RNG00_BASEADDR = 0x40000000
 PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x7FFFFFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
 BUS_INTERFACE M_AXI = axi_interconnect_core
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
END

BEGIN axi2axi_connector
 PARAMETER INSTANCE = axi2axi_connector_3
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ETH_A_DMA.M_AXI_SG & ETH_A_DMA.M_AXI_MM2S & ETH_A_DMA.M_AXI_S2MM
 PARAMETER C_S_AXI_RNG00_BASEADDR = 0x00000000
 PARAMETER C_S_AXI_RNG00_HIGHADDR = 0xFFFFFFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 BUS_INTERFACE S_AXI = axi_interconnect_dma
 BUS_INTERFACE M_AXI = axi_interconnect_core
END

BEGIN axi2axi_connector
 PARAMETER INSTANCE = axi2axi_connector_4
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_INTERCONNECT_S_AXI_MASTERS = ETH_B_DMA.M_AXI_SG & ETH_B_DMA.M_AXI_MM2S & ETH_B_DMA.M_AXI_S2MM
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 PARAMETER C_S_AXI_RNG00_BASEADDR = 0x00000000
 PARAMETER C_S_AXI_RNG00_HIGHADDR = 0xFFFFFFFF
 BUS_INTERFACE S_AXI = axi_interconnect_dma
 BUS_INTERFACE M_AXI = axi_interconnect_core
END

BEGIN axi2axi_connector
 PARAMETER INSTANCE = axi2axi_connector_5
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_S_AXI_RNG00_BASEADDR = 0x20000000
 PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x2FFFFFFF
 PARAMETER C_INTERCONNECT_S_AXI_AW_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_AR_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_W_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_R_REGISTER = 1
 PARAMETER C_INTERCONNECT_S_AXI_B_REGISTER = 1
 PARAMETER C_S_AXI_PROTOCOL = AXI4LITE
 BUS_INTERFACE S_AXI = axi_interconnect_periph_160
 BUS_INTERFACE M_AXI = axi_interconnect_periph_80
END