//Register write macros //4x4 #define warplab_mimo_WriteReg_TxDelay(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXDELAY, data) #define warplab_mimo_WriteReg_RADIO1RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO1RXBUFF_RXEN, data) #define warplab_mimo_WriteReg_RADIO1TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO1TXBUFF_TXEN, data) #define warplab_mimo_WriteReg_RADIO2RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO2RXBUFF_RXEN, data) #define warplab_mimo_WriteReg_RADIO2TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO2TXBUFF_TXEN, data) #define warplab_mimo_WriteReg_RADIO3RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO3RXBUFF_RXEN, data) #define warplab_mimo_WriteReg_RADIO3TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO3TXBUFF_TXEN, data) #define warplab_mimo_WriteReg_RADIO4RXBUFF_RXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO4RXBUFF_RXEN, data) #define warplab_mimo_WriteReg_RADIO4TXBUFF_TXEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO4TXBUFF_TXEN, data) #define warplab_mimo_WriteReg_StartCapture(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STARTCAPTURE, data) #define warplab_mimo_WriteReg_StartTx(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STARTTX, data) #define warplab_mimo_WriteReg_StopTx(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STOPTX, data) #define warplab_mimo_WriteReg_StartTxRx(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_STARTTXRX, data) #define warplab_mimo_WriteReg_TransMode(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TRANSMODE, data) #define warplab_mimo_WriteReg_TxLength(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXLENGTH, data) #define warplab_mimo_WriteReg_DebugRx1Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX1BUFFERS, data) #define warplab_mimo_WriteReg_DebugRx2Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX2BUFFERS, data) #define warplab_mimo_WriteReg_DebugRx3Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX3BUFFERS, data) #define warplab_mimo_WriteReg_DebugRx4Buffers(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX4BUFFERS, data) #define warplab_mimo_WriteReg_MGC_AGC_SEL(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_MGC_AGC_SEL, data) #define warplab_mimo_WriteReg_DCO_EN_SEL(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DCO_EN_SEL, data) //4x4AGC #define warplab_AGC_WriteReg_SRESET_IN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_SRESET_IN, data) #define warplab_AGC_WriteReg_MRESET_IN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_MRESET_IN, data) #define warplab_AGC_WriteReg_PACKET_IN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_PACKET_IN, data) #define warplab_AGC_WriteReg_T_dB(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_T_DB, data) #define warplab_AGC_WriteReg_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_AGC_EN, data) #define warplab_AGC_WriteReg_AVG_LEN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_AVG_LEN, data) #define warplab_AGC_WriteReg_Timing(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_TIMING, data) #define warplab_AGC_WriteReg_Thresholds(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_THRESHOLDS, data) #define warplab_AGC_WriteReg_ADJ(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_ADJ, data) #define warplab_AGC_WriteReg_GBB_init(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_INIT, data) #define warplab_AGC_WriteReg_RADIO1_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO1_AGC_EN, data) #define warplab_AGC_WriteReg_RADIO2_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO2_AGC_EN, data) #define warplab_AGC_WriteReg_RADIO3_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO3_AGC_EN, data) #define warplab_AGC_WriteReg_RADIO4_AGC_EN(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_RADIO4_AGC_EN, data) #define warplab_AGC_WriteReg_AGC_TRIGGER_DELAY(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_AGC_TRIGGER_DELAY, data); #define warplab_AGC_WriteReg_DCO_Timing(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_DCO_TIMING, data); #define warplab_AGC_WriteReg_Bits(data) XIo_Out32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_BITS, data); //Register read macros //4x4 #define warplab_mimo_ReadReg_TxDelay(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXDELAY) #define warplab_mimo_ReadReg_CaptOffset(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_CAPTOFFSET) #define warplab_mimo_ReadReg_CaptureDone(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_CAPTUREDONE) #define warplab_mimo_ReadReg_TransMode(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TRANSMODE) #define warplab_mimo_ReadReg_TxLength(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXLENGTH) #define warplab_mimo_ReadReg_DebugRx1Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX1BUFFERS) #define warplab_mimo_ReadReg_DebugRx2Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX2BUFFERS) #define warplab_mimo_ReadReg_DebugRx3Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX3BUFFERS) #define warplab_mimo_ReadReg_DebugRx4Buffers(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DEBUGRX4BUFFERS) #define warplab_mimo_ReadReg_MGC_AGC_SEL(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_MGC_AGC_SEL) #define warplab_mimo_ReadReg_DCO_EN_SEL(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_DCO_EN_SEL) #define warplab_mimo_ReadReg_AGCDoneAddr(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_AGCDONEADDR) #define warplab_mimo_ReadReg_Radio1AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO1AGCDONERSSI) #define warplab_mimo_ReadReg_Radio2AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO2AGCDONERSSI) #define warplab_mimo_ReadReg_Radio3AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO3AGCDONERSSI) #define warplab_mimo_ReadReg_Radio4AGCDoneRSSI(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RADIO4AGCDONERSSI) //4x4 AGC #define warplab_AGC_ReadReg_GBB_A(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_A) #define warplab_AGC_ReadReg_GBB_B(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_B) #define warplab_AGC_ReadReg_GBB_C(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_C) #define warplab_AGC_ReadReg_GBB_D(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GBB_D) #define warplab_AGC_ReadReg_GRF_A(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_A) #define warplab_AGC_ReadReg_GRF_B(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_B) #define warplab_AGC_ReadReg_GRF_C(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_C) #define warplab_AGC_ReadReg_GRF_D(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_GRF_D) #define warplab_AGC_ReadReg_Thresholds(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_THRESHOLDS) #define warplab_AGC_ReadReg_Bits(addr) XIo_In32(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_MEMMAP_BITS)