1 | |
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2 | # ############################################################################## |
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3 | # Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6 |
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4 | # Thu Jan 08 11:25:14 2009 |
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5 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 1.2 / Radio 1.4 / Clock 1.1 |
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6 | # Family: virtex2p |
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7 | # Device: XC2VP70 |
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8 | # Package: FF1517 |
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9 | # Speed Grade: -6 |
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10 | # Processor: ppc405_0 |
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11 | # Processor clock frequency: 240.00 MHz |
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12 | # Bus clock frequency: 80.00 MHz |
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13 | # On Chip Memory : 96 KB |
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14 | # ############################################################################## |
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15 | # ############################################################################## |
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16 | # Template for PPC405 v3 with PLBv46 bus interface |
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17 | # ############################################################################## |
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18 | PARAMETER VERSION = 2.1.0 |
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19 | |
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20 | |
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21 | PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk, DIR = I |
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22 | PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out, DIR = O |
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23 | PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out, DIR = O |
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24 | PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out, DIR = O |
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25 | PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out, DIR = O |
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26 | PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out, DIR = O |
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27 | PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out, DIR = O |
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28 | PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out, DIR = O |
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29 | PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out, DIR = O |
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30 | PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out, DIR = O |
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31 | PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO, DIR = IO |
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32 | PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk, DIR = O |
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33 | PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs, DIR = O |
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34 | PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data, DIR = O |
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35 | PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA, DIR = O |
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36 | PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA, DIR = O |
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37 | PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW, DIR = O, VEC = [1:0] |
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38 | PORT fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK, DIR = I |
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39 | PORT fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_2_radio_dac_RESET, DIR = O |
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40 | PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW, DIR = I, VEC = [3:0] |
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41 | PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD, DIR = I |
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42 | PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED, DIR = O, VEC = [2:0] |
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43 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk, DIR = O |
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44 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP, DIR = O |
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45 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D, DIR = I, VEC = [9:0] |
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46 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ, DIR = O |
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47 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR, DIR = I |
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48 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP, DIR = O |
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49 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS, DIR = O |
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50 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS, DIR = O |
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51 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA, DIR = I |
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52 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB, DIR = I |
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53 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA, DIR = O |
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54 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB, DIR = O |
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55 | PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn, DIR = O |
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56 | PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn, DIR = O |
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57 | PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP, DIR = O |
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58 | PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN, DIR = O |
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59 | PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk, DIR = O |
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60 | PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs, DIR = O |
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61 | PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data, DIR = O |
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62 | PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B, DIR = O, VEC = [6:0] |
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63 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I, DIR = O, VEC = [15:0] |
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64 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q, DIR = O, VEC = [15:0] |
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65 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I, DIR = I, VEC = [13:0] |
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66 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q, DIR = I, VEC = [13:0] |
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67 | PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out, DIR = O |
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68 | PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO, DIR = IO |
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69 | PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk, DIR = O |
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70 | PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs, DIR = O |
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71 | PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data, DIR = O |
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72 | PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA, DIR = O |
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73 | PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA, DIR = O |
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74 | PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW, DIR = O, VEC = [1:0] |
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75 | PORT fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK, DIR = I |
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76 | PORT fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_3_radio_dac_RESET, DIR = O |
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77 | PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW, DIR = I, VEC = [3:0] |
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78 | PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD, DIR = I |
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79 | PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED, DIR = O, VEC = [2:0] |
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80 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk, DIR = O |
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81 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP, DIR = O |
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82 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D, DIR = I, VEC = [9:0] |
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83 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ, DIR = O |
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84 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR, DIR = I |
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85 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP, DIR = O |
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86 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS, DIR = O |
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87 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS, DIR = O |
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88 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA, DIR = I |
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89 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB, DIR = I |
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90 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA, DIR = O |
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91 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB, DIR = O |
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92 | PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn, DIR = O |
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93 | PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn, DIR = O |
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94 | PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP, DIR = O |
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95 | PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN, DIR = O |
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96 | PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk, DIR = O |
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97 | PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs, DIR = O |
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98 | PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data, DIR = O |
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99 | PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B, DIR = O, VEC = [6:0] |
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100 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I, DIR = O, VEC = [15:0] |
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101 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q, DIR = O, VEC = [15:0] |
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102 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I, DIR = I, VEC = [13:0] |
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103 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q, DIR = I, VEC = [13:0] |
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104 | PORT fpga_0_USER_IO_GPIO2_d_out_pin = fpga_0_USER_IO_GPIO2_d_out, DIR = O, VEC = [0:17] |
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105 | PORT fpga_0_USER_IO_GPIO_in_pin = fpga_0_USER_IO_GPIO_in, DIR = I, VEC = [0:7] |
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106 | PORT fpga_0_rs232_RX_pin = fpga_0_rs232_RX, DIR = I |
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107 | PORT fpga_0_rs232_TX_pin = fpga_0_rs232_TX, DIR = O |
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108 | PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0, DIR = IO |
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109 | PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O |
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110 | PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O |
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111 | PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O |
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112 | PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I |
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113 | PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I |
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114 | PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0] |
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115 | PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O |
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116 | PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I |
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117 | PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I |
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118 | PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I |
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119 | PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I |
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120 | PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0] |
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121 | PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000 |
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122 | PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST |
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123 | PORT debug = rxrun & txrun & agcsetdone & ff_fpga_0_Ethernet_MAC_PHY_ensigs & 0b0 & 0b0 & 0b0 & debug_sw_gpio_O, VEC = [0:15], DIR = O |
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124 | |
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125 | |
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126 | BEGIN ppc405 |
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127 | PARAMETER INSTANCE = ppc405_0 |
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128 | PARAMETER HW_VER = 3.00.a |
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129 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 |
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130 | BUS_INTERFACE DPLB0 = plb0 |
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131 | BUS_INTERFACE IPLB0 = plb0 |
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132 | BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0 |
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133 | BUS_INTERFACE ISOCM = ppc405_0_iocm |
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134 | BUS_INTERFACE DSOCM = ppc405_0_docm |
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135 | BUS_INTERFACE RESETPPC = ppc_reset_bus |
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136 | PORT BRAMISOCMCLK = sys_clk_s |
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137 | PORT BRAMDSOCMCLK = sys_clk_s |
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138 | PORT CPMC405CLOCK = proc_clk_s |
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139 | END |
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140 | |
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141 | BEGIN jtagppc_cntlr |
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142 | PARAMETER INSTANCE = jtagppc_cntlr_0 |
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143 | PARAMETER HW_VER = 2.01.c |
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144 | BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0 |
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145 | END |
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146 | |
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147 | BEGIN plb_v46 |
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148 | PARAMETER INSTANCE = plb0 |
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149 | PARAMETER C_DCR_INTFCE = 0 |
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150 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 |
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151 | PARAMETER HW_VER = 1.03.a |
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152 | PORT PLB_Clk = sys_clk_s |
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153 | PORT SYS_Rst = sys_bus_reset |
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154 | END |
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155 | |
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156 | BEGIN xps_gpio |
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157 | PARAMETER INSTANCE = USER_IO |
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158 | PARAMETER HW_VER = 1.00.a |
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159 | PARAMETER C_GPIO_WIDTH = 18 |
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160 | PARAMETER C_IS_DUAL = 1 |
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161 | PARAMETER C_IS_BIDIR = 0 |
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162 | PARAMETER C_ALL_INPUTS = 1 |
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163 | PARAMETER C_IS_BIDIR_2 = 1 |
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164 | PARAMETER C_ALL_INPUTS_2 = 0 |
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165 | PARAMETER C_BASEADDR = 0x81400000 |
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166 | PARAMETER C_HIGHADDR = 0x8140ffff |
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167 | BUS_INTERFACE SPLB = plb0 |
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168 | PORT GPIO_in = fpga_0_USER_IO_GPIO_in & 0b0000000000 |
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169 | PORT GPIO2_d_out = fpga_0_USER_IO_GPIO2_d_out |
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170 | END |
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171 | |
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172 | BEGIN xps_uartlite |
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173 | PARAMETER INSTANCE = rs232 |
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174 | PARAMETER HW_VER = 1.00.a |
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175 | PARAMETER C_BAUDRATE = 57600 |
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176 | PARAMETER C_DATA_BITS = 8 |
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177 | PARAMETER C_ODD_PARITY = 0 |
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178 | PARAMETER C_USE_PARITY = 0 |
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179 | PARAMETER C_SPLB_CLK_FREQ_HZ = 80000000 |
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180 | PARAMETER C_BASEADDR = 0x84000000 |
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181 | PARAMETER C_HIGHADDR = 0x8400ffff |
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182 | BUS_INTERFACE SPLB = plb0 |
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183 | PORT RX = fpga_0_rs232_RX |
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184 | PORT TX = fpga_0_rs232_TX |
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185 | END |
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186 | |
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187 | BEGIN clock_board_config |
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188 | PARAMETER INSTANCE = clk_board_config |
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189 | PARAMETER HW_VER = 1.04.a |
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190 | PORT sys_clk = fpga_0_clk_board_config_sys_clk |
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191 | PORT sys_rst = net_gnd |
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192 | PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out |
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193 | PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out |
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194 | PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out |
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195 | PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out |
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196 | PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out |
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197 | PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out |
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198 | PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out |
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199 | PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out |
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200 | PORT config_invalid = clk_board_config_config_invalid |
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201 | END |
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202 | |
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203 | BEGIN eeprom |
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204 | PARAMETER INSTANCE = eeprom_controller |
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205 | PARAMETER HW_VER = 1.07.a |
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206 | PARAMETER C_MEM0_BASEADDR = 0xc5400000 |
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207 | PARAMETER C_MEM0_HIGHADDR = 0xc540ffff |
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208 | BUS_INTERFACE SPLB = plb_32b_40MHz |
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209 | PORT DQ0 = fpga_0_eeprom_controller_DQ0 |
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210 | PORT DQ1_I = net_vcc |
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211 | PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T |
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212 | PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O |
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213 | PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I |
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214 | PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T |
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215 | PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O |
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216 | PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I |
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217 | PORT DQ4_I = net_vcc |
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218 | PORT DQ5_I = net_vcc |
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219 | PORT DQ6_I = net_vcc |
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220 | PORT DQ7_I = net_vcc |
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221 | PORT SPLB_Rst = net_gnd |
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222 | END |
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223 | |
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224 | BEGIN xps_ethernetlite |
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225 | PARAMETER INSTANCE = Ethernet_MAC |
---|
226 | PARAMETER HW_VER = 2.00.b |
---|
227 | PARAMETER C_SPLB_CLK_PERIOD_PS = 12500 |
---|
228 | PARAMETER C_BASEADDR = 0x81000000 |
---|
229 | PARAMETER C_HIGHADDR = 0x8100ffff |
---|
230 | BUS_INTERFACE SPLB = plb0 |
---|
231 | PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n |
---|
232 | PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs |
---|
233 | PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col |
---|
234 | PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data |
---|
235 | PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en |
---|
236 | PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk |
---|
237 | PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er |
---|
238 | PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk |
---|
239 | PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv |
---|
240 | PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data |
---|
241 | END |
---|
242 | |
---|
243 | BEGIN radio_controller |
---|
244 | PARAMETER INSTANCE = radio_controller_0 |
---|
245 | PARAMETER HW_VER = 1.22.a |
---|
246 | PARAMETER C_BASEADDR = 0xcac00000 |
---|
247 | PARAMETER C_HIGHADDR = 0xcac0ffff |
---|
248 | BUS_INTERFACE SPLB = plb_32b_40MHz |
---|
249 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk |
---|
250 | PORT spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk |
---|
251 | PORT data_out = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out |
---|
252 | PORT radio2_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs |
---|
253 | PORT radio3_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs |
---|
254 | PORT dac2_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs |
---|
255 | PORT dac3_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs |
---|
256 | PORT radio2_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN |
---|
257 | PORT radio2_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn |
---|
258 | PORT radio2_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn |
---|
259 | PORT radio2_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP |
---|
260 | PORT radio2_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD |
---|
261 | PORT radio2_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA |
---|
262 | PORT radio2_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA |
---|
263 | PORT radio2_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW |
---|
264 | PORT radio2_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED |
---|
265 | PORT radio2_ADC_RX_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS |
---|
266 | PORT radio2_ADC_RX_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS |
---|
267 | PORT radio2_ADC_RX_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA |
---|
268 | PORT radio2_ADC_RX_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB |
---|
269 | PORT radio2_ADC_RX_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA |
---|
270 | PORT radio2_ADC_RX_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB |
---|
271 | PORT radio2_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW |
---|
272 | PORT radio2_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP |
---|
273 | PORT radio2_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ |
---|
274 | PORT radio2_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR |
---|
275 | PORT radio2_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP |
---|
276 | PORT radio2_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D |
---|
277 | PORT radio2_TX_DAC_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK |
---|
278 | PORT radio2_TX_DAC_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET |
---|
279 | PORT radio2_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external |
---|
280 | PORT radio2_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external |
---|
281 | PORT radio2_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external |
---|
282 | PORT radio2_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external |
---|
283 | PORT radio2_TxGain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain |
---|
284 | PORT radio2_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart |
---|
285 | PORT radio3_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN |
---|
286 | PORT radio3_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn |
---|
287 | PORT radio3_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn |
---|
288 | PORT radio3_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP |
---|
289 | PORT radio3_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD |
---|
290 | PORT radio3_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA |
---|
291 | PORT radio3_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA |
---|
292 | PORT radio3_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW |
---|
293 | PORT radio3_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED |
---|
294 | PORT radio3_ADC_RX_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS |
---|
295 | PORT radio3_ADC_RX_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS |
---|
296 | PORT radio3_ADC_RX_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA |
---|
297 | PORT radio3_ADC_RX_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB |
---|
298 | PORT radio3_ADC_RX_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA |
---|
299 | PORT radio3_ADC_RX_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB |
---|
300 | PORT radio3_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW |
---|
301 | PORT radio3_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP |
---|
302 | PORT radio3_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ |
---|
303 | PORT radio3_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR |
---|
304 | PORT radio3_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP |
---|
305 | PORT radio3_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D |
---|
306 | PORT radio3_TX_DAC_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK |
---|
307 | PORT radio3_TX_DAC_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET |
---|
308 | PORT radio3_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external |
---|
309 | PORT radio3_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external |
---|
310 | PORT radio3_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external |
---|
311 | PORT radio3_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external |
---|
312 | PORT radio3_TxGain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain |
---|
313 | PORT radio3_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart |
---|
314 | END |
---|
315 | |
---|
316 | BEGIN radio_bridge |
---|
317 | PARAMETER INSTANCE = radio_bridge_slot_2 |
---|
318 | PARAMETER HW_VER = 1.22.a |
---|
319 | PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out |
---|
320 | PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B |
---|
321 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I |
---|
322 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q |
---|
323 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I |
---|
324 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q |
---|
325 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk |
---|
326 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk |
---|
327 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out |
---|
328 | PORT controller_radio_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs |
---|
329 | PORT controller_dac_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs |
---|
330 | PORT controller_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN |
---|
331 | PORT controller_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn |
---|
332 | PORT controller_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn |
---|
333 | PORT controller_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP |
---|
334 | PORT controller_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA |
---|
335 | PORT controller_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA |
---|
336 | PORT controller_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW |
---|
337 | PORT controller_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED |
---|
338 | PORT controller_RX_ADC_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS |
---|
339 | PORT controller_RX_ADC_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS |
---|
340 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA |
---|
341 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB |
---|
342 | PORT controller_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW |
---|
343 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP |
---|
344 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ |
---|
345 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP |
---|
346 | PORT controller_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D |
---|
347 | PORT controller_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD |
---|
348 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA |
---|
349 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB |
---|
350 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR |
---|
351 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK |
---|
352 | PORT controller_dac_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET |
---|
353 | PORT user_Tx_gain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain |
---|
354 | PORT controller_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart |
---|
355 | PORT controller_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external |
---|
356 | PORT controller_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external |
---|
357 | PORT controller_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external |
---|
358 | PORT controller_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external |
---|
359 | PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data |
---|
360 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs |
---|
361 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk |
---|
362 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk |
---|
363 | PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data |
---|
364 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs |
---|
365 | PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN |
---|
366 | PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn |
---|
367 | PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn |
---|
368 | PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP |
---|
369 | PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA |
---|
370 | PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA |
---|
371 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW |
---|
372 | PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED |
---|
373 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS |
---|
374 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS |
---|
375 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA |
---|
376 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB |
---|
377 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW |
---|
378 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk |
---|
379 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP |
---|
380 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ |
---|
381 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP |
---|
382 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D |
---|
383 | PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD |
---|
384 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA |
---|
385 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB |
---|
386 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR |
---|
387 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK |
---|
388 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_2_radio_dac_RESET |
---|
389 | PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T |
---|
390 | PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O |
---|
391 | PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I |
---|
392 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO |
---|
393 | PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I |
---|
394 | PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q |
---|
395 | PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I |
---|
396 | PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q |
---|
397 | PORT user_TxModelStart = radio2_txStart |
---|
398 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
399 | PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
400 | PORT converter_clock_in = clk_40MHz |
---|
401 | PORT user_RxHP_external = agc_rxhp_b |
---|
402 | PORT user_RxBB_gain = agc_g_bb_b |
---|
403 | PORT user_RxRF_gain = agc_g_rf_b |
---|
404 | END |
---|
405 | |
---|
406 | BEGIN radio_bridge |
---|
407 | PARAMETER INSTANCE = radio_bridge_slot_3 |
---|
408 | PARAMETER HW_VER = 1.22.a |
---|
409 | PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out |
---|
410 | PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B |
---|
411 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I |
---|
412 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q |
---|
413 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I |
---|
414 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q |
---|
415 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk |
---|
416 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk |
---|
417 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out |
---|
418 | PORT controller_radio_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs |
---|
419 | PORT controller_dac_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs |
---|
420 | PORT controller_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN |
---|
421 | PORT controller_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn |
---|
422 | PORT controller_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn |
---|
423 | PORT controller_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP |
---|
424 | PORT controller_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA |
---|
425 | PORT controller_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA |
---|
426 | PORT controller_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW |
---|
427 | PORT controller_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED |
---|
428 | PORT controller_RX_ADC_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS |
---|
429 | PORT controller_RX_ADC_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS |
---|
430 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA |
---|
431 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB |
---|
432 | PORT controller_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW |
---|
433 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP |
---|
434 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ |
---|
435 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP |
---|
436 | PORT controller_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D |
---|
437 | PORT controller_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD |
---|
438 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA |
---|
439 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB |
---|
440 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR |
---|
441 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK |
---|
442 | PORT controller_dac_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET |
---|
443 | PORT user_Tx_gain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain |
---|
444 | PORT controller_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart |
---|
445 | PORT controller_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external |
---|
446 | PORT controller_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external |
---|
447 | PORT controller_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external |
---|
448 | PORT controller_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external |
---|
449 | PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data |
---|
450 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs |
---|
451 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk |
---|
452 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk |
---|
453 | PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data |
---|
454 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs |
---|
455 | PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN |
---|
456 | PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn |
---|
457 | PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn |
---|
458 | PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP |
---|
459 | PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA |
---|
460 | PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA |
---|
461 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW |
---|
462 | PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED |
---|
463 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS |
---|
464 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS |
---|
465 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA |
---|
466 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB |
---|
467 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW |
---|
468 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk |
---|
469 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP |
---|
470 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ |
---|
471 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP |
---|
472 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D |
---|
473 | PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD |
---|
474 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA |
---|
475 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB |
---|
476 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR |
---|
477 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK |
---|
478 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_3_radio_dac_RESET |
---|
479 | PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T |
---|
480 | PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O |
---|
481 | PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I |
---|
482 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO |
---|
483 | PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I |
---|
484 | PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q |
---|
485 | PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I |
---|
486 | PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q |
---|
487 | PORT user_TxModelStart = radio3_txStart |
---|
488 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
489 | PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
490 | PORT converter_clock_in = clk_40MHz |
---|
491 | PORT user_RxHP_external = agc_rxhp_c |
---|
492 | PORT user_RxBB_gain = agc_g_bb_c |
---|
493 | PORT user_RxRF_gain = agc_g_rf_c |
---|
494 | END |
---|
495 | |
---|
496 | BEGIN isocm_v10 |
---|
497 | PARAMETER INSTANCE = ppc405_0_iocm |
---|
498 | PARAMETER HW_VER = 2.00.b |
---|
499 | PARAMETER C_ISCNTLVALUE = 0x85 |
---|
500 | PORT ISOCM_Clk = sys_clk_s |
---|
501 | PORT sys_rst = sys_bus_reset |
---|
502 | END |
---|
503 | |
---|
504 | BEGIN isbram_if_cntlr |
---|
505 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr |
---|
506 | PARAMETER HW_VER = 3.00.b |
---|
507 | PARAMETER C_BASEADDR = 0xffff0000 |
---|
508 | PARAMETER C_HIGHADDR = 0xffffffff |
---|
509 | BUS_INTERFACE ISOCM = ppc405_0_iocm |
---|
510 | BUS_INTERFACE DCR_WRITE_PORT = isocm_porta |
---|
511 | BUS_INTERFACE INSTRN_READ_PORT = isocm_portb |
---|
512 | END |
---|
513 | |
---|
514 | BEGIN bram_block |
---|
515 | PARAMETER INSTANCE = isocm_bram |
---|
516 | PARAMETER HW_VER = 1.00.a |
---|
517 | BUS_INTERFACE PORTA = isocm_porta |
---|
518 | BUS_INTERFACE PORTB = isocm_portb |
---|
519 | END |
---|
520 | |
---|
521 | BEGIN dsocm_v10 |
---|
522 | PARAMETER INSTANCE = ppc405_0_docm |
---|
523 | PARAMETER HW_VER = 2.00.b |
---|
524 | PARAMETER C_DSCNTLVALUE = 0x85 |
---|
525 | PORT DSOCM_Clk = sys_clk_s |
---|
526 | PORT sys_rst = sys_bus_reset |
---|
527 | END |
---|
528 | |
---|
529 | BEGIN dsbram_if_cntlr |
---|
530 | PARAMETER INSTANCE = ppc405_0_docm_cntlr |
---|
531 | PARAMETER HW_VER = 3.00.b |
---|
532 | PARAMETER C_BASEADDR = 0x40800000 |
---|
533 | PARAMETER C_HIGHADDR = 0x40807fff |
---|
534 | BUS_INTERFACE DSOCM = ppc405_0_docm |
---|
535 | BUS_INTERFACE PORTA = dsocm_porta |
---|
536 | END |
---|
537 | |
---|
538 | BEGIN bram_block |
---|
539 | PARAMETER INSTANCE = dsocm_bram |
---|
540 | PARAMETER HW_VER = 1.00.a |
---|
541 | BUS_INTERFACE PORTA = dsocm_porta |
---|
542 | END |
---|
543 | |
---|
544 | BEGIN clock_generator |
---|
545 | PARAMETER INSTANCE = clock_generator_0 |
---|
546 | PARAMETER HW_VER = 2.01.a |
---|
547 | PARAMETER C_EXT_RESET_HIGH = 1 |
---|
548 | PARAMETER C_CLKIN_FREQ = 40000000 |
---|
549 | PARAMETER C_CLKOUT0_FREQ = 80000000 |
---|
550 | PARAMETER C_CLKOUT0_BUF = TRUE |
---|
551 | PARAMETER C_CLKOUT0_PHASE = 0 |
---|
552 | PARAMETER C_CLKOUT0_GROUP = DCM0 |
---|
553 | PARAMETER C_CLKOUT1_FREQ = 240000000 |
---|
554 | PARAMETER C_CLKOUT1_BUF = TRUE |
---|
555 | PARAMETER C_CLKOUT1_PHASE = 0 |
---|
556 | PARAMETER C_CLKOUT1_GROUP = DCM0 |
---|
557 | PARAMETER C_CLKOUT2_FREQ = 40000000 |
---|
558 | PORT CLKOUT0 = sys_clk_s |
---|
559 | PORT CLKOUT1 = proc_clk_s |
---|
560 | PORT CLKOUT2 = clk_40MHz |
---|
561 | PORT CLKIN = dcm_clk_s |
---|
562 | PORT LOCKED = Dcm_all_locked |
---|
563 | PORT RST = clk_board_config_config_invalid |
---|
564 | END |
---|
565 | |
---|
566 | BEGIN proc_sys_reset |
---|
567 | PARAMETER INSTANCE = proc_sys_reset_0 |
---|
568 | PARAMETER HW_VER = 2.00.a |
---|
569 | PARAMETER C_EXT_RESET_HIGH = 1 |
---|
570 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus |
---|
571 | PORT Slowest_sync_clk = clk_40MHz |
---|
572 | PORT Dcm_locked = Dcm_all_locked |
---|
573 | PORT Ext_Reset_In = sys_rst_s |
---|
574 | PORT Bus_Struct_Reset = sys_bus_reset |
---|
575 | PORT Peripheral_Reset = sys_periph_reset |
---|
576 | END |
---|
577 | |
---|
578 | BEGIN plbv46_plbv46_bridge |
---|
579 | PARAMETER INSTANCE = plbv46_plbv46_bridge_0 |
---|
580 | PARAMETER HW_VER = 1.01.a |
---|
581 | PARAMETER C_BUS_CLOCK_RATIO = 2 |
---|
582 | PARAMETER C_NUM_ADDR_RNG = 1 |
---|
583 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000 |
---|
584 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff |
---|
585 | PARAMETER C_RNG0_BASEADDR = 0xc0000000 |
---|
586 | PARAMETER C_RNG0_HIGHADDR = 0xcfffffff |
---|
587 | BUS_INTERFACE SPLB = plb0 |
---|
588 | BUS_INTERFACE MPLB = plb_32b_40MHz |
---|
589 | END |
---|
590 | |
---|
591 | BEGIN plb_v46 |
---|
592 | PARAMETER INSTANCE = plb_32b_40MHz |
---|
593 | PARAMETER HW_VER = 1.03.a |
---|
594 | PORT PLB_Clk = clk_40MHz |
---|
595 | END |
---|
596 | |
---|
597 | BEGIN warplab_mimo_4x4_plbw |
---|
598 | PARAMETER INSTANCE = warplab_mimo_4x4_plbw_0 |
---|
599 | PARAMETER HW_VER = 1.04.a |
---|
600 | PARAMETER C_BASEADDR = 0x84400000 |
---|
601 | PARAMETER C_HIGHADDR = 0x847fffff |
---|
602 | BUS_INTERFACE SPLB = plb0 |
---|
603 | PORT sysgen_clk = clk_40MHz |
---|
604 | PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I |
---|
605 | PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q |
---|
606 | PORT radio2_adc_i_otr = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA |
---|
607 | PORT radio2_adc_q_otr = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB |
---|
608 | PORT startcapture = net_gnd |
---|
609 | PORT StartTx = net_gnd |
---|
610 | PORT StopTx = net_gnd |
---|
611 | PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I |
---|
612 | PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q |
---|
613 | PORT rssi_adc_clk = rssi_clk_out |
---|
614 | PORT debug_capturing = rxrun |
---|
615 | PORT debug_transmitting = txrun |
---|
616 | PORT debug_agc_done = agcsetdone |
---|
617 | PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I |
---|
618 | PORT radio3_adc_i_otr = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA |
---|
619 | PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q |
---|
620 | PORT radio3_adc_q_otr = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB |
---|
621 | PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I |
---|
622 | PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q |
---|
623 | PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
624 | PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
625 | PORT agc_done = agc_is_done |
---|
626 | PORT fromagc_radio2_i = dc_filtered_i_b |
---|
627 | PORT fromagc_radio2_q = dc_filtered_q_b |
---|
628 | PORT fromagc_radio3_i = dc_filtered_i_c |
---|
629 | PORT fromagc_radio3_q = dc_filtered_q_c |
---|
630 | END |
---|
631 | |
---|
632 | BEGIN warplab_mimo_4x4_agc_plbw
|
---|
633 | PARAMETER INSTANCE = warplab_mimo_4x4_agc_plbw_0
|
---|
634 | PARAMETER HW_VER = 2.00.a
|
---|
635 | PARAMETER C_BASEADDR = 0xc4a00000
|
---|
636 | PARAMETER C_HIGHADDR = 0xc4a0ffff
|
---|
637 | BUS_INTERFACE SPLB = plb_32b_40MHz
|
---|
638 | PORT sysgen_clk = clk_40MHz
|
---|
639 | PORT rxhp_d = agc_rxhp_d
|
---|
640 | PORT rxhp_c = agc_rxhp_c
|
---|
641 | PORT rxhp_b = agc_rxhp_b
|
---|
642 | PORT rxhp_a = agc_rxhp_a
|
---|
643 | PORT g_rf_d = agc_g_rf_d
|
---|
644 | PORT g_rf_c = agc_g_rf_c
|
---|
645 | PORT g_rf_b = agc_g_rf_b
|
---|
646 | PORT g_rf_a = agc_g_rf_a
|
---|
647 | PORT g_bb_d = agc_g_bb_d
|
---|
648 | PORT g_bb_c = agc_g_bb_c
|
---|
649 | PORT g_bb_b = agc_g_bb_b
|
---|
650 | PORT g_bb_a = agc_g_bb_a
|
---|
651 | PORT agc_done = agc_is_done
|
---|
652 | PORT rssi_in_d = net_gnd
|
---|
653 | PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
654 | PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
655 | PORT rssi_in_a = net_gnd
|
---|
656 | PORT reset_in = net_gnd
|
---|
657 | PORT q_in_d = net_gnd
|
---|
658 | PORT q_in_c = radio_bridge_slot_3_user_ADC_Q
|
---|
659 | PORT q_in_b = radio_bridge_slot_2_user_ADC_Q
|
---|
660 | PORT q_in_a = net_gnd
|
---|
661 | PORT packet_in = net_gnd
|
---|
662 | PORT mreset_in = net_gnd
|
---|
663 | PORT i_in_d = net_gnd
|
---|
664 | PORT i_in_c = radio_bridge_slot_3_user_ADC_I
|
---|
665 | PORT i_in_b = radio_bridge_slot_2_user_ADC_I
|
---|
666 | PORT i_in_a = net_gnd
|
---|
667 | PORT i_out_a = dc_filtered_i_a
|
---|
668 | PORT i_out_b = dc_filtered_i_b
|
---|
669 | PORT i_out_c = dc_filtered_i_c
|
---|
670 | PORT i_out_d = dc_filtered_i_d
|
---|
671 | PORT q_out_a = dc_filtered_q_a
|
---|
672 | PORT q_out_b = dc_filtered_q_b
|
---|
673 | PORT q_out_c = dc_filtered_q_c
|
---|
674 | PORT q_out_d = dc_filtered_q_d
|
---|
675 | END
|
---|
676 | |
---|
677 | BEGIN xps_gpio |
---|
678 | PARAMETER INSTANCE = debug_sw_gpio |
---|
679 | PARAMETER HW_VER = 1.00.a |
---|
680 | PARAMETER C_GPIO_WIDTH = 8 |
---|
681 | PARAMETER C_IS_BIDIR = 0 |
---|
682 | PARAMETER C_BASEADDR = 0x81420000 |
---|
683 | PARAMETER C_HIGHADDR = 0x8142ffff |
---|
684 | BUS_INTERFACE SPLB = plb0 |
---|
685 | PORT GPIO_d_out = debug_sw_gpio_O |
---|
686 | END |
---|
687 | |
---|
688 | BEGIN util_flipflop |
---|
689 | PARAMETER INSTANCE = util_flipflop_0 |
---|
690 | PARAMETER HW_VER = 1.10.a |
---|
691 | PARAMETER C_USE_RST = 0 |
---|
692 | PARAMETER C_USE_SET = 0 |
---|
693 | PARAMETER C_SET_RST_HIGH = 0 |
---|
694 | PARAMETER C_USE_CE = 0 |
---|
695 | PARAMETER C_USE_ASYNCH = 0 |
---|
696 | PARAMETER C_SIZE = 2 |
---|
697 | PORT Clk = sys_clk_s |
---|
698 | PORT D = fpga_0_Ethernet_MAC_PHY_dv & fpga_0_Ethernet_MAC_PHY_tx_en |
---|
699 | PORT Q = ff_fpga_0_Ethernet_MAC_PHY_ensigs |
---|
700 | END |
---|
701 | |
---|