############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AT20;
Net sys_clk_pin IOSTANDARD = LVTTL;
Net sys_rst_pin LOC=AM16;
Net sys_rst_pin IOSTANDARD = LVTTL;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps;
Net sys_rst_pin TIG;
NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;

## IO Devices constraints

#Debug header LOC constraints (manually entered)
NET "debug<0>" LOC = "K28" | IOSTANDARD = LVTTL; #pin 0
NET "debug<1>" LOC = "G30" | IOSTANDARD = LVTTL; #pin 1
NET "debug<2>" LOC = "H29" | IOSTANDARD = LVTTL; #pin 2
NET "debug<3>" LOC = "H30" | IOSTANDARD = LVTTL; #pin 3
NET "debug<4>" LOC = "J28" | IOSTANDARD = LVTTL; #pin 4
NET "debug<5>" LOC = "F30" | IOSTANDARD = LVTTL; #pin 5
NET "debug<6>" LOC = "E29" | IOSTANDARD = LVTTL; #pin 6
NET "debug<7>" LOC = "D30" | IOSTANDARD = LVTTL; #pin 7
NET "debug<8>" LOC = "K30" | IOSTANDARD = LVTTL; #pin 8
NET "debug<9>" LOC = "J30" | IOSTANDARD = LVTTL; #pin 9
NET "debug<10>" LOC = "K29" | IOSTANDARD = LVTTL; #pin 10
NET "debug<11>" LOC = "J29" | IOSTANDARD = LVTTL; #pin 11
NET "debug<12>" LOC = "G29" | IOSTANDARD = LVTTL; #pin 12
NET "debug<13>" LOC = "H28" | IOSTANDARD = LVTTL; #pin 13
NET "debug<14>" LOC = "F29" | IOSTANDARD = LVTTL; #pin 14
NET "debug<15>" LOC = "E30" | IOSTANDARD = LVTTL; #pin 15

#### Module USER_IO constraints

Net fpga_0_USER_IO_GPIO_in_pin<0> LOC=Y27;
Net fpga_0_USER_IO_GPIO_in_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<1> LOC=Y28;
Net fpga_0_USER_IO_GPIO_in_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<2> LOC=AA27;
Net fpga_0_USER_IO_GPIO_in_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<3> LOC=Y29;
Net fpga_0_USER_IO_GPIO_in_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<4> LOC=AJ22;
Net fpga_0_USER_IO_GPIO_in_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<5> LOC=AJ15;
Net fpga_0_USER_IO_GPIO_in_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<6> LOC=AG18;
Net fpga_0_USER_IO_GPIO_in_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO_in_pin<7> LOC=AG17;
Net fpga_0_USER_IO_GPIO_in_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<0> LOC=AJ26;
Net fpga_0_USER_IO_GPIO2_d_out_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<1> LOC=AH26;
Net fpga_0_USER_IO_GPIO2_d_out_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<2> LOC=AH24;
Net fpga_0_USER_IO_GPIO2_d_out_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<3> LOC=AH25;
Net fpga_0_USER_IO_GPIO2_d_out_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<4> LOC=AH23;
Net fpga_0_USER_IO_GPIO2_d_out_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<5> LOC=AG22;
Net fpga_0_USER_IO_GPIO2_d_out_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<6> LOC=AG23;
Net fpga_0_USER_IO_GPIO2_d_out_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<7> LOC=AG19;
Net fpga_0_USER_IO_GPIO2_d_out_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<8> LOC=AG21;
Net fpga_0_USER_IO_GPIO2_d_out_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<9> LOC=AH19;
Net fpga_0_USER_IO_GPIO2_d_out_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<10> LOC=AJ19;
Net fpga_0_USER_IO_GPIO2_d_out_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<11> LOC=AP12;
Net fpga_0_USER_IO_GPIO2_d_out_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<12> LOC=AN13;
Net fpga_0_USER_IO_GPIO2_d_out_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<13> LOC=AL15;
Net fpga_0_USER_IO_GPIO2_d_out_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<14> LOC=AJ14;
Net fpga_0_USER_IO_GPIO2_d_out_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<15> LOC=AM13;
Net fpga_0_USER_IO_GPIO2_d_out_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<16> LOC=AR12;
Net fpga_0_USER_IO_GPIO2_d_out_pin<16> IOSTANDARD = LVTTL;
Net fpga_0_USER_IO_GPIO2_d_out_pin<17> LOC=AH13;
Net fpga_0_USER_IO_GPIO2_d_out_pin<17> IOSTANDARD = LVTTL;

#### Module rs232 constraints

Net fpga_0_rs232_RX_pin LOC=AA29;
Net fpga_0_rs232_RX_pin IOSTANDARD = LVTTL;
Net fpga_0_rs232_TX_pin LOC=AA28;
Net fpga_0_rs232_TX_pin IOSTANDARD = LVTTL;

#### Module clk_board_config constraints

Net fpga_0_clk_board_config_sys_clk_pin LOC=AH21;
Net fpga_0_clk_board_config_sys_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN25;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AK26;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AJ25;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AL26;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AT27;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AR27;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AN27;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AM27;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin IOSTANDARD=LVTTL;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin SLEW = SLOW;

#### Module eeprom_controller constraints

Net fpga_0_eeprom_controller_DQ0_pin LOC=AB28;
Net fpga_0_eeprom_controller_DQ0_pin IOSTANDARD = LVTTL;
Net fpga_0_eeprom_controller_DQ0_pin SLEW = SLOW;
Net fpga_0_eeprom_controller_DQ0_pin DRIVE = 8;

#### Module Ethernet_MAC constraints

Net fpga_0_Ethernet_MAC_slew1_pin LOC=H20;
Net fpga_0_Ethernet_MAC_slew1_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_slew1_pin SLEW = SLOW;
Net fpga_0_Ethernet_MAC_slew1_pin DRIVE = 8;
Net fpga_0_Ethernet_MAC_slew2_pin LOC=J22;
Net fpga_0_Ethernet_MAC_slew2_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_slew2_pin SLEW = SLOW;
Net fpga_0_Ethernet_MAC_slew2_pin DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J27;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_rst_n_pin DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=D29;
Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=J26;
Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=G26;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=D26;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=H23;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=D22;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=H22;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin SLEW = SLOW;
Net fpga_0_Ethernet_MAC_PHY_tx_en_pin DRIVE = 8;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=F20;
Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=F21;
Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=E24;
Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=F22;
Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=C22;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=E21;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C21;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=D23;
Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVTTL;

#### Module radio_controller_0 constraints


#### Module radio_bridge_slot_2 constraints

Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AG2;
Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AB7;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AB8;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=AC10;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=AB9;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AF3;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=AL1;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AE4;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=AD4;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=AB11;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=AB10;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG20;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=AG1;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=AE3;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AC5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=AE1;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AB5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=AB4;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=AB6;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AD2;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=AA7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=AB3;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AE7;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AC12;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AJ2;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AG5;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AJ1;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AH3;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AH4;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AJ3;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=AA10;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=AE2;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=AA12;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AF1;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=AD3;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=AF2;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AD13;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AT8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AR8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AT5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AH11;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AT6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AD12;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AN9;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AE13;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AK9;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AR7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AP7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AF12;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AH10;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AM6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AE10;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AH8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AM4;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AL7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AE11;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AL6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AN6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AK8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AG9;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AM7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AL9;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AE12;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AN7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AH7;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AR6;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AM8;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AL5;
Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AJ6;
Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK6;
Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AL3;
Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AK4;
Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AF9;
Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AF5;
Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=AM2;
Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AD10;
Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AE6;
Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=AA9;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AB2;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=AB1;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=AA6;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA5;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=AA8;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=AC2;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> DRIVE = 2;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AD8;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AK1;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=AA3;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AF6;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=AG7;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AL2;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=AJ4;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AK3;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AK2;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AH6;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AF8;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AF7;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AF11;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AE8;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AF10;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AD11;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AJ7;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AJ5;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AJ8;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AG11;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AM9;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AK7;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AK5;
Net fpga_0_radio_bridge_slot_2_radio_LD_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=AA4;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=AC4;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AJ9;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin LOC=AG10;
Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin LOC=AM3;
Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO LOC=AG3;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO DRIVE = 8;

#### Module radio_bridge_slot_3 constraints

Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AP33;
Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AJ33;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AL37;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AK36;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AM38;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AK37;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AJ36;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AL38;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AG29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AR34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AU35;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AJ21;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AT32;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AT34;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AR33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AM36;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AD28;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AL33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AH32;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AD29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AK33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AE31;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AH29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AK31;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AE28;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AF28;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AE27;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AD27;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AN33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AL31;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AR32;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AM33;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AG30;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AM32;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AE29;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AN31;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB30;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AF38;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AD37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=AF37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=AF39;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA30;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=AC35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=AE38;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AE36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=AB36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=AB33;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=AE39;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=AB35;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=AB32;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=AD32;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AK39;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=AF34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=AB29;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=AC27;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AE34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=AJ37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=AC30;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=AH36;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AJ38;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=AJ39;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AG39;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=AF33;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=AH37;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=AG34;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=AG38;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=AC32;
Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=AB31;
Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AC31;
Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AD33;
Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AK38;
Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AC28;
Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AE30;
Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AC34;
Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=AL34;
Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AK32;
Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AE33;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AH34;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AG33;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AH33;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AN34;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AK35;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AK34;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> DRIVE = 2;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AH30;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AM34;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AD30;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AF29;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG37;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AD34;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=AF36;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AL39;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AM37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=AA32;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=AB38;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=AA37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=AA33;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AD36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=AC38;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AB37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=AA36;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=AC39;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=AA34;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=AA31;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AA35;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=AE37;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AG35;
Net fpga_0_radio_bridge_slot_3_radio_LD_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AG31;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AF30;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=AD38;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin LOC=AH38;
Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin LOC=AE35;
Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO LOC=AJ31;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO SLEW = SLOW;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO DRIVE = 8;