1 | |
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2 | # ############################################################################## |
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3 | # Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6 |
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4 | # Sat Oct 10 15:03:40 2009 |
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5 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1 |
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6 | # Family: virtex4 |
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7 | # Device: XC4VFX100 |
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8 | # Package: FF1517 |
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9 | # Speed Grade: -11 |
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10 | # Processor: ppc405_0 |
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11 | # Processor clock frequency: 240.00 MHz |
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12 | # Bus clock frequency: 80.00 MHz |
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13 | # On Chip Memory : 96 KB |
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14 | # ############################################################################## |
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15 | PARAMETER VERSION = 2.1.0 |
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16 | |
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17 | |
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18 | PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk, DIR = I |
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19 | PORT fpga_0_warp_v4_userio_all_LEDs_out_pin = fpga_0_warp_v4_userio_all_LEDs_out, DIR = O, VEC = [0:7] |
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20 | PORT fpga_0_warp_v4_userio_all_PB_in_pin = fpga_0_warp_v4_userio_all_PB_in, DIR = I, VEC = [0:3] |
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21 | PORT fpga_0_warp_v4_userio_all_IOEx_SCL_pin = fpga_0_warp_v4_userio_all_IOEx_SCL, DIR = O |
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22 | PORT fpga_0_warp_v4_userio_all_IOEx_SDA_pin = fpga_0_warp_v4_userio_all_IOEx_SDA, DIR = O |
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23 | PORT fpga_0_rs232_db9_RX_pin = fpga_0_rs232_db9_RX, DIR = I |
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24 | PORT fpga_0_rs232_db9_TX_pin = fpga_0_rs232_db9_TX, DIR = O |
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25 | PORT fpga_0_warp_v4_userio_all_DIPSW_in_pin = fpga_0_warp_v4_userio_all_DIPSW_in, DIR = I, VEC = [0:3] |
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26 | PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out, DIR = O |
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27 | PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out, DIR = O |
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28 | PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out, DIR = O |
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29 | PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out, DIR = O |
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30 | PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out, DIR = O |
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31 | PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out, DIR = O |
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32 | PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out, DIR = O |
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33 | PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out, DIR = O |
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34 | PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out, DIR = O |
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35 | PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO, DIR = IO |
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36 | PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk, DIR = O |
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37 | PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs, DIR = O |
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38 | PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data, DIR = O |
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39 | PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA, DIR = O |
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40 | PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA, DIR = O |
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41 | PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW, DIR = O, VEC = [1:0] |
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42 | PORT fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK, DIR = I |
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43 | PORT fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_2_radio_dac_RESET, DIR = O |
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44 | PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW, DIR = I, VEC = [3:0] |
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45 | PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD, DIR = I |
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46 | PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED, DIR = O, VEC = [2:0] |
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47 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk, DIR = O |
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48 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP, DIR = O |
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49 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D, DIR = I, VEC = [9:0] |
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50 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ, DIR = O |
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51 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR, DIR = I |
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52 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP, DIR = O |
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53 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS, DIR = O |
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54 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS, DIR = O |
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55 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA, DIR = I |
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56 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB, DIR = I |
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57 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA, DIR = O |
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58 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB, DIR = O |
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59 | PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn, DIR = O |
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60 | PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP, DIR = O |
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61 | PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN, DIR = O |
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62 | PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk, DIR = O |
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63 | PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs, DIR = O |
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64 | PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data, DIR = O |
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65 | PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn, DIR = O |
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66 | PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B, DIR = O, VEC = [6:0] |
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67 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I, DIR = O, VEC = [15:0] |
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68 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q, DIR = O, VEC = [15:0] |
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69 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I, DIR = I, VEC = [13:0] |
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70 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q, DIR = I, VEC = [13:0] |
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71 | PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out, DIR = O |
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72 | PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO, DIR = IO |
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73 | PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk, DIR = O |
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74 | PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs, DIR = O |
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75 | PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data, DIR = O |
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76 | PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA, DIR = O |
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77 | PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA, DIR = O |
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78 | PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW, DIR = O, VEC = [1:0] |
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79 | PORT fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK, DIR = I |
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80 | PORT fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_3_radio_dac_RESET, DIR = O |
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81 | PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW, DIR = I, VEC = [3:0] |
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82 | PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD, DIR = I |
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83 | PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED, DIR = O, VEC = [2:0] |
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84 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk, DIR = O |
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85 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP, DIR = O |
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86 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D, DIR = I, VEC = [9:0] |
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87 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ, DIR = O |
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88 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR, DIR = I |
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89 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP, DIR = O |
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90 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS, DIR = O |
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91 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS, DIR = O |
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92 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA, DIR = I |
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93 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB, DIR = I |
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94 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA, DIR = O |
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95 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB, DIR = O |
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96 | PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn, DIR = O |
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97 | PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP, DIR = O |
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98 | PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN, DIR = O |
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99 | PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk, DIR = O |
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100 | PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs, DIR = O |
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101 | PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data, DIR = O |
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102 | PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn, DIR = O |
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103 | PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B, DIR = O, VEC = [6:0] |
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104 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I, DIR = O, VEC = [15:0] |
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105 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q, DIR = O, VEC = [15:0] |
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106 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I, DIR = I, VEC = [13:0] |
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107 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q, DIR = I, VEC = [13:0] |
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108 | PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0, DIR = IO |
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109 | PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O |
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110 | PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I |
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111 | PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I |
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112 | PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0] |
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113 | PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O |
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114 | PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I |
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115 | PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I |
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116 | PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I |
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117 | PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I |
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118 | PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0] |
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119 | PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000 |
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120 | PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST |
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121 | PORT debug = rxrun & txrun & agcsetdone & ff_fpga_0_Ethernet_MAC_PHY_ensigs & 0b0 & 0b0 & 0b0 & debug_sw_gpio_O, VEC = [0:15], DIR = O |
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122 | PORT mgt_null_controller_0_rxn_mgt01_pin = mgt_null_controller_0_rxn_mgt01, DIR = I, VEC = [0:1] |
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123 | PORT mgt_null_controller_0_rxp_mgt01_pin = mgt_null_controller_0_rxp_mgt01, DIR = I, VEC = [0:1] |
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124 | PORT mgt_null_controller_0_txn_mgt01_pin = mgt_null_controller_0_txn_mgt01, DIR = O, VEC = [0:1] |
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125 | PORT mgt_null_controller_0_txp_mgt01_pin = mgt_null_controller_0_txp_mgt01, DIR = O, VEC = [0:1] |
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126 | PORT mgt_null_controller_0_rxn_mgt02_pin = mgt_null_controller_0_rxn_mgt02, DIR = I, VEC = [0:1] |
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127 | PORT mgt_null_controller_0_rxp_mgt02_pin = mgt_null_controller_0_rxp_mgt02, DIR = I, VEC = [0:1] |
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128 | PORT mgt_null_controller_0_txn_mgt02_pin = mgt_null_controller_0_txn_mgt02, DIR = O, VEC = [0:1] |
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129 | PORT mgt_null_controller_0_txp_mgt02_pin = mgt_null_controller_0_txp_mgt02, DIR = O, VEC = [0:1] |
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130 | PORT mgt_null_controller_0_rxn_mgt03_pin = mgt_null_controller_0_rxn_mgt03, DIR = I, VEC = [0:1] |
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131 | PORT mgt_null_controller_0_rxp_mgt03_pin = mgt_null_controller_0_rxp_mgt03, DIR = I, VEC = [0:1] |
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132 | PORT mgt_null_controller_0_txn_mgt03_pin = mgt_null_controller_0_txn_mgt03, DIR = O, VEC = [0:1] |
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133 | PORT mgt_null_controller_0_txp_mgt03_pin = mgt_null_controller_0_txp_mgt03, DIR = O, VEC = [0:1] |
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134 | PORT mgt_null_controller_0_rxn_mgt05_pin = mgt_null_controller_0_rxn_mgt05, DIR = I, VEC = [0:1] |
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135 | PORT mgt_null_controller_0_rxp_mgt05_pin = mgt_null_controller_0_rxp_mgt05, DIR = I, VEC = [0:1] |
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136 | PORT mgt_null_controller_0_txn_mgt05_pin = mgt_null_controller_0_txn_mgt05, DIR = O, VEC = [0:1] |
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137 | PORT mgt_null_controller_0_txp_mgt05_pin = mgt_null_controller_0_txp_mgt05, DIR = O, VEC = [0:1] |
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138 | PORT mgt_null_controller_0_rxn_mgt06_pin = mgt_null_controller_0_rxn_mgt06, DIR = I, VEC = [0:1] |
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139 | PORT mgt_null_controller_0_rxp_mgt06_pin = mgt_null_controller_0_rxp_mgt06, DIR = I, VEC = [0:1] |
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140 | PORT mgt_null_controller_0_txn_mgt06_pin = mgt_null_controller_0_txn_mgt06, DIR = O, VEC = [0:1] |
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141 | PORT mgt_null_controller_0_txp_mgt06_pin = mgt_null_controller_0_txp_mgt06, DIR = O, VEC = [0:1] |
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142 | PORT mgt_null_controller_0_rxn_mgt09_pin = mgt_null_controller_0_rxn_mgt09, DIR = I, VEC = [0:1] |
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143 | PORT mgt_null_controller_0_rxp_mgt09_pin = mgt_null_controller_0_rxp_mgt09, DIR = I, VEC = [0:1] |
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144 | PORT mgt_null_controller_0_txn_mgt09_pin = mgt_null_controller_0_txn_mgt09, DIR = O, VEC = [0:1] |
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145 | PORT mgt_null_controller_0_txp_mgt09_pin = mgt_null_controller_0_txp_mgt09, DIR = O, VEC = [0:1] |
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146 | PORT mgt_null_controller_0_rxn_mgt10_pin = mgt_null_controller_0_rxn_mgt10, DIR = I, VEC = [0:1] |
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147 | PORT mgt_null_controller_0_rxp_mgt10_pin = mgt_null_controller_0_rxp_mgt10, DIR = I, VEC = [0:1] |
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148 | PORT mgt_null_controller_0_txn_mgt10_pin = mgt_null_controller_0_txn_mgt10, DIR = O, VEC = [0:1] |
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149 | PORT mgt_null_controller_0_txp_mgt10_pin = mgt_null_controller_0_txp_mgt10, DIR = O, VEC = [0:1] |
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150 | PORT mgt_null_controller_0_rxn_mgt12_pin = mgt_null_controller_0_rxn_mgt12, DIR = I, VEC = [0:1] |
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151 | PORT mgt_null_controller_0_rxp_mgt12_pin = mgt_null_controller_0_rxp_mgt12, DIR = I, VEC = [0:1] |
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152 | PORT mgt_null_controller_0_txn_mgt12_pin = mgt_null_controller_0_txn_mgt12, DIR = O, VEC = [0:1] |
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153 | PORT mgt_null_controller_0_txp_mgt12_pin = mgt_null_controller_0_txp_mgt12, DIR = O, VEC = [0:1] |
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154 | PORT mgt_null_controller_0_rxn_mgt13_pin = mgt_null_controller_0_rxn_mgt13, DIR = I, VEC = [0:1] |
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155 | PORT mgt_null_controller_0_rxp_mgt13_pin = mgt_null_controller_0_rxp_mgt13, DIR = I, VEC = [0:1] |
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156 | PORT mgt_null_controller_0_txn_mgt13_pin = mgt_null_controller_0_txn_mgt13, DIR = O, VEC = [0:1] |
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157 | PORT mgt_null_controller_0_txp_mgt13_pin = mgt_null_controller_0_txp_mgt13, DIR = O, VEC = [0:1] |
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158 | PORT mgt_null_controller_0_rxn_mgt14_pin = mgt_null_controller_0_rxn_mgt14, DIR = I, VEC = [0:1] |
---|
159 | PORT mgt_null_controller_0_rxp_mgt14_pin = mgt_null_controller_0_rxp_mgt14, DIR = I, VEC = [0:1] |
---|
160 | PORT mgt_null_controller_0_txn_mgt14_pin = mgt_null_controller_0_txn_mgt14, DIR = O, VEC = [0:1] |
---|
161 | PORT mgt_null_controller_0_txp_mgt14_pin = mgt_null_controller_0_txp_mgt14, DIR = O, VEC = [0:1] |
---|
162 | |
---|
163 | |
---|
164 | BEGIN ppc405_virtex4 |
---|
165 | PARAMETER INSTANCE = ppc405_0 |
---|
166 | PARAMETER HW_VER = 2.01.a |
---|
167 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 |
---|
168 | PARAMETER C_IDCR_BASEADDR = 0b0100000000 |
---|
169 | PARAMETER C_IDCR_HIGHADDR = 0b0111111111 |
---|
170 | BUS_INTERFACE IPLB0 = plb |
---|
171 | BUS_INTERFACE DPLB0 = plb |
---|
172 | BUS_INTERFACE ISOCM = ppc405_0_iocm |
---|
173 | BUS_INTERFACE DSOCM = ppc405_0_docm |
---|
174 | BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0 |
---|
175 | BUS_INTERFACE RESETPPC = ppc_reset_bus |
---|
176 | PORT BRAMISOCMCLK = sys_clk_s |
---|
177 | PORT BRAMDSOCMCLK = sys_clk_s |
---|
178 | PORT CPMC405CLOCK = proc_clk_s |
---|
179 | END |
---|
180 | |
---|
181 | BEGIN plb_v46 |
---|
182 | PARAMETER INSTANCE = plb |
---|
183 | PARAMETER C_DCR_INTFCE = 0 |
---|
184 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 |
---|
185 | PARAMETER HW_VER = 1.03.a |
---|
186 | PORT PLB_Clk = sys_clk_s |
---|
187 | PORT SYS_Rst = sys_bus_reset |
---|
188 | END |
---|
189 | |
---|
190 | BEGIN warp_v4_userio |
---|
191 | PARAMETER INSTANCE = warp_v4_userio_all |
---|
192 | PARAMETER HW_VER = 1.00.a |
---|
193 | PARAMETER C_ADDRESS_0 = 0x40 |
---|
194 | PARAMETER C_ADDRESS_1 = 0x42 |
---|
195 | PARAMETER C_I2C_DIVIDER = 0x40 |
---|
196 | PARAMETER C_BASEADDR = 0xc6000000 |
---|
197 | PARAMETER C_HIGHADDR = 0xc600ffff |
---|
198 | BUS_INTERFACE SPLB = plb |
---|
199 | PORT LEDs_out = fpga_0_warp_v4_userio_all_LEDs_out |
---|
200 | PORT DIPSW_in = fpga_0_warp_v4_userio_all_DIPSW_in |
---|
201 | PORT PB_in = fpga_0_warp_v4_userio_all_PB_in |
---|
202 | PORT IOEx_SCL = fpga_0_warp_v4_userio_all_IOEx_SCL |
---|
203 | PORT IOEx_SDA = fpga_0_warp_v4_userio_all_IOEx_SDA |
---|
204 | END |
---|
205 | |
---|
206 | BEGIN xps_uartlite |
---|
207 | PARAMETER INSTANCE = rs232_db9 |
---|
208 | PARAMETER HW_VER = 1.00.a |
---|
209 | PARAMETER C_BAUDRATE = 57600 |
---|
210 | PARAMETER C_DATA_BITS = 8 |
---|
211 | PARAMETER C_ODD_PARITY = 0 |
---|
212 | PARAMETER C_USE_PARITY = 0 |
---|
213 | PARAMETER C_SPLB_CLK_FREQ_HZ = 80000000 |
---|
214 | PARAMETER C_BASEADDR = 0x84000000 |
---|
215 | PARAMETER C_HIGHADDR = 0x8400ffff |
---|
216 | BUS_INTERFACE SPLB = plb |
---|
217 | PORT RX = fpga_0_rs232_db9_RX |
---|
218 | PORT TX = fpga_0_rs232_db9_TX |
---|
219 | END |
---|
220 | |
---|
221 | BEGIN clock_board_config |
---|
222 | PARAMETER INSTANCE = clk_board_config |
---|
223 | PARAMETER HW_VER = 1.04.a |
---|
224 | PARAMETER radio_clk_out4_mode = 0x1eff |
---|
225 | PARAMETER radio_clk_out7_mode = 0x1eff |
---|
226 | PARAMETER logic_clk_out0_mode = 0x08ff |
---|
227 | PARAMETER logic_clk_out1_mode = 0x08ff |
---|
228 | PORT sys_clk = fpga_0_clk_board_config_sys_clk |
---|
229 | PORT sys_rst = net_gnd |
---|
230 | PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out |
---|
231 | PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out |
---|
232 | PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out |
---|
233 | PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out |
---|
234 | PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out |
---|
235 | PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out |
---|
236 | PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out |
---|
237 | PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out |
---|
238 | PORT config_invalid = clk_board_config_config_invalid |
---|
239 | END |
---|
240 | |
---|
241 | BEGIN radio_controller |
---|
242 | PARAMETER INSTANCE = radio_controller_0 |
---|
243 | PARAMETER HW_VER = 1.22.a |
---|
244 | PARAMETER C_BASEADDR = 0xcac00000 |
---|
245 | PARAMETER C_HIGHADDR = 0xcac0ffff |
---|
246 | BUS_INTERFACE SPLB = plb_v46_40MHz |
---|
247 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk |
---|
248 | PORT spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk |
---|
249 | PORT data_out = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out |
---|
250 | PORT radio2_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs |
---|
251 | PORT radio3_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs |
---|
252 | PORT dac2_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs |
---|
253 | PORT dac3_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs |
---|
254 | PORT radio2_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN |
---|
255 | PORT radio2_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn |
---|
256 | PORT radio2_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn |
---|
257 | PORT radio2_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP |
---|
258 | PORT radio2_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD |
---|
259 | PORT radio2_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA |
---|
260 | PORT radio2_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA |
---|
261 | PORT radio2_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW |
---|
262 | PORT radio2_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED |
---|
263 | PORT radio2_ADC_RX_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS |
---|
264 | PORT radio2_ADC_RX_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS |
---|
265 | PORT radio2_ADC_RX_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA |
---|
266 | PORT radio2_ADC_RX_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB |
---|
267 | PORT radio2_ADC_RX_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA |
---|
268 | PORT radio2_ADC_RX_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB |
---|
269 | PORT radio2_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW |
---|
270 | PORT radio2_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP |
---|
271 | PORT radio2_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ |
---|
272 | PORT radio2_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR |
---|
273 | PORT radio2_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP |
---|
274 | PORT radio2_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D |
---|
275 | PORT radio2_TX_DAC_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK |
---|
276 | PORT radio2_TX_DAC_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET |
---|
277 | PORT radio2_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external |
---|
278 | PORT radio2_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external |
---|
279 | PORT radio2_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external |
---|
280 | PORT radio2_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external |
---|
281 | PORT radio2_TxGain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain |
---|
282 | PORT radio2_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart |
---|
283 | PORT radio3_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN |
---|
284 | PORT radio3_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn |
---|
285 | PORT radio3_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn |
---|
286 | PORT radio3_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP |
---|
287 | PORT radio3_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD |
---|
288 | PORT radio3_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA |
---|
289 | PORT radio3_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA |
---|
290 | PORT radio3_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW |
---|
291 | PORT radio3_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED |
---|
292 | PORT radio3_ADC_RX_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS |
---|
293 | PORT radio3_ADC_RX_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS |
---|
294 | PORT radio3_ADC_RX_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA |
---|
295 | PORT radio3_ADC_RX_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB |
---|
296 | PORT radio3_ADC_RX_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA |
---|
297 | PORT radio3_ADC_RX_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB |
---|
298 | PORT radio3_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW |
---|
299 | PORT radio3_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP |
---|
300 | PORT radio3_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ |
---|
301 | PORT radio3_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR |
---|
302 | PORT radio3_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP |
---|
303 | PORT radio3_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D |
---|
304 | PORT radio3_TX_DAC_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK |
---|
305 | PORT radio3_TX_DAC_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET |
---|
306 | PORT radio3_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external |
---|
307 | PORT radio3_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external |
---|
308 | PORT radio3_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external |
---|
309 | PORT radio3_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external |
---|
310 | PORT radio3_TxGain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain |
---|
311 | PORT radio3_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart |
---|
312 | END |
---|
313 | |
---|
314 | BEGIN radio_bridge |
---|
315 | PARAMETER INSTANCE = radio_bridge_slot_2 |
---|
316 | PARAMETER HW_VER = 1.22.a |
---|
317 | PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out |
---|
318 | PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B |
---|
319 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I |
---|
320 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q |
---|
321 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I |
---|
322 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q |
---|
323 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk |
---|
324 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk |
---|
325 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out |
---|
326 | PORT controller_radio_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs |
---|
327 | PORT controller_dac_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs |
---|
328 | PORT controller_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN |
---|
329 | PORT controller_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn |
---|
330 | PORT controller_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn |
---|
331 | PORT controller_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP |
---|
332 | PORT controller_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA |
---|
333 | PORT controller_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA |
---|
334 | PORT controller_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW |
---|
335 | PORT controller_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED |
---|
336 | PORT controller_RX_ADC_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS |
---|
337 | PORT controller_RX_ADC_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS |
---|
338 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA |
---|
339 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB |
---|
340 | PORT controller_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW |
---|
341 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP |
---|
342 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ |
---|
343 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP |
---|
344 | PORT controller_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D |
---|
345 | PORT controller_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD |
---|
346 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA |
---|
347 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB |
---|
348 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR |
---|
349 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK |
---|
350 | PORT controller_dac_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET |
---|
351 | PORT user_Tx_gain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain |
---|
352 | PORT controller_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart |
---|
353 | PORT controller_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external |
---|
354 | PORT controller_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external |
---|
355 | PORT controller_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external |
---|
356 | PORT controller_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external |
---|
357 | PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data |
---|
358 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs |
---|
359 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk |
---|
360 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk |
---|
361 | PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data |
---|
362 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs |
---|
363 | PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN |
---|
364 | PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn |
---|
365 | PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn |
---|
366 | PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP |
---|
367 | PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA |
---|
368 | PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA |
---|
369 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW |
---|
370 | PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED |
---|
371 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS |
---|
372 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS |
---|
373 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA |
---|
374 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB |
---|
375 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW |
---|
376 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk |
---|
377 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP |
---|
378 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ |
---|
379 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP |
---|
380 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D |
---|
381 | PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD |
---|
382 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA |
---|
383 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB |
---|
384 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR |
---|
385 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK |
---|
386 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_2_radio_dac_RESET |
---|
387 | PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T |
---|
388 | PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O |
---|
389 | PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I |
---|
390 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO |
---|
391 | PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I |
---|
392 | PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q |
---|
393 | PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I |
---|
394 | PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q |
---|
395 | PORT user_TxModelStart = radio2_txStart |
---|
396 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
397 | PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
398 | PORT converter_clock_in = clk_40MHz |
---|
399 | PORT user_RxHP_external = agc_rxhp_b |
---|
400 | PORT user_RxBB_gain = agc_g_bb_b |
---|
401 | PORT user_RxRF_gain = agc_g_rf_b |
---|
402 | END |
---|
403 | |
---|
404 | BEGIN radio_bridge |
---|
405 | PARAMETER INSTANCE = radio_bridge_slot_3 |
---|
406 | PARAMETER HW_VER = 1.22.a |
---|
407 | PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out |
---|
408 | PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B |
---|
409 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I |
---|
410 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q |
---|
411 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I |
---|
412 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q |
---|
413 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk |
---|
414 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk |
---|
415 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out |
---|
416 | PORT controller_radio_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs |
---|
417 | PORT controller_dac_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs |
---|
418 | PORT controller_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN |
---|
419 | PORT controller_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn |
---|
420 | PORT controller_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn |
---|
421 | PORT controller_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP |
---|
422 | PORT controller_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA |
---|
423 | PORT controller_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA |
---|
424 | PORT controller_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW |
---|
425 | PORT controller_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED |
---|
426 | PORT controller_RX_ADC_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS |
---|
427 | PORT controller_RX_ADC_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS |
---|
428 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA |
---|
429 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB |
---|
430 | PORT controller_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW |
---|
431 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP |
---|
432 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ |
---|
433 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP |
---|
434 | PORT controller_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D |
---|
435 | PORT controller_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD |
---|
436 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA |
---|
437 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB |
---|
438 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR |
---|
439 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK |
---|
440 | PORT controller_dac_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET |
---|
441 | PORT user_Tx_gain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain |
---|
442 | PORT controller_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart |
---|
443 | PORT controller_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external |
---|
444 | PORT controller_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external |
---|
445 | PORT controller_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external |
---|
446 | PORT controller_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external |
---|
447 | PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data |
---|
448 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs |
---|
449 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk |
---|
450 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk |
---|
451 | PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data |
---|
452 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs |
---|
453 | PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN |
---|
454 | PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn |
---|
455 | PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn |
---|
456 | PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP |
---|
457 | PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA |
---|
458 | PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA |
---|
459 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW |
---|
460 | PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED |
---|
461 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS |
---|
462 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS |
---|
463 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA |
---|
464 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB |
---|
465 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW |
---|
466 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk |
---|
467 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP |
---|
468 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ |
---|
469 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP |
---|
470 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D |
---|
471 | PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD |
---|
472 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA |
---|
473 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB |
---|
474 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR |
---|
475 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK |
---|
476 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_3_radio_dac_RESET |
---|
477 | PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T |
---|
478 | PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O |
---|
479 | PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I |
---|
480 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO |
---|
481 | PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I |
---|
482 | PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q |
---|
483 | PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I |
---|
484 | PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q |
---|
485 | PORT user_TxModelStart = radio3_txStart |
---|
486 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
487 | PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
488 | PORT converter_clock_in = clk_40MHz |
---|
489 | PORT user_RxHP_external = agc_rxhp_c |
---|
490 | PORT user_RxBB_gain = agc_g_bb_c |
---|
491 | PORT user_RxRF_gain = agc_g_rf_c |
---|
492 | END |
---|
493 | |
---|
494 | BEGIN eeprom |
---|
495 | PARAMETER INSTANCE = eeprom_controller |
---|
496 | PARAMETER HW_VER = 1.07.a |
---|
497 | PARAMETER C_MEM0_BASEADDR = 0xc5400000 |
---|
498 | PARAMETER C_MEM0_HIGHADDR = 0xc540ffff |
---|
499 | BUS_INTERFACE SPLB = plb |
---|
500 | PORT DQ0 = fpga_0_eeprom_controller_DQ0 |
---|
501 | PORT DQ1_I = net_vcc |
---|
502 | PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T |
---|
503 | PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O |
---|
504 | PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I |
---|
505 | PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T |
---|
506 | PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O |
---|
507 | PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I |
---|
508 | PORT DQ4_I = net_vcc |
---|
509 | PORT DQ5_I = net_vcc |
---|
510 | PORT DQ6_I = net_vcc |
---|
511 | PORT DQ7_I = net_vcc |
---|
512 | END |
---|
513 | |
---|
514 | BEGIN isocm_v10 |
---|
515 | PARAMETER INSTANCE = ppc405_0_iocm |
---|
516 | PARAMETER HW_VER = 2.00.b |
---|
517 | PARAMETER C_ISCNTLVALUE = 0xa5 |
---|
518 | PORT ISOCM_Clk = sys_clk_s |
---|
519 | PORT sys_rst = sys_bus_reset |
---|
520 | END |
---|
521 | |
---|
522 | BEGIN isbram_if_cntlr |
---|
523 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr |
---|
524 | PARAMETER HW_VER = 3.00.b |
---|
525 | PARAMETER C_BASEADDR = 0xffff0000 |
---|
526 | PARAMETER C_HIGHADDR = 0xffffffff |
---|
527 | BUS_INTERFACE ISOCM = ppc405_0_iocm |
---|
528 | BUS_INTERFACE DCR_WRITE_PORT = isocm_porta |
---|
529 | BUS_INTERFACE INSTRN_READ_PORT = isocm_portb |
---|
530 | END |
---|
531 | |
---|
532 | BEGIN bram_block |
---|
533 | PARAMETER INSTANCE = isocm_bram |
---|
534 | PARAMETER HW_VER = 1.00.a |
---|
535 | BUS_INTERFACE PORTA = isocm_porta |
---|
536 | BUS_INTERFACE PORTB = isocm_portb |
---|
537 | END |
---|
538 | |
---|
539 | BEGIN dsocm_v10 |
---|
540 | PARAMETER INSTANCE = ppc405_0_docm |
---|
541 | PARAMETER HW_VER = 2.00.b |
---|
542 | PARAMETER C_DSCNTLVALUE = 0xa5 |
---|
543 | PORT DSOCM_Clk = sys_clk_s |
---|
544 | PORT sys_rst = sys_bus_reset |
---|
545 | END |
---|
546 | |
---|
547 | BEGIN dsbram_if_cntlr |
---|
548 | PARAMETER INSTANCE = ppc405_0_docm_cntlr |
---|
549 | PARAMETER HW_VER = 3.00.b |
---|
550 | PARAMETER C_BASEADDR = 0x40800000 |
---|
551 | PARAMETER C_HIGHADDR = 0x40807fff |
---|
552 | BUS_INTERFACE DSOCM = ppc405_0_docm |
---|
553 | BUS_INTERFACE PORTA = dsocm_porta |
---|
554 | END |
---|
555 | |
---|
556 | BEGIN bram_block |
---|
557 | PARAMETER INSTANCE = dsocm_bram |
---|
558 | PARAMETER HW_VER = 1.00.a |
---|
559 | BUS_INTERFACE PORTA = dsocm_porta |
---|
560 | END |
---|
561 | |
---|
562 | BEGIN clock_generator |
---|
563 | PARAMETER INSTANCE = clock_generator_0 |
---|
564 | PARAMETER HW_VER = 2.01.a |
---|
565 | PARAMETER C_EXT_RESET_HIGH = 1 |
---|
566 | PARAMETER C_CLKIN_FREQ = 40000000 |
---|
567 | PARAMETER C_CLKOUT0_FREQ = 80000000 |
---|
568 | PARAMETER C_CLKOUT0_BUF = TRUE |
---|
569 | PARAMETER C_CLKOUT0_PHASE = 0 |
---|
570 | PARAMETER C_CLKOUT0_GROUP = DCM0 |
---|
571 | PARAMETER C_CLKOUT1_FREQ = 240000000 |
---|
572 | PARAMETER C_CLKOUT1_BUF = TRUE |
---|
573 | PARAMETER C_CLKOUT1_PHASE = 0 |
---|
574 | PARAMETER C_CLKOUT1_GROUP = DCM0 |
---|
575 | PARAMETER C_CLKOUT2_FREQ = 40000000 |
---|
576 | PARAMETER C_CLKOUT2_PHASE = 0 |
---|
577 | PARAMETER C_CLKOUT2_GROUP = NONE |
---|
578 | PARAMETER C_CLKOUT2_BUF = TRUE |
---|
579 | PARAMETER C_CLKOUT3_FREQ = 40000000 |
---|
580 | PARAMETER C_CLKOUT3_PHASE = 0 |
---|
581 | PARAMETER C_CLKOUT3_GROUP = DCM0 |
---|
582 | PARAMETER C_CLKOUT3_BUF = TRUE |
---|
583 | PORT CLKOUT0 = sys_clk_s |
---|
584 | PORT CLKOUT1 = proc_clk_s |
---|
585 | PORT CLKOUT2 = clk_40MHz |
---|
586 | PORT CLKOUT3 = clk_40MHz_90 |
---|
587 | PORT CLKIN = dcm_clk_s |
---|
588 | PORT LOCKED = Dcm_all_locked |
---|
589 | PORT RST = clk_board_config_config_invalid |
---|
590 | END |
---|
591 | |
---|
592 | BEGIN jtagppc_cntlr |
---|
593 | PARAMETER INSTANCE = jtagppc_cntlr_0 |
---|
594 | PARAMETER HW_VER = 2.01.c |
---|
595 | BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0 |
---|
596 | END |
---|
597 | |
---|
598 | BEGIN proc_sys_reset |
---|
599 | PARAMETER INSTANCE = proc_sys_reset_0 |
---|
600 | PARAMETER HW_VER = 2.00.a |
---|
601 | PARAMETER C_EXT_RESET_HIGH = 1 |
---|
602 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus |
---|
603 | PORT Slowest_sync_clk = clk_40MHz |
---|
604 | PORT Dcm_locked = Dcm_all_locked |
---|
605 | PORT Ext_Reset_In = sys_rst_s |
---|
606 | PORT Bus_Struct_Reset = sys_bus_reset |
---|
607 | END |
---|
608 | |
---|
609 | # PORT Peripheral_Reset = sys_periph_reset |
---|
610 | BEGIN xps_ethernetlite |
---|
611 | PARAMETER INSTANCE = xps_ethernetlite_0 |
---|
612 | PARAMETER HW_VER = 2.00.b |
---|
613 | PARAMETER C_BASEADDR = 0x81000000 |
---|
614 | PARAMETER C_HIGHADDR = 0x8100ffff |
---|
615 | BUS_INTERFACE SPLB = plb |
---|
616 | PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n |
---|
617 | PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs |
---|
618 | PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col |
---|
619 | PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data |
---|
620 | PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en |
---|
621 | PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk |
---|
622 | PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er |
---|
623 | PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk |
---|
624 | PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv |
---|
625 | PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data |
---|
626 | END |
---|
627 | |
---|
628 | BEGIN warplab_mimo_4x4_plbw |
---|
629 | PARAMETER INSTANCE = warplab_mimo_4x4_plbw_0 |
---|
630 | PARAMETER HW_VER = 1.04.a |
---|
631 | PARAMETER C_BASEADDR = 0xc4c00000 |
---|
632 | PARAMETER C_HIGHADDR = 0xc4ffffff |
---|
633 | BUS_INTERFACE SPLB = plb_v46_40MHz |
---|
634 | PORT sysgen_clk = clk_40MHz |
---|
635 | PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I |
---|
636 | PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q |
---|
637 | PORT radio2_adc_i_otr = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA |
---|
638 | PORT radio2_adc_q_otr = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB |
---|
639 | PORT startcapture = net_gnd |
---|
640 | PORT StartTx = net_gnd |
---|
641 | PORT StopTx = net_gnd |
---|
642 | PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I |
---|
643 | PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q |
---|
644 | PORT rssi_adc_clk = rssi_clk_out |
---|
645 | PORT debug_capturing = rxrun |
---|
646 | PORT debug_transmitting = txrun |
---|
647 | PORT debug_agc_done = agcsetdone |
---|
648 | PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I |
---|
649 | PORT radio3_adc_i_otr = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA |
---|
650 | PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q |
---|
651 | PORT radio3_adc_q_otr = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB |
---|
652 | PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I |
---|
653 | PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q |
---|
654 | PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
655 | PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
656 | PORT agc_done = agc_is_done |
---|
657 | PORT fromagc_radio2_i = dc_filtered_i_b |
---|
658 | PORT fromagc_radio2_q = dc_filtered_q_b |
---|
659 | PORT fromagc_radio3_i = dc_filtered_i_c |
---|
660 | PORT fromagc_radio3_q = dc_filtered_q_c |
---|
661 | END |
---|
662 | |
---|
663 | BEGIN warplab_mimo_4x4_agc_plbw |
---|
664 | PARAMETER INSTANCE = warplab_mimo_4x4_agc_plbw_0 |
---|
665 | PARAMETER HW_VER = 2.00.a |
---|
666 | PARAMETER C_BASEADDR = 0xc4a00000 |
---|
667 | PARAMETER C_HIGHADDR = 0xc4a0ffff |
---|
668 | BUS_INTERFACE SPLB = plb_v46_40MHz |
---|
669 | PORT sysgen_clk = clk_40MHz |
---|
670 | PORT rxhp_d = agc_rxhp_d |
---|
671 | PORT rxhp_c = agc_rxhp_c |
---|
672 | PORT rxhp_b = agc_rxhp_b |
---|
673 | PORT rxhp_a = agc_rxhp_a |
---|
674 | PORT g_rf_d = agc_g_rf_d |
---|
675 | PORT g_rf_c = agc_g_rf_c |
---|
676 | PORT g_rf_b = agc_g_rf_b |
---|
677 | PORT g_rf_a = agc_g_rf_a |
---|
678 | PORT g_bb_d = agc_g_bb_d |
---|
679 | PORT g_bb_c = agc_g_bb_c |
---|
680 | PORT g_bb_b = agc_g_bb_b |
---|
681 | PORT g_bb_a = agc_g_bb_a |
---|
682 | PORT agc_done = agc_is_done |
---|
683 | PORT rssi_in_d = net_gnd |
---|
684 | PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
685 | PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
686 | PORT rssi_in_a = net_gnd |
---|
687 | PORT reset_in = net_gnd |
---|
688 | PORT q_in_d = net_gnd |
---|
689 | PORT q_in_c = radio_bridge_slot_3_user_ADC_Q |
---|
690 | PORT q_in_b = radio_bridge_slot_2_user_ADC_Q |
---|
691 | PORT q_in_a = net_gnd |
---|
692 | PORT packet_in = net_gnd |
---|
693 | PORT mreset_in = net_gnd |
---|
694 | PORT i_in_d = net_gnd |
---|
695 | PORT i_in_c = radio_bridge_slot_3_user_ADC_I |
---|
696 | PORT i_in_b = radio_bridge_slot_2_user_ADC_I |
---|
697 | PORT i_in_a = net_gnd |
---|
698 | PORT i_out_a = dc_filtered_i_a |
---|
699 | PORT i_out_b = dc_filtered_i_b |
---|
700 | PORT i_out_c = dc_filtered_i_c |
---|
701 | PORT i_out_d = dc_filtered_i_d |
---|
702 | PORT q_out_a = dc_filtered_q_a |
---|
703 | PORT q_out_b = dc_filtered_q_b |
---|
704 | PORT q_out_c = dc_filtered_q_c |
---|
705 | PORT q_out_d = dc_filtered_q_d |
---|
706 | END |
---|
707 | |
---|
708 | # PORT q_out_d = dc_filtered_q_d |
---|
709 | BEGIN plbv46_plbv46_bridge |
---|
710 | PARAMETER INSTANCE = plbv46_plbv46_bridge_0 |
---|
711 | PARAMETER HW_VER = 1.01.a |
---|
712 | PARAMETER C_BUS_CLOCK_RATIO = 2 |
---|
713 | PARAMETER C_NUM_ADDR_RNG = 2 |
---|
714 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000 |
---|
715 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff |
---|
716 | PARAMETER C_RNG0_BASEADDR = 0xc4800000 |
---|
717 | PARAMETER C_RNG0_HIGHADDR = 0xc4ffffff |
---|
718 | PARAMETER C_RNG1_BASEADDR = 0xcac00000 |
---|
719 | PARAMETER C_RNG1_HIGHADDR = 0xcac0ffff |
---|
720 | BUS_INTERFACE SPLB = plb |
---|
721 | BUS_INTERFACE MPLB = plb_v46_40MHz |
---|
722 | END |
---|
723 | |
---|
724 | BEGIN plb_v46 |
---|
725 | PARAMETER INSTANCE = plb_v46_40MHz |
---|
726 | PARAMETER HW_VER = 1.03.a |
---|
727 | PORT PLB_Clk = clk_40MHz |
---|
728 | PORT SYS_Rst = sys_bus_reset |
---|
729 | END |
---|
730 | |
---|
731 | BEGIN xps_gpio |
---|
732 | PARAMETER INSTANCE = debug_sw_gpio |
---|
733 | PARAMETER HW_VER = 1.00.a |
---|
734 | PARAMETER C_GPIO_WIDTH = 8 |
---|
735 | PARAMETER C_IS_BIDIR = 0 |
---|
736 | PARAMETER C_BASEADDR = 0x81400000 |
---|
737 | PARAMETER C_HIGHADDR = 0x8140ffff |
---|
738 | BUS_INTERFACE SPLB = plb |
---|
739 | PORT GPIO_d_out = debug_sw_gpio_O |
---|
740 | END |
---|
741 | |
---|
742 | BEGIN util_flipflop |
---|
743 | PARAMETER INSTANCE = util_flipflop_0 |
---|
744 | PARAMETER HW_VER = 1.10.a |
---|
745 | PARAMETER C_USE_RST = 0 |
---|
746 | PARAMETER C_USE_SET = 0 |
---|
747 | PARAMETER C_SET_RST_HIGH = 0 |
---|
748 | PARAMETER C_USE_CE = 0 |
---|
749 | PARAMETER C_USE_ASYNCH = 0 |
---|
750 | PARAMETER C_SIZE = 2 |
---|
751 | PORT Clk = sys_clk_s |
---|
752 | PORT D = fpga_0_Ethernet_MAC_PHY_dv & fpga_0_Ethernet_MAC_PHY_tx_en |
---|
753 | PORT Q = ff_fpga_0_Ethernet_MAC_PHY_ensigs |
---|
754 | END |
---|
755 | |
---|
756 | BEGIN mgt_null_controller |
---|
757 | PARAMETER INSTANCE = mgt_null_controller_0 |
---|
758 | PARAMETER HW_VER = 1.02.a |
---|
759 | PORT grefclk = fpga_0_clk_board_config_sys_clk |
---|
760 | PORT rxn_mgt01 = mgt_null_controller_0_rxn_mgt01 |
---|
761 | PORT rxp_mgt01 = mgt_null_controller_0_rxp_mgt01 |
---|
762 | PORT txn_mgt01 = mgt_null_controller_0_txn_mgt01 |
---|
763 | PORT txp_mgt01 = mgt_null_controller_0_txp_mgt01 |
---|
764 | PORT rxn_mgt02 = mgt_null_controller_0_rxn_mgt02 |
---|
765 | PORT rxp_mgt02 = mgt_null_controller_0_rxp_mgt02 |
---|
766 | PORT txn_mgt02 = mgt_null_controller_0_txn_mgt02 |
---|
767 | PORT txp_mgt02 = mgt_null_controller_0_txp_mgt02 |
---|
768 | PORT rxn_mgt03 = mgt_null_controller_0_rxn_mgt03 |
---|
769 | PORT rxp_mgt03 = mgt_null_controller_0_rxp_mgt03 |
---|
770 | PORT txn_mgt03 = mgt_null_controller_0_txn_mgt03 |
---|
771 | PORT txp_mgt03 = mgt_null_controller_0_txp_mgt03 |
---|
772 | PORT rxn_mgt05 = mgt_null_controller_0_rxn_mgt05 |
---|
773 | PORT rxp_mgt05 = mgt_null_controller_0_rxp_mgt05 |
---|
774 | PORT txn_mgt05 = mgt_null_controller_0_txn_mgt05 |
---|
775 | PORT txp_mgt05 = mgt_null_controller_0_txp_mgt05 |
---|
776 | PORT rxn_mgt06 = mgt_null_controller_0_rxn_mgt06 |
---|
777 | PORT rxp_mgt06 = mgt_null_controller_0_rxp_mgt06 |
---|
778 | PORT txn_mgt06 = mgt_null_controller_0_txn_mgt06 |
---|
779 | PORT txp_mgt06 = mgt_null_controller_0_txp_mgt06 |
---|
780 | PORT rxn_mgt09 = mgt_null_controller_0_rxn_mgt09 |
---|
781 | PORT rxp_mgt09 = mgt_null_controller_0_rxp_mgt09 |
---|
782 | PORT txn_mgt09 = mgt_null_controller_0_txn_mgt09 |
---|
783 | PORT txp_mgt09 = mgt_null_controller_0_txp_mgt09 |
---|
784 | PORT rxn_mgt10 = mgt_null_controller_0_rxn_mgt10 |
---|
785 | PORT rxp_mgt10 = mgt_null_controller_0_rxp_mgt10 |
---|
786 | PORT txn_mgt10 = mgt_null_controller_0_txn_mgt10 |
---|
787 | PORT txp_mgt10 = mgt_null_controller_0_txp_mgt10 |
---|
788 | PORT rxn_mgt12 = mgt_null_controller_0_rxn_mgt12 |
---|
789 | PORT rxp_mgt12 = mgt_null_controller_0_rxp_mgt12 |
---|
790 | PORT txn_mgt12 = mgt_null_controller_0_txn_mgt12 |
---|
791 | PORT txp_mgt12 = mgt_null_controller_0_txp_mgt12 |
---|
792 | PORT rxn_mgt13 = mgt_null_controller_0_rxn_mgt13 |
---|
793 | PORT rxp_mgt13 = mgt_null_controller_0_rxp_mgt13 |
---|
794 | PORT txn_mgt13 = mgt_null_controller_0_txn_mgt13 |
---|
795 | PORT txp_mgt13 = mgt_null_controller_0_txp_mgt13 |
---|
796 | PORT rxn_mgt14 = mgt_null_controller_0_rxn_mgt14 |
---|
797 | PORT rxp_mgt14 = mgt_null_controller_0_rxp_mgt14 |
---|
798 | PORT txn_mgt14 = mgt_null_controller_0_txn_mgt14 |
---|
799 | PORT txp_mgt14 = mgt_null_controller_0_txp_mgt14 |
---|
800 | END |
---|
801 | |
---|