[1311] | 1 | ############################################################################
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| 2 | ## This system.ucf file is generated by Base System Builder based on the
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| 3 | ## settings in the selected Xilinx Board Definition file. Please add other
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| 4 | ## user constraints to this file based on customer design specifications.
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| 5 | ############################################################################
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| 6 |
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| 7 | Net sys_clk_pin LOC=AT20;
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| 8 | Net sys_clk_pin IOSTANDARD = LVTTL;
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| 9 | Net sys_rst_pin LOC=AM16;
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| 10 | Net sys_rst_pin IOSTANDARD = LVTTL;
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| 11 | ## System level constraints
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| 12 | Net sys_clk_pin TNM_NET = sys_clk_pin;
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| 13 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps;
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| 14 | Net sys_rst_pin TIG;
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| 15 | NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP";
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| 16 | NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP";
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| 17 | NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP";
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| 18 | TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
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| 19 |
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| 20 | ## IO Devices constraints
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| 21 |
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| 22 | #Debug header LOC constraints (manually entered)
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| 23 | NET "debug<0>" LOC = "K28" | IOSTANDARD = LVTTL; #pin 0
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| 24 | NET "debug<1>" LOC = "G30" | IOSTANDARD = LVTTL; #pin 1
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| 25 | NET "debug<2>" LOC = "H29" | IOSTANDARD = LVTTL; #pin 2
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[1420] | 26 | NET "debug<3>" LOC = "H30" | IOSTANDARD = LVTTL; #pin 3
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| 27 | NET "debug<4>" LOC = "J28" | IOSTANDARD = LVTTL; #pin 4
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| 28 | NET "debug<5>" LOC = "F30" | IOSTANDARD = LVTTL; #pin 5
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| 29 | NET "debug<6>" LOC = "E29" | IOSTANDARD = LVTTL; #pin 6
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| 30 | NET "debug<7>" LOC = "D30" | IOSTANDARD = LVTTL; #pin 7
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| 31 | NET "debug<8>" LOC = "K30" | IOSTANDARD = LVTTL; #pin 8
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| 32 | NET "debug<9>" LOC = "J30" | IOSTANDARD = LVTTL; #pin 9
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| 33 | NET "debug<10>" LOC = "K29" | IOSTANDARD = LVTTL; #pin 10
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| 34 | NET "debug<11>" LOC = "J29" | IOSTANDARD = LVTTL; #pin 11
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| 35 | NET "debug<12>" LOC = "G29" | IOSTANDARD = LVTTL; #pin 12
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| 36 | NET "debug<13>" LOC = "H28" | IOSTANDARD = LVTTL; #pin 13
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| 37 | NET "debug<14>" LOC = "F29" | IOSTANDARD = LVTTL; #pin 14
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| 38 | NET "debug<15>" LOC = "E30" | IOSTANDARD = LVTTL; #pin 15
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[1311] | 39 |
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| 40 | #### Module USER_IO constraints
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| 41 |
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| 42 | Net fpga_0_USER_IO_GPIO_in_pin<0> LOC=Y27;
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| 43 | Net fpga_0_USER_IO_GPIO_in_pin<0> IOSTANDARD = LVTTL;
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| 44 | Net fpga_0_USER_IO_GPIO_in_pin<1> LOC=Y28;
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| 45 | Net fpga_0_USER_IO_GPIO_in_pin<1> IOSTANDARD = LVTTL;
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| 46 | Net fpga_0_USER_IO_GPIO_in_pin<2> LOC=AA27;
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| 47 | Net fpga_0_USER_IO_GPIO_in_pin<2> IOSTANDARD = LVTTL;
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| 48 | Net fpga_0_USER_IO_GPIO_in_pin<3> LOC=Y29;
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| 49 | Net fpga_0_USER_IO_GPIO_in_pin<3> IOSTANDARD = LVTTL;
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| 50 | Net fpga_0_USER_IO_GPIO_in_pin<4> LOC=AJ22;
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| 51 | Net fpga_0_USER_IO_GPIO_in_pin<4> IOSTANDARD = LVTTL;
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| 52 | Net fpga_0_USER_IO_GPIO_in_pin<5> LOC=AJ15;
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| 53 | Net fpga_0_USER_IO_GPIO_in_pin<5> IOSTANDARD = LVTTL;
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| 54 | Net fpga_0_USER_IO_GPIO_in_pin<6> LOC=AG18;
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| 55 | Net fpga_0_USER_IO_GPIO_in_pin<6> IOSTANDARD = LVTTL;
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| 56 | Net fpga_0_USER_IO_GPIO_in_pin<7> LOC=AG17;
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| 57 | Net fpga_0_USER_IO_GPIO_in_pin<7> IOSTANDARD = LVTTL;
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| 58 | Net fpga_0_USER_IO_GPIO2_d_out_pin<0> LOC=AJ26;
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| 59 | Net fpga_0_USER_IO_GPIO2_d_out_pin<0> IOSTANDARD = LVTTL;
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| 60 | Net fpga_0_USER_IO_GPIO2_d_out_pin<1> LOC=AH26;
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| 61 | Net fpga_0_USER_IO_GPIO2_d_out_pin<1> IOSTANDARD = LVTTL;
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| 62 | Net fpga_0_USER_IO_GPIO2_d_out_pin<2> LOC=AH24;
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| 63 | Net fpga_0_USER_IO_GPIO2_d_out_pin<2> IOSTANDARD = LVTTL;
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| 64 | Net fpga_0_USER_IO_GPIO2_d_out_pin<3> LOC=AH25;
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| 65 | Net fpga_0_USER_IO_GPIO2_d_out_pin<3> IOSTANDARD = LVTTL;
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| 66 | Net fpga_0_USER_IO_GPIO2_d_out_pin<4> LOC=AH23;
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| 67 | Net fpga_0_USER_IO_GPIO2_d_out_pin<4> IOSTANDARD = LVTTL;
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| 68 | Net fpga_0_USER_IO_GPIO2_d_out_pin<5> LOC=AG22;
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| 69 | Net fpga_0_USER_IO_GPIO2_d_out_pin<5> IOSTANDARD = LVTTL;
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| 70 | Net fpga_0_USER_IO_GPIO2_d_out_pin<6> LOC=AG23;
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| 71 | Net fpga_0_USER_IO_GPIO2_d_out_pin<6> IOSTANDARD = LVTTL;
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| 72 | Net fpga_0_USER_IO_GPIO2_d_out_pin<7> LOC=AG19;
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| 73 | Net fpga_0_USER_IO_GPIO2_d_out_pin<7> IOSTANDARD = LVTTL;
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| 74 | Net fpga_0_USER_IO_GPIO2_d_out_pin<8> LOC=AG21;
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| 75 | Net fpga_0_USER_IO_GPIO2_d_out_pin<8> IOSTANDARD = LVTTL;
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| 76 | Net fpga_0_USER_IO_GPIO2_d_out_pin<9> LOC=AH19;
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| 77 | Net fpga_0_USER_IO_GPIO2_d_out_pin<9> IOSTANDARD = LVTTL;
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| 78 | Net fpga_0_USER_IO_GPIO2_d_out_pin<10> LOC=AJ19;
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| 79 | Net fpga_0_USER_IO_GPIO2_d_out_pin<10> IOSTANDARD = LVTTL;
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| 80 | Net fpga_0_USER_IO_GPIO2_d_out_pin<11> LOC=AP12;
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| 81 | Net fpga_0_USER_IO_GPIO2_d_out_pin<11> IOSTANDARD = LVTTL;
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| 82 | Net fpga_0_USER_IO_GPIO2_d_out_pin<12> LOC=AN13;
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| 83 | Net fpga_0_USER_IO_GPIO2_d_out_pin<12> IOSTANDARD = LVTTL;
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| 84 | Net fpga_0_USER_IO_GPIO2_d_out_pin<13> LOC=AL15;
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| 85 | Net fpga_0_USER_IO_GPIO2_d_out_pin<13> IOSTANDARD = LVTTL;
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| 86 | Net fpga_0_USER_IO_GPIO2_d_out_pin<14> LOC=AJ14;
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| 87 | Net fpga_0_USER_IO_GPIO2_d_out_pin<14> IOSTANDARD = LVTTL;
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| 88 | Net fpga_0_USER_IO_GPIO2_d_out_pin<15> LOC=AM13;
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| 89 | Net fpga_0_USER_IO_GPIO2_d_out_pin<15> IOSTANDARD = LVTTL;
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| 90 | Net fpga_0_USER_IO_GPIO2_d_out_pin<16> LOC=AR12;
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| 91 | Net fpga_0_USER_IO_GPIO2_d_out_pin<16> IOSTANDARD = LVTTL;
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| 92 | Net fpga_0_USER_IO_GPIO2_d_out_pin<17> LOC=AH13;
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| 93 | Net fpga_0_USER_IO_GPIO2_d_out_pin<17> IOSTANDARD = LVTTL;
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| 94 |
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| 95 | #### Module rs232 constraints
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| 96 |
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| 97 | Net fpga_0_rs232_RX_pin LOC=AA29;
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| 98 | Net fpga_0_rs232_RX_pin IOSTANDARD = LVTTL;
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| 99 | Net fpga_0_rs232_TX_pin LOC=AA28;
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| 100 | Net fpga_0_rs232_TX_pin IOSTANDARD = LVTTL;
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| 101 |
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| 102 | #### Module clk_board_config constraints
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| 103 |
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| 104 | Net fpga_0_clk_board_config_sys_clk_pin LOC=AH21;
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| 105 | Net fpga_0_clk_board_config_sys_clk_pin IOSTANDARD = LVTTL;
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| 106 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN25;
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| 107 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin IOSTANDARD=LVTTL;
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| 108 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin SLEW = SLOW;
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| 109 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AK26;
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| 110 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin IOSTANDARD=LVTTL;
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| 111 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin SLEW = SLOW;
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| 112 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AJ25;
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| 113 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin IOSTANDARD=LVTTL;
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| 114 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin SLEW = SLOW;
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| 115 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AL26;
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| 116 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin IOSTANDARD=LVTTL;
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| 117 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin SLEW = SLOW;
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| 118 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AT27;
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| 119 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin IOSTANDARD=LVTTL;
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| 120 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin SLEW = SLOW;
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| 121 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AR27;
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| 122 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin IOSTANDARD=LVTTL;
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| 123 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin SLEW = SLOW;
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| 124 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AN27;
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| 125 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin IOSTANDARD=LVTTL;
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| 126 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin SLEW = SLOW;
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| 127 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AM27;
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| 128 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin IOSTANDARD=LVTTL;
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| 129 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin SLEW = SLOW;
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| 130 |
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| 131 | #### Module eeprom_controller constraints
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| 132 |
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| 133 | Net fpga_0_eeprom_controller_DQ0_pin LOC=AB28;
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| 134 | Net fpga_0_eeprom_controller_DQ0_pin IOSTANDARD = LVTTL;
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| 135 | Net fpga_0_eeprom_controller_DQ0_pin SLEW = SLOW;
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| 136 | Net fpga_0_eeprom_controller_DQ0_pin DRIVE = 8;
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| 137 |
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| 138 | #### Module Ethernet_MAC constraints
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| 139 |
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| 140 | Net fpga_0_Ethernet_MAC_slew1_pin LOC=H20;
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| 141 | Net fpga_0_Ethernet_MAC_slew1_pin IOSTANDARD = LVTTL;
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| 142 | Net fpga_0_Ethernet_MAC_slew1_pin SLEW = SLOW;
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| 143 | Net fpga_0_Ethernet_MAC_slew1_pin DRIVE = 8;
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| 144 | Net fpga_0_Ethernet_MAC_slew2_pin LOC=J22;
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| 145 | Net fpga_0_Ethernet_MAC_slew2_pin IOSTANDARD = LVTTL;
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| 146 | Net fpga_0_Ethernet_MAC_slew2_pin SLEW = SLOW;
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| 147 | Net fpga_0_Ethernet_MAC_slew2_pin DRIVE = 8;
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| 148 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J27;
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| 149 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin IOSTANDARD = LVTTL;
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| 150 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin SLEW = SLOW;
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| 151 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin DRIVE = 8;
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| 152 | Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=D29;
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| 153 | Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVTTL;
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| 154 | Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=J26;
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| 155 | Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVTTL;
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| 156 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=G26;
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| 157 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVTTL;
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| 158 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> SLEW = SLOW;
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| 159 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> DRIVE = 8;
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| 160 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=D26;
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| 161 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVTTL;
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| 162 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> SLEW = SLOW;
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| 163 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> DRIVE = 8;
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| 164 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=H23;
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| 165 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVTTL;
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| 166 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> SLEW = SLOW;
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| 167 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> DRIVE = 8;
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| 168 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=D22;
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| 169 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVTTL;
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| 170 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> SLEW = SLOW;
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| 171 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> DRIVE = 8;
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| 172 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=H22;
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| 173 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVTTL;
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| 174 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin SLEW = SLOW;
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| 175 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin DRIVE = 8;
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| 176 | Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=F20;
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| 177 | Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVTTL;
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| 178 | Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=F21;
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| 179 | Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVTTL;
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| 180 | Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=E24;
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| 181 | Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVTTL;
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| 182 | Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=F22;
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| 183 | Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVTTL;
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| 184 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=C22;
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| 185 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVTTL;
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| 186 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=E21;
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| 187 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVTTL;
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| 188 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C21;
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| 189 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVTTL;
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| 190 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=D23;
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| 191 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVTTL;
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| 192 |
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| 193 | #### Module radio_controller_0 constraints
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| 194 |
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| 195 |
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| 196 | #### Module radio_bridge_slot_1 constraints
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| 197 |
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| 198 | Net fpga_0_radio_bridge_slot_1_converter_clock_out_pin LOC=L2;
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| 199 | Net fpga_0_radio_bridge_slot_1_converter_clock_out_pin IOSTANDARD=LVTTL;
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| 200 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<0> LOC=P1;
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| 201 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<0> IOSTANDARD = LVTTL;
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| 202 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<0> SLEW = SLOW;
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| 203 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<1> LOC=P8;
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| 204 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<1> IOSTANDARD = LVTTL;
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| 205 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<1> SLEW = SLOW;
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| 206 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<2> LOC=P10;
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| 207 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<2> IOSTANDARD = LVTTL;
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| 208 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<2> SLEW = SLOW;
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| 209 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<3> LOC=N3;
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| 210 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<3> IOSTANDARD = LVTTL;
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| 211 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<3> SLEW = SLOW;
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| 212 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<4> LOC=P4;
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| 213 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<4> IOSTANDARD = LVTTL;
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| 214 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<4> SLEW = SLOW;
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| 215 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<5> LOC=K1;
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| 216 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<5> IOSTANDARD = LVTTL;
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| 217 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<5> SLEW = SLOW;
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| 218 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<6> LOC=K2;
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| 219 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<6> IOSTANDARD = LVTTL;
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| 220 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<6> SLEW = SLOW;
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| 221 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<0> LOC=E7;
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| 222 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
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| 223 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<0> PULLDOWN;
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| 224 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<1> LOC=J1;
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| 225 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
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| 226 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<1> PULLDOWN;
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| 227 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<2> LOC=E3;
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| 228 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
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| 229 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<2> PULLDOWN;
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| 230 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<3> LOC=M20;
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| 231 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
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| 232 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<3> PULLDOWN;
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| 233 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<4> LOC=D6;
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| 234 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
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| 235 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<4> PULLDOWN;
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| 236 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<5> LOC=K4;
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| 237 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
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| 238 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<5> PULLDOWN;
|
---|
| 239 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<6> LOC=E2;
|
---|
| 240 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 241 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<6> PULLDOWN;
|
---|
| 242 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<7> LOC=J7;
|
---|
| 243 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 244 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<7> PULLDOWN;
|
---|
| 245 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<8> LOC=H6;
|
---|
| 246 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 247 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<8> PULLDOWN;
|
---|
| 248 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<9> LOC=J2;
|
---|
| 249 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 250 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<9> PULLDOWN;
|
---|
| 251 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<10> LOC=K8;
|
---|
| 252 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 253 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<10> PULLDOWN;
|
---|
| 254 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<11> LOC=J6;
|
---|
| 255 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 256 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<11> PULLDOWN;
|
---|
| 257 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<12> LOC=J9;
|
---|
| 258 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 259 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<12> PULLDOWN;
|
---|
| 260 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<13> LOC=L9;
|
---|
| 261 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 262 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<13> PULLDOWN;
|
---|
| 263 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<0> LOC=M2;
|
---|
| 264 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 265 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<0> PULLDOWN;
|
---|
| 266 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<1> LOC=L3;
|
---|
| 267 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 268 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<1> PULLDOWN;
|
---|
| 269 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<2> LOC=M10;
|
---|
| 270 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 271 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<2> PULLDOWN;
|
---|
| 272 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<3> LOC=M4;
|
---|
| 273 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 274 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<3> PULLDOWN;
|
---|
| 275 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<4> LOC=K5;
|
---|
| 276 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 277 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<4> PULLDOWN;
|
---|
| 278 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<5> LOC=N7;
|
---|
| 279 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 280 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<5> PULLDOWN;
|
---|
| 281 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<6> LOC=L7;
|
---|
| 282 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 283 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<6> PULLDOWN;
|
---|
| 284 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<7> LOC=L1;
|
---|
| 285 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 286 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<7> PULLDOWN;
|
---|
| 287 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<8> LOC=J3;
|
---|
| 288 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 289 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<8> PULLDOWN;
|
---|
| 290 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<9> LOC=H4;
|
---|
| 291 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 292 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<9> PULLDOWN;
|
---|
| 293 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<10> LOC=H3;
|
---|
| 294 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 295 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<10> PULLDOWN;
|
---|
| 296 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<11> LOC=J5;
|
---|
| 297 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 298 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<11> PULLDOWN;
|
---|
| 299 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<12> LOC=G9;
|
---|
| 300 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 301 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<12> PULLDOWN;
|
---|
| 302 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<13> LOC=H9;
|
---|
| 303 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 304 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<13> PULLDOWN;
|
---|
| 305 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<0> LOC=Y3;
|
---|
| 306 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 307 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<1> LOC=W13;
|
---|
| 308 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 309 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<2> LOC=V13;
|
---|
| 310 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 311 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<3> LOC=W12;
|
---|
| 312 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 313 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<4> LOC=Y4;
|
---|
| 314 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 315 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<5> LOC=V12;
|
---|
| 316 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 317 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<6> LOC=W10;
|
---|
| 318 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 319 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<7> LOC=Y8;
|
---|
| 320 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 321 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<8> LOC=Y9;
|
---|
| 322 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 323 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<9> LOC=V11;
|
---|
| 324 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 325 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<10> LOC=V10;
|
---|
| 326 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 327 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<11> LOC=W11;
|
---|
| 328 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 329 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<12> LOC=W9;
|
---|
| 330 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 331 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<13> LOC=W8;
|
---|
| 332 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 333 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<14> LOC=T10;
|
---|
| 334 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
|
---|
| 335 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<15> LOC=U12;
|
---|
| 336 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
|
---|
| 337 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<0> LOC=U8;
|
---|
| 338 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 339 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<1> LOC=V7;
|
---|
| 340 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 341 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<2> LOC=R10;
|
---|
| 342 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 343 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<3> LOC=U5;
|
---|
| 344 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 345 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<4> LOC=T4;
|
---|
| 346 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 347 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<5> LOC=T3;
|
---|
| 348 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 349 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<6> LOC=U9;
|
---|
| 350 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 351 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<7> LOC=U4;
|
---|
| 352 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 353 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<8> LOC=T11;
|
---|
| 354 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 355 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<9> LOC=V6;
|
---|
| 356 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 357 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<10> LOC=U10;
|
---|
| 358 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 359 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<11> LOC=V9;
|
---|
| 360 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 361 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<12> LOC=V4;
|
---|
| 362 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 363 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<13> LOC=V8;
|
---|
| 364 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 365 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<14> LOC=V3;
|
---|
| 366 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
|
---|
| 367 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<15> LOC=W4;
|
---|
| 368 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
|
---|
| 369 | Net fpga_0_radio_bridge_slot_1_dac_spi_data_pin LOC=R8;
|
---|
| 370 | Net fpga_0_radio_bridge_slot_1_dac_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 371 | Net fpga_0_radio_bridge_slot_1_dac_spi_cs_pin LOC=T6;
|
---|
| 372 | Net fpga_0_radio_bridge_slot_1_dac_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 373 | Net fpga_0_radio_bridge_slot_1_dac_spi_clk_pin LOC=T7;
|
---|
| 374 | Net fpga_0_radio_bridge_slot_1_dac_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 375 | Net fpga_0_radio_bridge_slot_1_radio_spi_clk_pin LOC=P9;
|
---|
| 376 | Net fpga_0_radio_bridge_slot_1_radio_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 377 | Net fpga_0_radio_bridge_slot_1_radio_spi_data_pin LOC=R5;
|
---|
| 378 | Net fpga_0_radio_bridge_slot_1_radio_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 379 | Net fpga_0_radio_bridge_slot_1_radio_spi_cs_pin LOC=R3;
|
---|
| 380 | Net fpga_0_radio_bridge_slot_1_radio_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 381 | Net fpga_0_radio_bridge_slot_1_radio_SHDN_pin LOC=L5;
|
---|
| 382 | Net fpga_0_radio_bridge_slot_1_radio_SHDN_pin IOSTANDARD=LVTTL;
|
---|
| 383 | Net fpga_0_radio_bridge_slot_1_radio_SHDN_pin SLEW = SLOW;
|
---|
| 384 | Net fpga_0_radio_bridge_slot_1_radio_TxEn_pin LOC=R4;
|
---|
| 385 | Net fpga_0_radio_bridge_slot_1_radio_TxEn_pin IOSTANDARD=LVTTL;
|
---|
| 386 | Net fpga_0_radio_bridge_slot_1_radio_TxEn_pin SLEW = SLOW;
|
---|
| 387 | Net fpga_0_radio_bridge_slot_1_radio_RxEn_pin LOC=L4;
|
---|
| 388 | Net fpga_0_radio_bridge_slot_1_radio_RxEn_pin IOSTANDARD=LVTTL;
|
---|
| 389 | Net fpga_0_radio_bridge_slot_1_radio_RxEn_pin SLEW = SLOW;
|
---|
| 390 | Net fpga_0_radio_bridge_slot_1_radio_RxHP_pin LOC=M6;
|
---|
| 391 | Net fpga_0_radio_bridge_slot_1_radio_RxHP_pin IOSTANDARD=LVTTL;
|
---|
| 392 | Net fpga_0_radio_bridge_slot_1_radio_RxHP_pin SLEW = SLOW;
|
---|
| 393 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin LOC=E6;
|
---|
| 394 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin IOSTANDARD=LVTTL;
|
---|
| 395 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin SLEW = SLOW;
|
---|
| 396 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin DRIVE = 2;
|
---|
| 397 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin LOC=N10;
|
---|
| 398 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin IOSTANDARD=LVTTL;
|
---|
| 399 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin SLEW = SLOW;
|
---|
| 400 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin DRIVE = 2;
|
---|
| 401 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> LOC=D5;
|
---|
| 402 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 403 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> SLEW = SLOW;
|
---|
| 404 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> DRIVE = 2;
|
---|
| 405 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> LOC=K6;
|
---|
| 406 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 407 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> SLEW = SLOW;
|
---|
| 408 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> DRIVE = 2;
|
---|
| 409 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> LOC=F7;
|
---|
| 410 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> IOSTANDARD=LVTTL;
|
---|
| 411 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> SLEW = SLOW;
|
---|
| 412 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> DRIVE = 2;
|
---|
| 413 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> LOC=L8;
|
---|
| 414 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> IOSTANDARD=LVTTL;
|
---|
| 415 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> SLEW = SLOW;
|
---|
| 416 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> DRIVE = 2;
|
---|
| 417 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> LOC=H2;
|
---|
| 418 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> IOSTANDARD=LVTTL;
|
---|
| 419 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> SLEW = SLOW;
|
---|
| 420 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> DRIVE = 2;
|
---|
| 421 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin LOC=M7;
|
---|
| 422 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
|
---|
| 423 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin LOC=N2;
|
---|
| 424 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
|
---|
| 425 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin LOC=H8;
|
---|
| 426 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
|
---|
| 427 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin LOC=R11;
|
---|
| 428 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
|
---|
| 429 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<0> LOC=T2;
|
---|
| 430 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 431 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<1> LOC=P3;
|
---|
| 432 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 433 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<2> LOC=R1;
|
---|
| 434 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
|
---|
| 435 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<3> LOC=R2;
|
---|
| 436 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
|
---|
| 437 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin LOC=N1;
|
---|
| 438 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
|
---|
| 439 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin LOC=V2;
|
---|
| 440 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
|
---|
| 441 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin LOC=V1;
|
---|
| 442 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
|
---|
| 443 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin LOC=P7;
|
---|
| 444 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
|
---|
| 445 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> LOC=R9;
|
---|
| 446 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
|
---|
| 447 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> PULLDOWN;
|
---|
| 448 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> LOC=W3;
|
---|
| 449 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
|
---|
| 450 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> PULLDOWN;
|
---|
| 451 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> LOC=R6;
|
---|
| 452 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
|
---|
| 453 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> PULLDOWN;
|
---|
| 454 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> LOC=R7;
|
---|
| 455 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
|
---|
| 456 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> PULLDOWN;
|
---|
| 457 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> LOC=P5;
|
---|
| 458 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
|
---|
| 459 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> PULLDOWN;
|
---|
| 460 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> LOC=T12;
|
---|
| 461 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
|
---|
| 462 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> PULLDOWN;
|
---|
| 463 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> LOC=U6;
|
---|
| 464 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
|
---|
| 465 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> PULLDOWN;
|
---|
| 466 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> LOC=W6;
|
---|
| 467 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
|
---|
| 468 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> PULLDOWN;
|
---|
| 469 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> LOC=W7;
|
---|
| 470 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
|
---|
| 471 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> PULLDOWN;
|
---|
| 472 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> LOC=Y7;
|
---|
| 473 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
|
---|
| 474 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> PULLDOWN;
|
---|
| 475 | Net fpga_0_radio_bridge_slot_1_radio_LD_pin LOC=P6;
|
---|
| 476 | Net fpga_0_radio_bridge_slot_1_radio_LD_pin IOSTANDARD=LVTTL;
|
---|
| 477 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin LOC=H7;
|
---|
| 478 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
|
---|
| 479 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin LOC=K9;
|
---|
| 480 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
|
---|
| 481 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin LOC=T8;
|
---|
| 482 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
|
---|
| 483 | Net fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin LOC=V5;
|
---|
| 484 | Net fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
|
---|
| 485 | Net fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin LOC=U2;
|
---|
| 486 | Net fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin IOSTANDARD=LVTTL;
|
---|
| 487 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO LOC=K3;
|
---|
| 488 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO IOSTANDARD=LVTTL;
|
---|
| 489 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO SLEW = SLOW;
|
---|
| 490 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO DRIVE = 8;
|
---|
| 491 |
|
---|
| 492 | #### Module radio_bridge_slot_2 constraints
|
---|
| 493 |
|
---|
| 494 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AG2;
|
---|
| 495 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin IOSTANDARD=LVTTL;
|
---|
| 496 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AB7;
|
---|
| 497 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> IOSTANDARD = LVTTL;
|
---|
| 498 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> SLEW = SLOW;
|
---|
| 499 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AB8;
|
---|
| 500 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> IOSTANDARD = LVTTL;
|
---|
| 501 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> SLEW = SLOW;
|
---|
| 502 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=AC10;
|
---|
| 503 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> IOSTANDARD = LVTTL;
|
---|
| 504 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> SLEW = SLOW;
|
---|
| 505 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=AB9;
|
---|
| 506 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> IOSTANDARD = LVTTL;
|
---|
| 507 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> SLEW = SLOW;
|
---|
| 508 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AF3;
|
---|
| 509 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> IOSTANDARD = LVTTL;
|
---|
| 510 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> SLEW = SLOW;
|
---|
| 511 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=AL1;
|
---|
| 512 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> IOSTANDARD = LVTTL;
|
---|
| 513 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> SLEW = SLOW;
|
---|
| 514 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AE4;
|
---|
| 515 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> IOSTANDARD = LVTTL;
|
---|
| 516 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> SLEW = SLOW;
|
---|
| 517 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=AD4;
|
---|
| 518 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 519 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> PULLDOWN;
|
---|
| 520 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=AB11;
|
---|
| 521 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 522 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> PULLDOWN;
|
---|
| 523 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=AB10;
|
---|
| 524 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 525 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> PULLDOWN;
|
---|
| 526 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG20;
|
---|
| 527 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 528 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> PULLDOWN;
|
---|
| 529 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=AG1;
|
---|
| 530 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 531 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> PULLDOWN;
|
---|
| 532 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=AE3;
|
---|
| 533 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 534 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> PULLDOWN;
|
---|
| 535 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AC5;
|
---|
| 536 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 537 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> PULLDOWN;
|
---|
| 538 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=AE1;
|
---|
| 539 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 540 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> PULLDOWN;
|
---|
| 541 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AB5;
|
---|
| 542 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 543 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> PULLDOWN;
|
---|
| 544 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=AB4;
|
---|
| 545 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 546 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> PULLDOWN;
|
---|
| 547 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=AB6;
|
---|
| 548 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 549 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> PULLDOWN;
|
---|
| 550 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AD2;
|
---|
| 551 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 552 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> PULLDOWN;
|
---|
| 553 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=AA7;
|
---|
| 554 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 555 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> PULLDOWN;
|
---|
| 556 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=AB3;
|
---|
| 557 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 558 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> PULLDOWN;
|
---|
| 559 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AE7;
|
---|
| 560 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 561 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> PULLDOWN;
|
---|
| 562 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AC12;
|
---|
| 563 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 564 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> PULLDOWN;
|
---|
| 565 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AJ2;
|
---|
| 566 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 567 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> PULLDOWN;
|
---|
| 568 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AG5;
|
---|
| 569 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 570 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> PULLDOWN;
|
---|
| 571 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AJ1;
|
---|
| 572 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 573 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> PULLDOWN;
|
---|
| 574 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AH3;
|
---|
| 575 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 576 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> PULLDOWN;
|
---|
| 577 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AH4;
|
---|
| 578 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 579 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> PULLDOWN;
|
---|
| 580 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AJ3;
|
---|
| 581 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 582 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> PULLDOWN;
|
---|
| 583 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=AA10;
|
---|
| 584 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 585 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> PULLDOWN;
|
---|
| 586 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=AE2;
|
---|
| 587 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 588 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> PULLDOWN;
|
---|
| 589 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=AA12;
|
---|
| 590 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 591 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> PULLDOWN;
|
---|
| 592 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AF1;
|
---|
| 593 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 594 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> PULLDOWN;
|
---|
| 595 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=AD3;
|
---|
| 596 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 597 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> PULLDOWN;
|
---|
| 598 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=AF2;
|
---|
| 599 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 600 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> PULLDOWN;
|
---|
| 601 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AD13;
|
---|
| 602 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 603 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AT8;
|
---|
| 604 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 605 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AR8;
|
---|
| 606 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 607 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AT5;
|
---|
| 608 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 609 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AH11;
|
---|
| 610 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 611 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AT6;
|
---|
| 612 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 613 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AD12;
|
---|
| 614 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 615 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5;
|
---|
| 616 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 617 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AN9;
|
---|
| 618 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 619 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AE13;
|
---|
| 620 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 621 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AK9;
|
---|
| 622 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 623 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AR7;
|
---|
| 624 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 625 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AP7;
|
---|
| 626 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 627 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AF12;
|
---|
| 628 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 629 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AH10;
|
---|
| 630 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
|
---|
| 631 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AM6;
|
---|
| 632 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
|
---|
| 633 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AE10;
|
---|
| 634 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 635 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AH8;
|
---|
| 636 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 637 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AM4;
|
---|
| 638 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 639 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AL7;
|
---|
| 640 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 641 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AE11;
|
---|
| 642 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 643 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AL6;
|
---|
| 644 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 645 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AN6;
|
---|
| 646 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 647 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AK8;
|
---|
| 648 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 649 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AG9;
|
---|
| 650 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 651 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AM7;
|
---|
| 652 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 653 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AL9;
|
---|
| 654 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 655 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AE12;
|
---|
| 656 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 657 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AN7;
|
---|
| 658 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 659 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AH7;
|
---|
| 660 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 661 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AR6;
|
---|
| 662 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
|
---|
| 663 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AM8;
|
---|
| 664 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
|
---|
| 665 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AL5;
|
---|
| 666 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 667 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AJ6;
|
---|
| 668 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 669 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK6;
|
---|
| 670 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 671 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AL3;
|
---|
| 672 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 673 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AK4;
|
---|
| 674 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 675 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AF9;
|
---|
| 676 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 677 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AF5;
|
---|
| 678 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin IOSTANDARD=LVTTL;
|
---|
| 679 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin SLEW = SLOW;
|
---|
| 680 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=AM2;
|
---|
| 681 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin IOSTANDARD=LVTTL;
|
---|
| 682 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin SLEW = SLOW;
|
---|
| 683 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AD10;
|
---|
| 684 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin IOSTANDARD=LVTTL;
|
---|
| 685 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin SLEW = SLOW;
|
---|
| 686 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AE6;
|
---|
| 687 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin IOSTANDARD=LVTTL;
|
---|
| 688 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin SLEW = SLOW;
|
---|
| 689 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=AA9;
|
---|
| 690 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin IOSTANDARD=LVTTL;
|
---|
| 691 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin SLEW = SLOW;
|
---|
| 692 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin DRIVE = 2;
|
---|
| 693 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AB2;
|
---|
| 694 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin IOSTANDARD=LVTTL;
|
---|
| 695 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin SLEW = SLOW;
|
---|
| 696 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin DRIVE = 2;
|
---|
| 697 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=AB1;
|
---|
| 698 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 699 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> SLEW = SLOW;
|
---|
| 700 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> DRIVE = 2;
|
---|
| 701 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=AA6;
|
---|
| 702 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 703 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> SLEW = SLOW;
|
---|
| 704 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> DRIVE = 2;
|
---|
| 705 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA5;
|
---|
| 706 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> IOSTANDARD=LVTTL;
|
---|
| 707 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> SLEW = SLOW;
|
---|
| 708 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> DRIVE = 2;
|
---|
| 709 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=AA8;
|
---|
| 710 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> IOSTANDARD=LVTTL;
|
---|
| 711 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> SLEW = SLOW;
|
---|
| 712 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> DRIVE = 2;
|
---|
| 713 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=AC2;
|
---|
| 714 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> IOSTANDARD=LVTTL;
|
---|
| 715 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> SLEW = SLOW;
|
---|
| 716 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> DRIVE = 2;
|
---|
| 717 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AD8;
|
---|
| 718 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
|
---|
| 719 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AK1;
|
---|
| 720 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
|
---|
| 721 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=AA3;
|
---|
| 722 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
|
---|
| 723 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AF6;
|
---|
| 724 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
|
---|
| 725 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=AG7;
|
---|
| 726 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 727 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AL2;
|
---|
| 728 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 729 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=AJ4;
|
---|
| 730 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
|
---|
| 731 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AK3;
|
---|
| 732 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
|
---|
| 733 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AK2;
|
---|
| 734 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
|
---|
| 735 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AH6;
|
---|
| 736 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
|
---|
| 737 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AF8;
|
---|
| 738 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
|
---|
| 739 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AF7;
|
---|
| 740 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
|
---|
| 741 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AF11;
|
---|
| 742 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
|
---|
| 743 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> PULLDOWN;
|
---|
| 744 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AE8;
|
---|
| 745 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
|
---|
| 746 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> PULLDOWN;
|
---|
| 747 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AF10;
|
---|
| 748 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
|
---|
| 749 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> PULLDOWN;
|
---|
| 750 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AD11;
|
---|
| 751 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
|
---|
| 752 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> PULLDOWN;
|
---|
| 753 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AJ7;
|
---|
| 754 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
|
---|
| 755 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> PULLDOWN;
|
---|
| 756 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AJ5;
|
---|
| 757 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
|
---|
| 758 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> PULLDOWN;
|
---|
| 759 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AJ8;
|
---|
| 760 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
|
---|
| 761 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> PULLDOWN;
|
---|
| 762 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AG11;
|
---|
| 763 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
|
---|
| 764 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> PULLDOWN;
|
---|
| 765 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AM9;
|
---|
| 766 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
|
---|
| 767 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> PULLDOWN;
|
---|
| 768 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AK7;
|
---|
| 769 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
|
---|
| 770 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> PULLDOWN;
|
---|
| 771 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AK5;
|
---|
| 772 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin IOSTANDARD=LVTTL;
|
---|
| 773 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=AA4;
|
---|
| 774 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
|
---|
| 775 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=AC4;
|
---|
| 776 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
|
---|
| 777 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AJ9;
|
---|
| 778 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
|
---|
| 779 | Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin LOC=AG10;
|
---|
| 780 | Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
|
---|
| 781 | Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin LOC=AM3;
|
---|
| 782 | Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin IOSTANDARD=LVTTL;
|
---|
| 783 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO LOC=AG3;
|
---|
| 784 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IOSTANDARD=LVTTL;
|
---|
| 785 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO SLEW = SLOW;
|
---|
| 786 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO DRIVE = 8;
|
---|
| 787 |
|
---|
| 788 | #### Module radio_bridge_slot_3 constraints
|
---|
| 789 |
|
---|
| 790 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AP33;
|
---|
| 791 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin IOSTANDARD=LVTTL;
|
---|
| 792 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AJ33;
|
---|
| 793 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> IOSTANDARD = LVTTL;
|
---|
| 794 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> SLEW = SLOW;
|
---|
| 795 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AL37;
|
---|
| 796 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> IOSTANDARD = LVTTL;
|
---|
| 797 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> SLEW = SLOW;
|
---|
| 798 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AK36;
|
---|
| 799 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> IOSTANDARD = LVTTL;
|
---|
| 800 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> SLEW = SLOW;
|
---|
| 801 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AM38;
|
---|
| 802 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> IOSTANDARD = LVTTL;
|
---|
| 803 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> SLEW = SLOW;
|
---|
| 804 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AK37;
|
---|
| 805 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> IOSTANDARD = LVTTL;
|
---|
| 806 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> SLEW = SLOW;
|
---|
| 807 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AJ36;
|
---|
| 808 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> IOSTANDARD = LVTTL;
|
---|
| 809 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> SLEW = SLOW;
|
---|
| 810 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AL38;
|
---|
| 811 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> IOSTANDARD = LVTTL;
|
---|
| 812 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> SLEW = SLOW;
|
---|
| 813 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AG29;
|
---|
| 814 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 815 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> PULLDOWN;
|
---|
| 816 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AR34;
|
---|
| 817 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 818 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> PULLDOWN;
|
---|
| 819 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AU35;
|
---|
| 820 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 821 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> PULLDOWN;
|
---|
| 822 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AJ21;
|
---|
| 823 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 824 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> PULLDOWN;
|
---|
| 825 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AT32;
|
---|
| 826 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 827 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> PULLDOWN;
|
---|
| 828 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AT34;
|
---|
| 829 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 830 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> PULLDOWN;
|
---|
| 831 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AR33;
|
---|
| 832 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 833 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> PULLDOWN;
|
---|
| 834 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AM36;
|
---|
| 835 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 836 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> PULLDOWN;
|
---|
| 837 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AD28;
|
---|
| 838 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 839 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> PULLDOWN;
|
---|
| 840 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AL33;
|
---|
| 841 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 842 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> PULLDOWN;
|
---|
| 843 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AH32;
|
---|
| 844 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 845 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> PULLDOWN;
|
---|
| 846 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AD29;
|
---|
| 847 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 848 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> PULLDOWN;
|
---|
| 849 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AK33;
|
---|
| 850 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 851 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> PULLDOWN;
|
---|
| 852 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AE31;
|
---|
| 853 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 854 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> PULLDOWN;
|
---|
| 855 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AH29;
|
---|
| 856 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 857 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> PULLDOWN;
|
---|
| 858 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AK31;
|
---|
| 859 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 860 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> PULLDOWN;
|
---|
| 861 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AE28;
|
---|
| 862 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 863 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> PULLDOWN;
|
---|
| 864 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AF28;
|
---|
| 865 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 866 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> PULLDOWN;
|
---|
| 867 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AE27;
|
---|
| 868 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 869 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> PULLDOWN;
|
---|
| 870 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AD27;
|
---|
| 871 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 872 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> PULLDOWN;
|
---|
| 873 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AN33;
|
---|
| 874 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 875 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> PULLDOWN;
|
---|
| 876 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AL31;
|
---|
| 877 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 878 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> PULLDOWN;
|
---|
| 879 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AR32;
|
---|
| 880 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 881 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> PULLDOWN;
|
---|
| 882 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AM33;
|
---|
| 883 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 884 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> PULLDOWN;
|
---|
| 885 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AG30;
|
---|
| 886 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 887 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> PULLDOWN;
|
---|
| 888 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AM32;
|
---|
| 889 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 890 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> PULLDOWN;
|
---|
| 891 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AE29;
|
---|
| 892 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 893 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> PULLDOWN;
|
---|
| 894 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AN31;
|
---|
| 895 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 896 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> PULLDOWN;
|
---|
| 897 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB30;
|
---|
| 898 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 899 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AF38;
|
---|
| 900 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 901 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AD37;
|
---|
| 902 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 903 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=AF37;
|
---|
| 904 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 905 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB34;
|
---|
| 906 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 907 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=AF39;
|
---|
| 908 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 909 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA30;
|
---|
| 910 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 911 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=AC35;
|
---|
| 912 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 913 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC36;
|
---|
| 914 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 915 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=AE38;
|
---|
| 916 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 917 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AE36;
|
---|
| 918 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 919 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=AB36;
|
---|
| 920 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 921 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=AB33;
|
---|
| 922 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 923 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=AE39;
|
---|
| 924 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 925 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=AB35;
|
---|
| 926 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
|
---|
| 927 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=AB32;
|
---|
| 928 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
|
---|
| 929 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=AD32;
|
---|
| 930 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 931 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AK39;
|
---|
| 932 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 933 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=AF34;
|
---|
| 934 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 935 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=AB29;
|
---|
| 936 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 937 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=AC27;
|
---|
| 938 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 939 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AE34;
|
---|
| 940 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 941 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=AJ37;
|
---|
| 942 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 943 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=AC30;
|
---|
| 944 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 945 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=AH36;
|
---|
| 946 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 947 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AJ38;
|
---|
| 948 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 949 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=AJ39;
|
---|
| 950 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 951 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AG39;
|
---|
| 952 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 953 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=AF33;
|
---|
| 954 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 955 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=AH37;
|
---|
| 956 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 957 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=AG34;
|
---|
| 958 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
|
---|
| 959 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=AG38;
|
---|
| 960 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
|
---|
| 961 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=AC32;
|
---|
| 962 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 963 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=AB31;
|
---|
| 964 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 965 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AC31;
|
---|
| 966 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 967 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AD33;
|
---|
| 968 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 969 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AK38;
|
---|
| 970 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 971 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AC28;
|
---|
| 972 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 973 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AE30;
|
---|
| 974 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin IOSTANDARD=LVTTL;
|
---|
| 975 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin SLEW = SLOW;
|
---|
| 976 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AC34;
|
---|
| 977 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin IOSTANDARD=LVTTL;
|
---|
| 978 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin SLEW = SLOW;
|
---|
| 979 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=AL34;
|
---|
| 980 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin IOSTANDARD=LVTTL;
|
---|
| 981 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin SLEW = SLOW;
|
---|
| 982 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AK32;
|
---|
| 983 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin IOSTANDARD=LVTTL;
|
---|
| 984 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin SLEW = SLOW;
|
---|
| 985 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AE33;
|
---|
| 986 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin IOSTANDARD=LVTTL;
|
---|
| 987 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin SLEW = SLOW;
|
---|
| 988 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin DRIVE = 2;
|
---|
| 989 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AH34;
|
---|
| 990 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin IOSTANDARD=LVTTL;
|
---|
| 991 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin SLEW = SLOW;
|
---|
| 992 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin DRIVE = 2;
|
---|
| 993 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AG33;
|
---|
| 994 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 995 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> SLEW = SLOW;
|
---|
| 996 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> DRIVE = 2;
|
---|
| 997 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AH33;
|
---|
| 998 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 999 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> SLEW = SLOW;
|
---|
| 1000 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> DRIVE = 2;
|
---|
| 1001 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AN34;
|
---|
| 1002 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1003 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> SLEW = SLOW;
|
---|
| 1004 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> DRIVE = 2;
|
---|
| 1005 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AK35;
|
---|
| 1006 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1007 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> SLEW = SLOW;
|
---|
| 1008 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> DRIVE = 2;
|
---|
| 1009 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AK34;
|
---|
| 1010 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> IOSTANDARD=LVTTL;
|
---|
| 1011 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> SLEW = SLOW;
|
---|
| 1012 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> DRIVE = 2;
|
---|
| 1013 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AH30;
|
---|
| 1014 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
|
---|
| 1015 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AM34;
|
---|
| 1016 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
|
---|
| 1017 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AD30;
|
---|
| 1018 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
|
---|
| 1019 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AF29;
|
---|
| 1020 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
|
---|
| 1021 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG37;
|
---|
| 1022 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1023 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AD34;
|
---|
| 1024 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1025 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=AF36;
|
---|
| 1026 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
|
---|
| 1027 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AL39;
|
---|
| 1028 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
|
---|
| 1029 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AM37;
|
---|
| 1030 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
|
---|
| 1031 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=AA32;
|
---|
| 1032 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
|
---|
| 1033 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=AB38;
|
---|
| 1034 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
|
---|
| 1035 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=AA37;
|
---|
| 1036 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
|
---|
| 1037 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=AA33;
|
---|
| 1038 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1039 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> PULLDOWN;
|
---|
| 1040 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AD36;
|
---|
| 1041 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1042 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> PULLDOWN;
|
---|
| 1043 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=AC38;
|
---|
| 1044 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
|
---|
| 1045 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> PULLDOWN;
|
---|
| 1046 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AB37;
|
---|
| 1047 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
|
---|
| 1048 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> PULLDOWN;
|
---|
| 1049 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=AA36;
|
---|
| 1050 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
|
---|
| 1051 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> PULLDOWN;
|
---|
| 1052 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=AC39;
|
---|
| 1053 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
|
---|
| 1054 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> PULLDOWN;
|
---|
| 1055 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=AA34;
|
---|
| 1056 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
|
---|
| 1057 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> PULLDOWN;
|
---|
| 1058 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=AA31;
|
---|
| 1059 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
|
---|
| 1060 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> PULLDOWN;
|
---|
| 1061 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AA35;
|
---|
| 1062 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
|
---|
| 1063 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> PULLDOWN;
|
---|
| 1064 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=AE37;
|
---|
| 1065 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
|
---|
| 1066 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> PULLDOWN;
|
---|
| 1067 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AG35;
|
---|
| 1068 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin IOSTANDARD=LVTTL;
|
---|
| 1069 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AG31;
|
---|
| 1070 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
|
---|
| 1071 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AF30;
|
---|
| 1072 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
|
---|
| 1073 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=AD38;
|
---|
| 1074 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
|
---|
| 1075 | Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin LOC=AH38;
|
---|
| 1076 | Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
|
---|
| 1077 | Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin LOC=AE35;
|
---|
| 1078 | Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin IOSTANDARD=LVTTL;
|
---|
| 1079 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO LOC=AJ31;
|
---|
| 1080 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IOSTANDARD=LVTTL;
|
---|
| 1081 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO SLEW = SLOW;
|
---|
| 1082 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO DRIVE = 8;
|
---|
| 1083 |
|
---|
| 1084 | #### Module radio_bridge_slot_4 constraints
|
---|
| 1085 |
|
---|
| 1086 | Net fpga_0_radio_bridge_slot_4_converter_clock_out_pin LOC=W30;
|
---|
| 1087 | Net fpga_0_radio_bridge_slot_4_converter_clock_out_pin IOSTANDARD=LVTTL;
|
---|
| 1088 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<0> LOC=R34;
|
---|
| 1089 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<0> IOSTANDARD = LVTTL;
|
---|
| 1090 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<0> SLEW = SLOW;
|
---|
| 1091 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<1> LOC=R35;
|
---|
| 1092 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<1> IOSTANDARD = LVTTL;
|
---|
| 1093 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<1> SLEW = SLOW;
|
---|
| 1094 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<2> LOC=T38;
|
---|
| 1095 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<2> IOSTANDARD = LVTTL;
|
---|
| 1096 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<2> SLEW = SLOW;
|
---|
| 1097 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<3> LOC=R37;
|
---|
| 1098 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<3> IOSTANDARD = LVTTL;
|
---|
| 1099 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<3> SLEW = SLOW;
|
---|
| 1100 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<4> LOC=R36;
|
---|
| 1101 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<4> IOSTANDARD = LVTTL;
|
---|
| 1102 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<4> SLEW = SLOW;
|
---|
| 1103 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<5> LOC=R39;
|
---|
| 1104 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<5> IOSTANDARD = LVTTL;
|
---|
| 1105 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<5> SLEW = SLOW;
|
---|
| 1106 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<6> LOC=R38;
|
---|
| 1107 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<6> IOSTANDARD = LVTTL;
|
---|
| 1108 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<6> SLEW = SLOW;
|
---|
| 1109 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<0> LOC=Y31;
|
---|
| 1110 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 1111 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<0> PULLDOWN;
|
---|
| 1112 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<1> LOC=Y32;
|
---|
| 1113 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 1114 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<1> PULLDOWN;
|
---|
| 1115 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<2> LOC=W28;
|
---|
| 1116 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 1117 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<2> PULLDOWN;
|
---|
| 1118 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<3> LOC=L21;
|
---|
| 1119 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 1120 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<3> PULLDOWN;
|
---|
| 1121 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<4> LOC=W27;
|
---|
| 1122 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 1123 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<4> PULLDOWN;
|
---|
| 1124 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<5> LOC=V27;
|
---|
| 1125 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 1126 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<5> PULLDOWN;
|
---|
| 1127 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<6> LOC=W29;
|
---|
| 1128 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 1129 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<6> PULLDOWN;
|
---|
| 1130 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<7> LOC=V32;
|
---|
| 1131 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 1132 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<7> PULLDOWN;
|
---|
| 1133 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<8> LOC=W32;
|
---|
| 1134 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 1135 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<8> PULLDOWN;
|
---|
| 1136 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<9> LOC=W35;
|
---|
| 1137 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 1138 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<9> PULLDOWN;
|
---|
| 1139 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<10> LOC=T29;
|
---|
| 1140 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 1141 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<10> PULLDOWN;
|
---|
| 1142 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<11> LOC=V31;
|
---|
| 1143 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 1144 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<11> PULLDOWN;
|
---|
| 1145 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<12> LOC=V35;
|
---|
| 1146 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 1147 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<12> PULLDOWN;
|
---|
| 1148 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<13> LOC=U34;
|
---|
| 1149 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 1150 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<13> PULLDOWN;
|
---|
| 1151 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<0> LOC=U36;
|
---|
| 1152 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 1153 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<0> PULLDOWN;
|
---|
| 1154 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<1> LOC=U30;
|
---|
| 1155 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 1156 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<1> PULLDOWN;
|
---|
| 1157 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<2> LOC=V36;
|
---|
| 1158 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 1159 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<2> PULLDOWN;
|
---|
| 1160 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<3> LOC=T32;
|
---|
| 1161 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 1162 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<3> PULLDOWN;
|
---|
| 1163 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<4> LOC=V30;
|
---|
| 1164 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 1165 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<4> PULLDOWN;
|
---|
| 1166 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<5> LOC=U31;
|
---|
| 1167 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 1168 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<5> PULLDOWN;
|
---|
| 1169 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<6> LOC=V37;
|
---|
| 1170 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 1171 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<6> PULLDOWN;
|
---|
| 1172 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<7> LOC=W36;
|
---|
| 1173 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 1174 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<7> PULLDOWN;
|
---|
| 1175 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<8> LOC=Y33;
|
---|
| 1176 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 1177 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<8> PULLDOWN;
|
---|
| 1178 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<9> LOC=W34;
|
---|
| 1179 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 1180 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<9> PULLDOWN;
|
---|
| 1181 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<10> LOC=V29;
|
---|
| 1182 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 1183 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<10> PULLDOWN;
|
---|
| 1184 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<11> LOC=V28;
|
---|
| 1185 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 1186 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<11> PULLDOWN;
|
---|
| 1187 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<12> LOC=W33;
|
---|
| 1188 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 1189 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<12> PULLDOWN;
|
---|
| 1190 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<13> LOC=T28;
|
---|
| 1191 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 1192 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<13> PULLDOWN;
|
---|
| 1193 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<0> LOC=H31;
|
---|
| 1194 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<0> IOSTANDARD = LVTTL;
|
---|
| 1195 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<1> LOC=G31;
|
---|
| 1196 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<1> IOSTANDARD = LVTTL;
|
---|
| 1197 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<2> LOC=F33;
|
---|
| 1198 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<2> IOSTANDARD = LVTTL;
|
---|
| 1199 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<3> LOC=E33;
|
---|
| 1200 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<3> IOSTANDARD = LVTTL;
|
---|
| 1201 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<4> LOC=E38;
|
---|
| 1202 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<4> IOSTANDARD = LVTTL;
|
---|
| 1203 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<5> LOC=E34;
|
---|
| 1204 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<5> IOSTANDARD = LVTTL;
|
---|
| 1205 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<6> LOC=D38;
|
---|
| 1206 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<6> IOSTANDARD = LVTTL;
|
---|
| 1207 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<7> LOC=D35;
|
---|
| 1208 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<7> IOSTANDARD = LVTTL;
|
---|
| 1209 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<8> LOC=H32;
|
---|
| 1210 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<8> IOSTANDARD = LVTTL;
|
---|
| 1211 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<9> LOC=D34;
|
---|
| 1212 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<9> IOSTANDARD = LVTTL;
|
---|
| 1213 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<10> LOC=C35;
|
---|
| 1214 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<10> IOSTANDARD = LVTTL;
|
---|
| 1215 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<11> LOC=H33;
|
---|
| 1216 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<11> IOSTANDARD = LVTTL;
|
---|
| 1217 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<12> LOC=J39;
|
---|
| 1218 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<12> IOSTANDARD = LVTTL;
|
---|
| 1219 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<13> LOC=J38;
|
---|
| 1220 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<13> IOSTANDARD = LVTTL;
|
---|
| 1221 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<14> LOC=H38;
|
---|
| 1222 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<14> IOSTANDARD = LVTTL;
|
---|
| 1223 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<15> LOC=J31;
|
---|
| 1224 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<15> IOSTANDARD = LVTTL;
|
---|
| 1225 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<0> LOC=N33;
|
---|
| 1226 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL;
|
---|
| 1227 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<1> LOC=M37;
|
---|
| 1228 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL;
|
---|
| 1229 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<2> LOC=M34;
|
---|
| 1230 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL;
|
---|
| 1231 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<3> LOC=L39;
|
---|
| 1232 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL;
|
---|
| 1233 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<4> LOC=M36;
|
---|
| 1234 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL;
|
---|
| 1235 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<5> LOC=N30;
|
---|
| 1236 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL;
|
---|
| 1237 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<6> LOC=L37;
|
---|
| 1238 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL;
|
---|
| 1239 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<7> LOC=M33;
|
---|
| 1240 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL;
|
---|
| 1241 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<8> LOC=L35;
|
---|
| 1242 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL;
|
---|
| 1243 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<9> LOC=L38;
|
---|
| 1244 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL;
|
---|
| 1245 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<10> LOC=N31;
|
---|
| 1246 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL;
|
---|
| 1247 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<11> LOC=L36;
|
---|
| 1248 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL;
|
---|
| 1249 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<12> LOC=M32;
|
---|
| 1250 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL;
|
---|
| 1251 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<13> LOC=K37;
|
---|
| 1252 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL;
|
---|
| 1253 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<14> LOC=L34;
|
---|
| 1254 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL;
|
---|
| 1255 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<15> LOC=L33;
|
---|
| 1256 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL;
|
---|
| 1257 | Net fpga_0_radio_bridge_slot_4_dac_spi_data_pin LOC=L31;
|
---|
| 1258 | Net fpga_0_radio_bridge_slot_4_dac_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 1259 | Net fpga_0_radio_bridge_slot_4_dac_spi_cs_pin LOC=N34;
|
---|
| 1260 | Net fpga_0_radio_bridge_slot_4_dac_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 1261 | Net fpga_0_radio_bridge_slot_4_dac_spi_clk_pin LOC=M38;
|
---|
| 1262 | Net fpga_0_radio_bridge_slot_4_dac_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 1263 | Net fpga_0_radio_bridge_slot_4_radio_spi_clk_pin LOC=N38;
|
---|
| 1264 | Net fpga_0_radio_bridge_slot_4_radio_spi_clk_pin IOSTANDARD=LVTTL;
|
---|
| 1265 | Net fpga_0_radio_bridge_slot_4_radio_spi_data_pin LOC=N39;
|
---|
| 1266 | Net fpga_0_radio_bridge_slot_4_radio_spi_data_pin IOSTANDARD=LVTTL;
|
---|
| 1267 | Net fpga_0_radio_bridge_slot_4_radio_spi_cs_pin LOC=N37;
|
---|
| 1268 | Net fpga_0_radio_bridge_slot_4_radio_spi_cs_pin IOSTANDARD=LVTTL;
|
---|
| 1269 | Net fpga_0_radio_bridge_slot_4_radio_SHDN_pin LOC=V39;
|
---|
| 1270 | Net fpga_0_radio_bridge_slot_4_radio_SHDN_pin IOSTANDARD=LVTTL;
|
---|
| 1271 | Net fpga_0_radio_bridge_slot_4_radio_SHDN_pin SLEW = SLOW;
|
---|
| 1272 | Net fpga_0_radio_bridge_slot_4_radio_TxEn_pin LOC=P38;
|
---|
| 1273 | Net fpga_0_radio_bridge_slot_4_radio_TxEn_pin IOSTANDARD=LVTTL;
|
---|
| 1274 | Net fpga_0_radio_bridge_slot_4_radio_TxEn_pin SLEW = SLOW;
|
---|
| 1275 | Net fpga_0_radio_bridge_slot_4_radio_RxEn_pin LOC=T33;
|
---|
| 1276 | Net fpga_0_radio_bridge_slot_4_radio_RxEn_pin IOSTANDARD=LVTTL;
|
---|
| 1277 | Net fpga_0_radio_bridge_slot_4_radio_RxEn_pin SLEW = SLOW;
|
---|
| 1278 | Net fpga_0_radio_bridge_slot_4_radio_RxHP_pin LOC=V38;
|
---|
| 1279 | Net fpga_0_radio_bridge_slot_4_radio_RxHP_pin IOSTANDARD=LVTTL;
|
---|
| 1280 | Net fpga_0_radio_bridge_slot_4_radio_RxHP_pin SLEW = SLOW;
|
---|
| 1281 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin LOC=Y36;
|
---|
| 1282 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin IOSTANDARD=LVTTL;
|
---|
| 1283 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin SLEW = SLOW;
|
---|
| 1284 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin DRIVE = 2;
|
---|
| 1285 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin LOC=P35;
|
---|
| 1286 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin IOSTANDARD=LVTTL;
|
---|
| 1287 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin SLEW = SLOW;
|
---|
| 1288 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin DRIVE = 2;
|
---|
| 1289 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> LOC=R30;
|
---|
| 1290 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1291 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> SLEW = SLOW;
|
---|
| 1292 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> DRIVE = 2;
|
---|
| 1293 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> LOC=R33;
|
---|
| 1294 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1295 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> SLEW = SLOW;
|
---|
| 1296 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> DRIVE = 2;
|
---|
| 1297 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> LOC=R28;
|
---|
| 1298 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1299 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> SLEW = SLOW;
|
---|
| 1300 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> DRIVE = 2;
|
---|
| 1301 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> LOC=V34;
|
---|
| 1302 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1303 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> SLEW = SLOW;
|
---|
| 1304 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> DRIVE = 2;
|
---|
| 1305 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> LOC=P31;
|
---|
| 1306 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> IOSTANDARD=LVTTL;
|
---|
| 1307 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> SLEW = SLOW;
|
---|
| 1308 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> DRIVE = 2;
|
---|
| 1309 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin LOC=R32;
|
---|
| 1310 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL;
|
---|
| 1311 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin LOC=T34;
|
---|
| 1312 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL;
|
---|
| 1313 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin LOC=V33;
|
---|
| 1314 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL;
|
---|
| 1315 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin LOC=T30;
|
---|
| 1316 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL;
|
---|
| 1317 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<0> LOC=P36;
|
---|
| 1318 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1319 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<1> LOC=P39;
|
---|
| 1320 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1321 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<2> LOC=P34;
|
---|
| 1322 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<2> IOSTANDARD=LVTTL;
|
---|
| 1323 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<3> LOC=P37;
|
---|
| 1324 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<3> IOSTANDARD=LVTTL;
|
---|
| 1325 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin LOC=U39;
|
---|
| 1326 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL;
|
---|
| 1327 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin LOC=K39;
|
---|
| 1328 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL;
|
---|
| 1329 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin LOC=K38;
|
---|
| 1330 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL;
|
---|
| 1331 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin LOC=M30;
|
---|
| 1332 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL;
|
---|
| 1333 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> LOC=F39;
|
---|
| 1334 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL;
|
---|
| 1335 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> PULLDOWN;
|
---|
| 1336 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> LOC=D39;
|
---|
| 1337 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL;
|
---|
| 1338 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> PULLDOWN;
|
---|
| 1339 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> LOC=J35;
|
---|
| 1340 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL;
|
---|
| 1341 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> PULLDOWN;
|
---|
| 1342 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> LOC=K33;
|
---|
| 1343 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL;
|
---|
| 1344 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> PULLDOWN;
|
---|
| 1345 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> LOC=K34;
|
---|
| 1346 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL;
|
---|
| 1347 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> PULLDOWN;
|
---|
| 1348 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> LOC=K35;
|
---|
| 1349 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL;
|
---|
| 1350 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> PULLDOWN;
|
---|
| 1351 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> LOC=J34;
|
---|
| 1352 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL;
|
---|
| 1353 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> PULLDOWN;
|
---|
| 1354 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> LOC=K32;
|
---|
| 1355 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL;
|
---|
| 1356 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> PULLDOWN;
|
---|
| 1357 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> LOC=K31;
|
---|
| 1358 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL;
|
---|
| 1359 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> PULLDOWN;
|
---|
| 1360 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> LOC=G39;
|
---|
| 1361 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL;
|
---|
| 1362 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> PULLDOWN;
|
---|
| 1363 | Net fpga_0_radio_bridge_slot_4_radio_LD_pin LOC=P33;
|
---|
| 1364 | Net fpga_0_radio_bridge_slot_4_radio_LD_pin IOSTANDARD=LVTTL;
|
---|
| 1365 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin LOC=W37;
|
---|
| 1366 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL;
|
---|
| 1367 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin LOC=W31;
|
---|
| 1368 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL;
|
---|
| 1369 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin LOC=J33;
|
---|
| 1370 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL;
|
---|
| 1371 | Net fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin LOC=K36;
|
---|
| 1372 | Net fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL;
|
---|
| 1373 | Net fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin LOC=N35;
|
---|
| 1374 | Net fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin IOSTANDARD=LVTTL;
|
---|
| 1375 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO LOC=P32;
|
---|
| 1376 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO IOSTANDARD=LVTTL;
|
---|
| 1377 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO SLEW = SLOW;
|
---|
| 1378 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO DRIVE = 8;
|
---|
| 1379 |
|
---|