1 | ############################################################################ |
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2 | ## This system.ucf file is generated by Base System Builder based on the |
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3 | ## settings in the selected Xilinx Board Definition file. Please add other |
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4 | ## user constraints to this file based on customer design specifications. |
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5 | ############################################################################ |
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6 | |
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7 | Net sys_clk_pin LOC=AN20; |
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8 | Net sys_clk_pin IOSTANDARD = LVTTL; |
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9 | Net sys_rst_pin LOC=M21; |
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10 | Net sys_rst_pin IOSTANDARD = LVCMOS25; |
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11 | ## System level constraints |
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12 | Net sys_clk_pin TNM_NET = sys_clk_pin; |
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13 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps; |
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14 | Net sys_rst_pin TIG; |
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15 | NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; |
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16 | NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; |
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17 | NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; |
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18 | TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; |
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19 | |
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20 | ## IO Devices constraints |
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21 | #Debug header LOC constraints (manually entered) |
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22 | NET "debug<0>" LOC = "L20" | IOSTANDARD = LVTTL; #pin 0 |
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23 | NET "debug<1>" LOC = "J21" | IOSTANDARD = LVTTL; #pin 1 |
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24 | NET "debug<2>" LOC = "G20" | IOSTANDARD = LVTTL; #pin 2 |
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25 | NET "debug<3>" LOC = "J20" | IOSTANDARD = LVTTL; #pin 3 |
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26 | NET "debug<4>" LOC = "K21" | IOSTANDARD = LVTTL; #pin 4 |
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27 | NET "debug<5>" LOC = "F20" | IOSTANDARD = LVTTL; #pin 5 |
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28 | NET "debug<6>" LOC = "H20" | IOSTANDARD = LVTTL; #pin 6 |
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29 | NET "debug<7>" LOC = "L21" | IOSTANDARD = LVTTL; #pin 7 |
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30 | NET "debug<8>" LOC = "H18" | IOSTANDARD = LVTTL; #pin 8 |
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31 | NET "debug<9>" LOC = "H19" | IOSTANDARD = LVTTL; #pin 9 |
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32 | NET "debug<10>" LOC = "K19" | IOSTANDARD = LVTTL; #pin 10 |
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33 | NET "debug<11>" LOC = "G18" | IOSTANDARD = LVTTL; #pin 11 |
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34 | NET "debug<12>" LOC = "F19" | IOSTANDARD = LVTTL; #pin 12 |
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35 | NET "debug<13>" LOC = "L19" | IOSTANDARD = LVTTL; #pin 13 |
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36 | NET "debug<14>" LOC = "J19" | IOSTANDARD = LVTTL; #pin 14 |
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37 | NET "debug<15>" LOC = "F18" | IOSTANDARD = LVTTL; #pin 15 |
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38 | |
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39 | #### Module Ethernet_MAC constraints |
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40 | |
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41 | Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=H24; |
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42 | Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=G17; |
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43 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=C17; |
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44 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=G15; |
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45 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=K17; |
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46 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=E17; |
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47 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=D17; |
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48 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=C18; |
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49 | Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=G22; |
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50 | Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=F23; |
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51 | Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=J22; |
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52 | Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=H23; |
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53 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=K23; |
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54 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=E21; |
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55 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=E22; |
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56 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=H22; |
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57 | |
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58 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin IOSTANDARD = LVCMOS25; |
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59 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin SLEW = SLOW; |
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60 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin DRIVE = 8; |
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61 | Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVCMOS25; |
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62 | Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVCMOS25; |
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63 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVCMOS25; |
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64 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> SLEW = SLOW; |
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65 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> DRIVE = 8; |
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66 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVCMOS25; |
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67 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> SLEW = SLOW; |
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68 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> DRIVE = 8; |
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69 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVCMOS25; |
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70 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> SLEW = SLOW; |
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71 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> DRIVE = 8; |
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72 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVCMOS25; |
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73 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> SLEW = SLOW; |
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74 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> DRIVE = 8; |
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75 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVCMOS25; |
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76 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin SLEW = SLOW; |
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77 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin DRIVE = 8; |
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78 | Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVCMOS25; |
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79 | Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVCMOS25; |
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80 | Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVCMOS25; |
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81 | Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVCMOS25; |
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82 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVCMOS25; |
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83 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVCMOS25; |
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84 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVCMOS25; |
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85 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVCMOS25; |
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86 | |
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87 | #### Module warp_v4_userio_all constraints |
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88 | |
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89 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<0> LOC=N24; |
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90 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<0> IOSTANDARD = LVCMOS25; |
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91 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<1> LOC=N20; |
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92 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<1> IOSTANDARD = LVCMOS25; |
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93 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<2> LOC=L18; |
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94 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<2> IOSTANDARD = LVCMOS25; |
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95 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<3> LOC=N18; |
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96 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<3> IOSTANDARD = LVCMOS25; |
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97 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<4> LOC=M18; |
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98 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<4> IOSTANDARD = LVCMOS25; |
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99 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<5> LOC=M25; |
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100 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<5> IOSTANDARD = LVCMOS25; |
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101 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<6> LOC=N19; |
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102 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<6> IOSTANDARD = LVCMOS25; |
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103 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<7> LOC=P19; |
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104 | Net fpga_0_warp_v4_userio_all_LEDs_out_pin<7> IOSTANDARD = LVCMOS25; |
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105 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<0> LOC=M17; |
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106 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<0> IOSTANDARD = LVCMOS25; |
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107 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<1> LOC=R18; |
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108 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<1> IOSTANDARD = LVCMOS25; |
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109 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<2> LOC=P17; |
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110 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<2> IOSTANDARD = LVCMOS25; |
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111 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<3> LOC=M16; |
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112 | Net fpga_0_warp_v4_userio_all_DIPSW_in_pin<3> IOSTANDARD = LVCMOS25; |
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113 | Net fpga_0_warp_v4_userio_all_PB_in_pin<0> LOC=N23; |
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114 | Net fpga_0_warp_v4_userio_all_PB_in_pin<0> IOSTANDARD = LVCMOS25; |
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115 | Net fpga_0_warp_v4_userio_all_PB_in_pin<1> LOC=N22; |
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116 | Net fpga_0_warp_v4_userio_all_PB_in_pin<1> IOSTANDARD = LVCMOS25; |
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117 | Net fpga_0_warp_v4_userio_all_PB_in_pin<2> LOC=M23; |
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118 | Net fpga_0_warp_v4_userio_all_PB_in_pin<2> IOSTANDARD = LVCMOS25; |
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119 | Net fpga_0_warp_v4_userio_all_PB_in_pin<3> LOC=L23; |
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120 | Net fpga_0_warp_v4_userio_all_PB_in_pin<3> IOSTANDARD = LVCMOS25; |
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121 | Net fpga_0_warp_v4_userio_all_IOEx_SCL_pin LOC=AK17; |
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122 | Net fpga_0_warp_v4_userio_all_IOEx_SCL_pin IOSTANDARD = LVTTL; |
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123 | Net fpga_0_warp_v4_userio_all_IOEx_SDA_pin LOC=AL18; |
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124 | Net fpga_0_warp_v4_userio_all_IOEx_SDA_pin IOSTANDARD = LVTTL; |
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125 | |
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126 | #### Module rs232_db9 constraints |
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127 | |
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128 | Net fpga_0_rs232_db9_RX_pin LOC=L24; |
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129 | Net fpga_0_rs232_db9_RX_pin IOSTANDARD = LVCMOS25; |
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130 | Net fpga_0_rs232_db9_TX_pin LOC=K24; |
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131 | Net fpga_0_rs232_db9_TX_pin IOSTANDARD = LVCMOS25; |
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132 | |
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133 | #### Module clk_board_config constraints |
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134 | |
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135 | Net fpga_0_clk_board_config_sys_clk_pin LOC=AM21; |
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136 | Net fpga_0_clk_board_config_sys_clk_pin IOSTANDARD = LVTTL; |
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137 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN19; |
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138 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin IOSTANDARD=LVTTL; |
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139 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin SLEW = SLOW; |
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140 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AP19; |
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141 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin IOSTANDARD=LVTTL; |
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142 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin SLEW = SLOW; |
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143 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AR19; |
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144 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin IOSTANDARD=LVTTL; |
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145 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin SLEW = SLOW; |
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146 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AM20; |
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147 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin IOSTANDARD=LVTTL; |
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148 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin SLEW = SLOW; |
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149 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AR21; |
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150 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin IOSTANDARD=LVTTL; |
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151 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin SLEW = SLOW; |
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152 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AL21; |
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153 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin IOSTANDARD=LVTTL; |
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154 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin SLEW = SLOW; |
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155 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AK21; |
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156 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin IOSTANDARD=LVTTL; |
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157 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin SLEW = SLOW; |
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158 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AN22; |
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159 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin IOSTANDARD=LVTTL; |
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160 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin SLEW = SLOW; |
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161 | |
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162 | #### Module radio_controller_0 constraints |
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163 | |
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164 | |
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165 | #### Module radio_bridge_slot_1 constraints |
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166 | |
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167 | Net fpga_0_radio_bridge_slot_1_converter_clock_out_pin LOC=F10; |
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168 | Net fpga_0_radio_bridge_slot_1_converter_clock_out_pin IOSTANDARD=LVTTL; |
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169 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<0> LOC=F16; |
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170 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<0> IOSTANDARD = LVTTL; |
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171 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<1> LOC=H13; |
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172 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<1> IOSTANDARD = LVTTL; |
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173 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<2> LOC=E16; |
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174 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<2> IOSTANDARD = LVTTL; |
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175 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<3> LOC=D15; |
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176 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<3> IOSTANDARD = LVTTL; |
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177 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<4> LOC=H10; |
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178 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<4> IOSTANDARD = LVTTL; |
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179 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<5> LOC=D16; |
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180 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<5> IOSTANDARD = LVTTL; |
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181 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<6> LOC=H8; |
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182 | Net fpga_0_radio_bridge_slot_1_radio_B_pin<6> IOSTANDARD = LVTTL; |
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183 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<0> LOC=E7; |
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184 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<0> IOSTANDARD = LVTTL; |
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185 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<1> LOC=E8; |
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186 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<1> IOSTANDARD = LVTTL; |
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187 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<2> LOC=D10; |
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188 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<2> IOSTANDARD = LVTTL; |
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189 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<3> LOC=AG20; |
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190 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<3> IOSTANDARD = LVTTL; |
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191 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<4> LOC=D11; |
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192 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<4> IOSTANDARD = LVTTL; |
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193 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<5> LOC=C15; |
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194 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<5> IOSTANDARD = LVTTL; |
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195 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<6> LOC=E6; |
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196 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<6> IOSTANDARD = LVTTL; |
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197 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<7> LOC=E4; |
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198 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<7> IOSTANDARD = LVTTL; |
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199 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<8> LOC=D4; |
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200 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<8> IOSTANDARD = LVTTL; |
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201 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<9> LOC=C10; |
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202 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<9> IOSTANDARD = LVTTL; |
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203 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<10> LOC=G6; |
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204 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<10> IOSTANDARD = LVTTL; |
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205 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<11> LOC=D7; |
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206 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<11> IOSTANDARD = LVTTL; |
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207 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<12> LOC=F4; |
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208 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<12> IOSTANDARD = LVTTL; |
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209 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<13> LOC=E3; |
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210 | Net fpga_0_radio_bridge_slot_1_radio_ADC_I_pin<13> IOSTANDARD = LVTTL; |
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211 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<0> LOC=G7; |
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212 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL; |
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213 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<1> LOC=E12; |
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214 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL; |
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215 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<2> LOC=E13; |
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216 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL; |
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217 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<3> LOC=D12; |
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218 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL; |
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219 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<4> LOC=F9; |
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220 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL; |
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221 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<5> LOC=H7; |
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222 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL; |
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223 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<6> LOC=G8; |
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224 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL; |
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225 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<7> LOC=E9; |
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226 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL; |
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227 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<8> LOC=C12; |
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228 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL; |
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229 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<9> LOC=F5; |
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230 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL; |
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231 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<10> LOC=F8; |
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232 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL; |
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233 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<11> LOC=D6; |
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234 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL; |
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235 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<12> LOC=C13; |
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236 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL; |
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237 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<13> LOC=D9; |
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238 | Net fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL; |
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239 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<0> LOC=N10; |
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240 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<0> IOSTANDARD = LVTTL; |
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241 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<1> LOC=R4; |
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242 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<1> IOSTANDARD = LVTTL; |
---|
243 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<2> LOC=R3; |
---|
244 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<2> IOSTANDARD = LVTTL; |
---|
245 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<3> LOC=N9; |
---|
246 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<3> IOSTANDARD = LVTTL; |
---|
247 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<4> LOC=R8; |
---|
248 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<4> IOSTANDARD = LVTTL; |
---|
249 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<5> LOC=T3; |
---|
250 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<5> IOSTANDARD = LVTTL; |
---|
251 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<6> LOC=T11; |
---|
252 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<6> IOSTANDARD = LVTTL; |
---|
253 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<7> LOC=P5; |
---|
254 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<7> IOSTANDARD = LVTTL; |
---|
255 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<8> LOC=R12; |
---|
256 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<8> IOSTANDARD = LVTTL; |
---|
257 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<9> LOC=P12; |
---|
258 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<9> IOSTANDARD = LVTTL; |
---|
259 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<10> LOC=T10; |
---|
260 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<10> IOSTANDARD = LVTTL; |
---|
261 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<11> LOC=T8; |
---|
262 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<11> IOSTANDARD = LVTTL; |
---|
263 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<12> LOC=P10; |
---|
264 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<12> IOSTANDARD = LVTTL; |
---|
265 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<13> LOC=P11; |
---|
266 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<13> IOSTANDARD = LVTTL; |
---|
267 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<14> LOC=N12; |
---|
268 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<14> IOSTANDARD = LVTTL; |
---|
269 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<15> LOC=T6; |
---|
270 | Net fpga_0_radio_bridge_slot_1_radio_DAC_I_pin<15> IOSTANDARD = LVTTL; |
---|
271 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<0> LOC=N7; |
---|
272 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
273 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<1> LOC=M11; |
---|
274 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
275 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<2> LOC=L4; |
---|
276 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
277 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<3> LOC=M5; |
---|
278 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
279 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<4> LOC=L5; |
---|
280 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
281 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<5> LOC=J10; |
---|
282 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
283 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<6> LOC=J11; |
---|
284 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
285 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<7> LOC=J9; |
---|
286 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
287 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<8> LOC=M7; |
---|
288 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
289 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<9> LOC=M6; |
---|
290 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
291 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<10> LOC=M3; |
---|
292 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
293 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<11> LOC=M10; |
---|
294 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
295 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<12> LOC=K9; |
---|
296 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
297 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<13> LOC=J12; |
---|
298 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
299 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<14> LOC=L6; |
---|
300 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL; |
---|
301 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<15> LOC=L8; |
---|
302 | Net fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL; |
---|
303 | Net fpga_0_radio_bridge_slot_1_dac_spi_data_pin LOC=N5; |
---|
304 | Net fpga_0_radio_bridge_slot_1_dac_spi_data_pin IOSTANDARD=LVTTL; |
---|
305 | Net fpga_0_radio_bridge_slot_1_dac_spi_cs_pin LOC=J6; |
---|
306 | Net fpga_0_radio_bridge_slot_1_dac_spi_cs_pin IOSTANDARD=LVTTL; |
---|
307 | Net fpga_0_radio_bridge_slot_1_dac_spi_clk_pin LOC=K7; |
---|
308 | Net fpga_0_radio_bridge_slot_1_dac_spi_clk_pin IOSTANDARD=LVTTL; |
---|
309 | Net fpga_0_radio_bridge_slot_1_radio_spi_clk_pin LOC=P9; |
---|
310 | Net fpga_0_radio_bridge_slot_1_radio_spi_clk_pin IOSTANDARD=LVTTL; |
---|
311 | Net fpga_0_radio_bridge_slot_1_radio_spi_data_pin LOC=K4; |
---|
312 | Net fpga_0_radio_bridge_slot_1_radio_spi_data_pin IOSTANDARD=LVTTL; |
---|
313 | Net fpga_0_radio_bridge_slot_1_radio_spi_cs_pin LOC=N3; |
---|
314 | Net fpga_0_radio_bridge_slot_1_radio_spi_cs_pin IOSTANDARD=LVTTL; |
---|
315 | Net fpga_0_radio_bridge_slot_1_radio_SHDN_pin LOC=F11; |
---|
316 | Net fpga_0_radio_bridge_slot_1_radio_SHDN_pin IOSTANDARD=LVTTL; |
---|
317 | Net fpga_0_radio_bridge_slot_1_radio_TxEn_pin LOC=R6; |
---|
318 | Net fpga_0_radio_bridge_slot_1_radio_TxEn_pin IOSTANDARD=LVTTL; |
---|
319 | Net fpga_0_radio_bridge_slot_1_radio_RxEn_pin LOC=G13; |
---|
320 | Net fpga_0_radio_bridge_slot_1_radio_RxEn_pin IOSTANDARD=LVTTL; |
---|
321 | Net fpga_0_radio_bridge_slot_1_radio_RxHP_pin LOC=F6; |
---|
322 | Net fpga_0_radio_bridge_slot_1_radio_RxHP_pin IOSTANDARD=LVTTL; |
---|
323 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin LOC=G3; |
---|
324 | Net fpga_0_radio_bridge_slot_1_radio_24PA_pin IOSTANDARD=LVTTL; |
---|
325 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin LOC=F3; |
---|
326 | Net fpga_0_radio_bridge_slot_1_radio_5PA_pin IOSTANDARD=LVTTL; |
---|
327 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> LOC=H3; |
---|
328 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<0> IOSTANDARD=LVTTL; |
---|
329 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> LOC=C5; |
---|
330 | Net fpga_0_radio_bridge_slot_1_radio_ANTSW_pin<1> IOSTANDARD=LVTTL; |
---|
331 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> LOC=H4; |
---|
332 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<0> IOSTANDARD=LVTTL; |
---|
333 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> LOC=C4; |
---|
334 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<1> IOSTANDARD=LVTTL; |
---|
335 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> LOC=C8; |
---|
336 | Net fpga_0_radio_bridge_slot_1_radio_LED_pin<2> IOSTANDARD=LVTTL; |
---|
337 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin LOC=D14; |
---|
338 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL; |
---|
339 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin LOC=G11; |
---|
340 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL; |
---|
341 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin LOC=G5; |
---|
342 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL; |
---|
343 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin LOC=G10; |
---|
344 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL; |
---|
345 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<0> LOC=J5; |
---|
346 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<0> IOSTANDARD=LVTTL; |
---|
347 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<1> LOC=K3; |
---|
348 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<1> IOSTANDARD=LVTTL; |
---|
349 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<2> LOC=P6; |
---|
350 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<2> IOSTANDARD=LVTTL; |
---|
351 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<3> LOC=J4; |
---|
352 | Net fpga_0_radio_bridge_slot_1_radio_DIPSW_pin<3> IOSTANDARD=LVTTL; |
---|
353 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin LOC=H9; |
---|
354 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL; |
---|
355 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin LOC=U12; |
---|
356 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL; |
---|
357 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin LOC=U11; |
---|
358 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL; |
---|
359 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin LOC=T5; |
---|
360 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL; |
---|
361 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> LOC=T9; |
---|
362 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL; |
---|
363 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<0> PULLDOWN; |
---|
364 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> LOC=L10; |
---|
365 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL; |
---|
366 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<1> PULLDOWN; |
---|
367 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> LOC=U8; |
---|
368 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL; |
---|
369 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<2> PULLDOWN; |
---|
370 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> LOC=T4; |
---|
371 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL; |
---|
372 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<3> PULLDOWN; |
---|
373 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> LOC=K11; |
---|
374 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL; |
---|
375 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<4> PULLDOWN; |
---|
376 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> LOC=T13; |
---|
377 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL; |
---|
378 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<5> PULLDOWN; |
---|
379 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> LOC=N8; |
---|
380 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL; |
---|
381 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<6> PULLDOWN; |
---|
382 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> LOC=R11; |
---|
383 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL; |
---|
384 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<7> PULLDOWN; |
---|
385 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> LOC=U10; |
---|
386 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL; |
---|
387 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<8> PULLDOWN; |
---|
388 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> LOC=J14; |
---|
389 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL; |
---|
390 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin<9> PULLDOWN; |
---|
391 | Net fpga_0_radio_bridge_slot_1_radio_LD_pin LOC=L3; |
---|
392 | Net fpga_0_radio_bridge_slot_1_radio_LD_pin IOSTANDARD=LVTTL; |
---|
393 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin LOC=C7; |
---|
394 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL; |
---|
395 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin LOC=C9; |
---|
396 | Net fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL; |
---|
397 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin LOC=V9; |
---|
398 | Net fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL; |
---|
399 | Net fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin LOC=K8; |
---|
400 | Net fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL; |
---|
401 | Net fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin LOC=P7; |
---|
402 | Net fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin IOSTANDARD=LVTTL; |
---|
403 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO LOC=G12; |
---|
404 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO IOSTANDARD=LVTTL; |
---|
405 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO SLEW = SLOW; |
---|
406 | Net fpga_0_radio_bridge_slot_1_radio_EEPROM_IO DRIVE = 8; |
---|
407 | |
---|
408 | #### Module radio_bridge_slot_2 constraints |
---|
409 | |
---|
410 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AD5; |
---|
411 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin IOSTANDARD=LVTTL; |
---|
412 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AA4; |
---|
413 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> IOSTANDARD = LVTTL; |
---|
414 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AH5; |
---|
415 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> IOSTANDARD = LVTTL; |
---|
416 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=Y4; |
---|
417 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> IOSTANDARD = LVTTL; |
---|
418 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=V17; |
---|
419 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> IOSTANDARD = LVTTL; |
---|
420 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AC3; |
---|
421 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> IOSTANDARD = LVTTL; |
---|
422 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=Y6; |
---|
423 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> IOSTANDARD = LVTTL; |
---|
424 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AH4; |
---|
425 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> IOSTANDARD = LVTTL; |
---|
426 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=V14; |
---|
427 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> IOSTANDARD = LVTTL; |
---|
428 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=U15; |
---|
429 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> IOSTANDARD = LVTTL; |
---|
430 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=W6; |
---|
431 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> IOSTANDARD = LVTTL; |
---|
432 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG18; |
---|
433 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> IOSTANDARD = LVTTL; |
---|
434 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=V15; |
---|
435 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> IOSTANDARD = LVTTL; |
---|
436 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=V5; |
---|
437 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> IOSTANDARD = LVTTL; |
---|
438 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AA10; |
---|
439 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> IOSTANDARD = LVTTL; |
---|
440 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=Y11; |
---|
441 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> IOSTANDARD = LVTTL; |
---|
442 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AA9; |
---|
443 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> IOSTANDARD = LVTTL; |
---|
444 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=V7; |
---|
445 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> IOSTANDARD = LVTTL; |
---|
446 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=U6; |
---|
447 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> IOSTANDARD = LVTTL; |
---|
448 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AB11; |
---|
449 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> IOSTANDARD = LVTTL; |
---|
450 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=W4; |
---|
451 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> IOSTANDARD = LVTTL; |
---|
452 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=V12; |
---|
453 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> IOSTANDARD = LVTTL; |
---|
454 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AB7; |
---|
455 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
456 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AE7; |
---|
457 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
458 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AC7; |
---|
459 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
460 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AC5; |
---|
461 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
462 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AE4; |
---|
463 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
464 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AD4; |
---|
465 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
466 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AD7; |
---|
467 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
468 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AD6; |
---|
469 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
470 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=W14; |
---|
471 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
472 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=U5; |
---|
473 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
474 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=W5; |
---|
475 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
476 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AA11; |
---|
477 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
478 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=W9; |
---|
479 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
480 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=Y12; |
---|
481 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
482 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AP4; |
---|
483 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> IOSTANDARD = LVTTL; |
---|
484 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AR3; |
---|
485 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> IOSTANDARD = LVTTL; |
---|
486 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AT4; |
---|
487 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> IOSTANDARD = LVTTL; |
---|
488 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AR4; |
---|
489 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> IOSTANDARD = LVTTL; |
---|
490 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AT5; |
---|
491 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> IOSTANDARD = LVTTL; |
---|
492 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AN3; |
---|
493 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> IOSTANDARD = LVTTL; |
---|
494 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AT3; |
---|
495 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> IOSTANDARD = LVTTL; |
---|
496 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5; |
---|
497 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> IOSTANDARD = LVTTL; |
---|
498 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AM7; |
---|
499 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> IOSTANDARD = LVTTL; |
---|
500 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AU6; |
---|
501 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> IOSTANDARD = LVTTL; |
---|
502 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AP5; |
---|
503 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> IOSTANDARD = LVTTL; |
---|
504 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AN5; |
---|
505 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> IOSTANDARD = LVTTL; |
---|
506 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AT6; |
---|
507 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> IOSTANDARD = LVTTL; |
---|
508 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AM6; |
---|
509 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> IOSTANDARD = LVTTL; |
---|
510 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AL6; |
---|
511 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> IOSTANDARD = LVTTL; |
---|
512 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AL8; |
---|
513 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> IOSTANDARD = LVTTL; |
---|
514 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AF8; |
---|
515 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
516 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AF9; |
---|
517 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
518 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AH8; |
---|
519 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
520 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AG7; |
---|
521 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
522 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AJ6; |
---|
523 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
524 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AN4; |
---|
525 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
526 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AG8; |
---|
527 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
528 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AM5; |
---|
529 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
530 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AJ5; |
---|
531 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
532 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AK6; |
---|
533 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
534 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AH7; |
---|
535 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
536 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AJ4; |
---|
537 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
538 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AL4; |
---|
539 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
540 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AB15; |
---|
541 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
542 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AC14; |
---|
543 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL; |
---|
544 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AK4; |
---|
545 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL; |
---|
546 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AC9; |
---|
547 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin IOSTANDARD=LVTTL; |
---|
548 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AK8; |
---|
549 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin IOSTANDARD=LVTTL; |
---|
550 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK7; |
---|
551 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin IOSTANDARD=LVTTL; |
---|
552 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AB12; |
---|
553 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin IOSTANDARD=LVTTL; |
---|
554 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AG3; |
---|
555 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin IOSTANDARD=LVTTL; |
---|
556 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AE8; |
---|
557 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin IOSTANDARD=LVTTL; |
---|
558 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AB3; |
---|
559 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin IOSTANDARD=LVTTL; |
---|
560 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=W16; |
---|
561 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin IOSTANDARD=LVTTL; |
---|
562 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AB10; |
---|
563 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin IOSTANDARD=LVTTL; |
---|
564 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AC4; |
---|
565 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin IOSTANDARD=LVTTL; |
---|
566 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=W7; |
---|
567 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin IOSTANDARD=LVTTL; |
---|
568 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AC8; |
---|
569 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin IOSTANDARD=LVTTL; |
---|
570 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=U3; |
---|
571 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> IOSTANDARD=LVTTL; |
---|
572 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=Y7; |
---|
573 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> IOSTANDARD=LVTTL; |
---|
574 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA8; |
---|
575 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> IOSTANDARD=LVTTL; |
---|
576 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=W10; |
---|
577 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> IOSTANDARD=LVTTL; |
---|
578 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=V4; |
---|
579 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> IOSTANDARD=LVTTL; |
---|
580 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AA5; |
---|
581 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL; |
---|
582 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AF4; |
---|
583 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL; |
---|
584 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=Y8; |
---|
585 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL; |
---|
586 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AA14; |
---|
587 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL; |
---|
588 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=Y13; |
---|
589 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> IOSTANDARD=LVTTL; |
---|
590 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AH3; |
---|
591 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> IOSTANDARD=LVTTL; |
---|
592 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=W15; |
---|
593 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> IOSTANDARD=LVTTL; |
---|
594 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AA13; |
---|
595 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> IOSTANDARD=LVTTL; |
---|
596 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AF5; |
---|
597 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL; |
---|
598 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AB13; |
---|
599 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL; |
---|
600 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AK3; |
---|
601 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL; |
---|
602 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AH9; |
---|
603 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL; |
---|
604 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AD10; |
---|
605 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL; |
---|
606 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> PULLDOWN; |
---|
607 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AD11; |
---|
608 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL; |
---|
609 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> PULLDOWN; |
---|
610 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AE3; |
---|
611 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL; |
---|
612 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> PULLDOWN; |
---|
613 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AC13; |
---|
614 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL; |
---|
615 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> PULLDOWN; |
---|
616 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AF3; |
---|
617 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL; |
---|
618 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> PULLDOWN; |
---|
619 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AM3; |
---|
620 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL; |
---|
621 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> PULLDOWN; |
---|
622 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AG10; |
---|
623 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL; |
---|
624 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> PULLDOWN; |
---|
625 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AF10; |
---|
626 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL; |
---|
627 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> PULLDOWN; |
---|
628 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AL5; |
---|
629 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL; |
---|
630 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> PULLDOWN; |
---|
631 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AM8; |
---|
632 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL; |
---|
633 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> PULLDOWN; |
---|
634 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AD9; |
---|
635 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin IOSTANDARD=LVTTL; |
---|
636 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=V13; |
---|
637 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL; |
---|
638 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=Y9; |
---|
639 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL; |
---|
640 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AC12; |
---|
641 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL; |
---|
642 | Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin LOC=AL3; |
---|
643 | Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL; |
---|
644 | Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin LOC=AC10; |
---|
645 | Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin IOSTANDARD=LVTTL; |
---|
646 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO LOC=AE6; |
---|
647 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IOSTANDARD=LVTTL; |
---|
648 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO SLEW = SLOW; |
---|
649 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO DRIVE = 8; |
---|
650 | |
---|
651 | #### Module radio_bridge_slot_3 constraints |
---|
652 | |
---|
653 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AC29; |
---|
654 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin IOSTANDARD=LVTTL; |
---|
655 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AG28; |
---|
656 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> IOSTANDARD = LVTTL; |
---|
657 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AC24; |
---|
658 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> IOSTANDARD = LVTTL; |
---|
659 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AD31; |
---|
660 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> IOSTANDARD = LVTTL; |
---|
661 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AA24; |
---|
662 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> IOSTANDARD = LVTTL; |
---|
663 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AG30; |
---|
664 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> IOSTANDARD = LVTTL; |
---|
665 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AB23; |
---|
666 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> IOSTANDARD = LVTTL; |
---|
667 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AH29; |
---|
668 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> IOSTANDARD = LVTTL; |
---|
669 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AM33; |
---|
670 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> IOSTANDARD = LVTTL; |
---|
671 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AF33; |
---|
672 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> IOSTANDARD = LVTTL; |
---|
673 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AG31; |
---|
674 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> IOSTANDARD = LVTTL; |
---|
675 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AM22; |
---|
676 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> IOSTANDARD = LVTTL; |
---|
677 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AH30; |
---|
678 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> IOSTANDARD = LVTTL; |
---|
679 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AG32; |
---|
680 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> IOSTANDARD = LVTTL; |
---|
681 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AF31; |
---|
682 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> IOSTANDARD = LVTTL; |
---|
683 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AH34; |
---|
684 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> IOSTANDARD = LVTTL; |
---|
685 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AK32; |
---|
686 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> IOSTANDARD = LVTTL; |
---|
687 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AF34; |
---|
688 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> IOSTANDARD = LVTTL; |
---|
689 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AN34; |
---|
690 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> IOSTANDARD = LVTTL; |
---|
691 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AJ36; |
---|
692 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> IOSTANDARD = LVTTL; |
---|
693 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AN33; |
---|
694 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> IOSTANDARD = LVTTL; |
---|
695 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AH35; |
---|
696 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> IOSTANDARD = LVTTL; |
---|
697 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AA26; |
---|
698 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
699 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AE29; |
---|
700 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
701 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AA29; |
---|
702 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
703 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AD29; |
---|
704 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
705 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AB26; |
---|
706 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
707 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AB27; |
---|
708 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
709 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AA28; |
---|
710 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
711 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AC28; |
---|
712 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
713 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AL34; |
---|
714 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
715 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AJ34; |
---|
716 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
717 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AK33; |
---|
718 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
719 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AK34; |
---|
720 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
721 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AJ35; |
---|
722 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
723 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AG33; |
---|
724 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
725 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB35; |
---|
726 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> IOSTANDARD = LVTTL; |
---|
727 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AC34; |
---|
728 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> IOSTANDARD = LVTTL; |
---|
729 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AA30; |
---|
730 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> IOSTANDARD = LVTTL; |
---|
731 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=Y27; |
---|
732 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> IOSTANDARD = LVTTL; |
---|
733 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB31; |
---|
734 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> IOSTANDARD = LVTTL; |
---|
735 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=N37; |
---|
736 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> IOSTANDARD = LVTTL; |
---|
737 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA31; |
---|
738 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> IOSTANDARD = LVTTL; |
---|
739 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=R34; |
---|
740 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> IOSTANDARD = LVTTL; |
---|
741 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC32; |
---|
742 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> IOSTANDARD = LVTTL; |
---|
743 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=Y32; |
---|
744 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> IOSTANDARD = LVTTL; |
---|
745 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AD35; |
---|
746 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> IOSTANDARD = LVTTL; |
---|
747 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=Y34; |
---|
748 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> IOSTANDARD = LVTTL; |
---|
749 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=P37; |
---|
750 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> IOSTANDARD = LVTTL; |
---|
751 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=R36; |
---|
752 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> IOSTANDARD = LVTTL; |
---|
753 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=T35; |
---|
754 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> IOSTANDARD = LVTTL; |
---|
755 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=Y33; |
---|
756 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> IOSTANDARD = LVTTL; |
---|
757 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=V34; |
---|
758 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
759 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AC35; |
---|
760 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
761 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=V33; |
---|
762 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
763 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=Y36; |
---|
764 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
765 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=U37; |
---|
766 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
767 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AB36; |
---|
768 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
769 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=U35; |
---|
770 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
771 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=Y37; |
---|
772 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
773 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=W37; |
---|
774 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
775 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AA34; |
---|
776 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
777 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=W36; |
---|
778 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
779 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AA35; |
---|
780 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
781 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=W30; |
---|
782 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
783 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=W32; |
---|
784 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
785 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=V35; |
---|
786 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL; |
---|
787 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=W34; |
---|
788 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL; |
---|
789 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=T36; |
---|
790 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin IOSTANDARD=LVTTL; |
---|
791 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=W35; |
---|
792 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin IOSTANDARD=LVTTL; |
---|
793 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AA36; |
---|
794 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin IOSTANDARD=LVTTL; |
---|
795 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AC37; |
---|
796 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin IOSTANDARD=LVTTL; |
---|
797 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AD37; |
---|
798 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin IOSTANDARD=LVTTL; |
---|
799 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AF36; |
---|
800 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin IOSTANDARD=LVTTL; |
---|
801 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AD27; |
---|
802 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin IOSTANDARD=LVTTL; |
---|
803 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AE37; |
---|
804 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin IOSTANDARD=LVTTL; |
---|
805 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=Y26; |
---|
806 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin IOSTANDARD=LVTTL; |
---|
807 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AC25; |
---|
808 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin IOSTANDARD=LVTTL; |
---|
809 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AM36; |
---|
810 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin IOSTANDARD=LVTTL; |
---|
811 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AN35; |
---|
812 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin IOSTANDARD=LVTTL; |
---|
813 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AN37; |
---|
814 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> IOSTANDARD=LVTTL; |
---|
815 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AJ37; |
---|
816 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> IOSTANDARD=LVTTL; |
---|
817 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AL35; |
---|
818 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> IOSTANDARD=LVTTL; |
---|
819 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AE33; |
---|
820 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> IOSTANDARD=LVTTL; |
---|
821 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AM35; |
---|
822 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> IOSTANDARD=LVTTL; |
---|
823 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AF28; |
---|
824 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL; |
---|
825 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AD34; |
---|
826 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL; |
---|
827 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AK36; |
---|
828 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL; |
---|
829 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AE28; |
---|
830 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL; |
---|
831 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG36; |
---|
832 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> IOSTANDARD=LVTTL; |
---|
833 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AG37; |
---|
834 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> IOSTANDARD=LVTTL; |
---|
835 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=T34; |
---|
836 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> IOSTANDARD=LVTTL; |
---|
837 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AH37; |
---|
838 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> IOSTANDARD=LVTTL; |
---|
839 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AD32; |
---|
840 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL; |
---|
841 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=K36; |
---|
842 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL; |
---|
843 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=W29; |
---|
844 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL; |
---|
845 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=K37; |
---|
846 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL; |
---|
847 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=P35; |
---|
848 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL; |
---|
849 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> PULLDOWN; |
---|
850 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AB28; |
---|
851 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL; |
---|
852 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> PULLDOWN; |
---|
853 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=M36; |
---|
854 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL; |
---|
855 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> PULLDOWN; |
---|
856 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AF35; |
---|
857 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL; |
---|
858 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> PULLDOWN; |
---|
859 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=L36; |
---|
860 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL; |
---|
861 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> PULLDOWN; |
---|
862 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=M37; |
---|
863 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL; |
---|
864 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> PULLDOWN; |
---|
865 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=R37; |
---|
866 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL; |
---|
867 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> PULLDOWN; |
---|
868 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=P36; |
---|
869 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL; |
---|
870 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> PULLDOWN; |
---|
871 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AE34; |
---|
872 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL; |
---|
873 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> PULLDOWN; |
---|
874 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=Y31; |
---|
875 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL; |
---|
876 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> PULLDOWN; |
---|
877 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AB37; |
---|
878 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin IOSTANDARD=LVTTL; |
---|
879 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AM37; |
---|
880 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL; |
---|
881 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AL36; |
---|
882 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL; |
---|
883 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=U36; |
---|
884 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL; |
---|
885 | Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin LOC=AG35; |
---|
886 | Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL; |
---|
887 | Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin LOC=AE36; |
---|
888 | Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin IOSTANDARD=LVTTL; |
---|
889 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO LOC=AE32; |
---|
890 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IOSTANDARD=LVTTL; |
---|
891 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO SLEW = SLOW; |
---|
892 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO DRIVE = 8; |
---|
893 | |
---|
894 | #### Module radio_bridge_slot_4 constraints |
---|
895 | |
---|
896 | Net fpga_0_radio_bridge_slot_4_converter_clock_out_pin LOC=H33; |
---|
897 | Net fpga_0_radio_bridge_slot_4_converter_clock_out_pin IOSTANDARD=LVTTL; |
---|
898 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<0> LOC=G30; |
---|
899 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<0> IOSTANDARD = LVTTL; |
---|
900 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<1> LOC=U33; |
---|
901 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<1> IOSTANDARD = LVTTL; |
---|
902 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<2> LOC=G32; |
---|
903 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<2> IOSTANDARD = LVTTL; |
---|
904 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<3> LOC=J34; |
---|
905 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<3> IOSTANDARD = LVTTL; |
---|
906 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<4> LOC=K29; |
---|
907 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<4> IOSTANDARD = LVTTL; |
---|
908 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<5> LOC=J35; |
---|
909 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<5> IOSTANDARD = LVTTL; |
---|
910 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<6> LOC=U32; |
---|
911 | Net fpga_0_radio_bridge_slot_4_radio_B_pin<6> IOSTANDARD = LVTTL; |
---|
912 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<0> LOC=K26; |
---|
913 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<0> IOSTANDARD = LVTTL; |
---|
914 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<1> LOC=P30; |
---|
915 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<1> IOSTANDARD = LVTTL; |
---|
916 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<2> LOC=M27; |
---|
917 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<2> IOSTANDARD = LVTTL; |
---|
918 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<3> LOC=AF23; |
---|
919 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<3> IOSTANDARD = LVTTL; |
---|
920 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<4> LOC=T29; |
---|
921 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<4> IOSTANDARD = LVTTL; |
---|
922 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<5> LOC=R31; |
---|
923 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<5> IOSTANDARD = LVTTL; |
---|
924 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<6> LOC=V30; |
---|
925 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<6> IOSTANDARD = LVTTL; |
---|
926 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<7> LOC=M31; |
---|
927 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<7> IOSTANDARD = LVTTL; |
---|
928 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<8> LOC=W26; |
---|
929 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<8> IOSTANDARD = LVTTL; |
---|
930 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<9> LOC=K27; |
---|
931 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<9> IOSTANDARD = LVTTL; |
---|
932 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<10> LOC=M26; |
---|
933 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<10> IOSTANDARD = LVTTL; |
---|
934 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<11> LOC=L29; |
---|
935 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<11> IOSTANDARD = LVTTL; |
---|
936 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<12> LOC=V25; |
---|
937 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<12> IOSTANDARD = LVTTL; |
---|
938 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<13> LOC=W27; |
---|
939 | Net fpga_0_radio_bridge_slot_4_radio_ADC_I_pin<13> IOSTANDARD = LVTTL; |
---|
940 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<0> LOC=K28; |
---|
941 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
942 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<1> LOC=J32; |
---|
943 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
944 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<2> LOC=K33; |
---|
945 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
946 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<3> LOC=H32; |
---|
947 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
948 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<4> LOC=L30; |
---|
949 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
950 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<5> LOC=M33; |
---|
951 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
952 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<6> LOC=M35; |
---|
953 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
954 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<7> LOC=P32; |
---|
955 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
956 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<8> LOC=U28; |
---|
957 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
958 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<9> LOC=N33; |
---|
959 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
960 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<10> LOC=U27; |
---|
961 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
962 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<11> LOC=L28; |
---|
963 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
964 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<12> LOC=V28; |
---|
965 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
966 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<13> LOC=M28; |
---|
967 | Net fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
968 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<0> LOC=E32; |
---|
969 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<0> IOSTANDARD = LVTTL; |
---|
970 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<1> LOC=D27; |
---|
971 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<1> IOSTANDARD = LVTTL; |
---|
972 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<2> LOC=E33; |
---|
973 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<2> IOSTANDARD = LVTTL; |
---|
974 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<3> LOC=F34; |
---|
975 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<3> IOSTANDARD = LVTTL; |
---|
976 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<4> LOC=F35; |
---|
977 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<4> IOSTANDARD = LVTTL; |
---|
978 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<5> LOC=F33; |
---|
979 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<5> IOSTANDARD = LVTTL; |
---|
980 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<6> LOC=D31; |
---|
981 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<6> IOSTANDARD = LVTTL; |
---|
982 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<7> LOC=D30; |
---|
983 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<7> IOSTANDARD = LVTTL; |
---|
984 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<8> LOC=E28; |
---|
985 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<8> IOSTANDARD = LVTTL; |
---|
986 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<9> LOC=F36; |
---|
987 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<9> IOSTANDARD = LVTTL; |
---|
988 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<10> LOC=G33; |
---|
989 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<10> IOSTANDARD = LVTTL; |
---|
990 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<11> LOC=G35; |
---|
991 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<11> IOSTANDARD = LVTTL; |
---|
992 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<12> LOC=D29; |
---|
993 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<12> IOSTANDARD = LVTTL; |
---|
994 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<13> LOC=C29; |
---|
995 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<13> IOSTANDARD = LVTTL; |
---|
996 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<14> LOC=D37; |
---|
997 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<14> IOSTANDARD = LVTTL; |
---|
998 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<15> LOC=E37; |
---|
999 | Net fpga_0_radio_bridge_slot_4_radio_DAC_I_pin<15> IOSTANDARD = LVTTL; |
---|
1000 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<0> LOC=D26; |
---|
1001 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
1002 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<1> LOC=C27; |
---|
1003 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
1004 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<2> LOC=G25; |
---|
1005 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
1006 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<3> LOC=C25; |
---|
1007 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
1008 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<4> LOC=F29; |
---|
1009 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
1010 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<5> LOC=F24; |
---|
1011 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
1012 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<6> LOC=E26; |
---|
1013 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
1014 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<7> LOC=D32; |
---|
1015 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
1016 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<8> LOC=F28; |
---|
1017 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
1018 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<9> LOC=F31; |
---|
1019 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
1020 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<10> LOC=E27; |
---|
1021 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
1022 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<11> LOC=F26; |
---|
1023 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
1024 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<12> LOC=H34; |
---|
1025 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
1026 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<13> LOC=E31; |
---|
1027 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
1028 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<14> LOC=F25; |
---|
1029 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL; |
---|
1030 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<15> LOC=E29; |
---|
1031 | Net fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL; |
---|
1032 | Net fpga_0_radio_bridge_slot_4_dac_spi_data_pin LOC=C28; |
---|
1033 | Net fpga_0_radio_bridge_slot_4_dac_spi_data_pin IOSTANDARD=LVTTL; |
---|
1034 | Net fpga_0_radio_bridge_slot_4_dac_spi_cs_pin LOC=D25; |
---|
1035 | Net fpga_0_radio_bridge_slot_4_dac_spi_cs_pin IOSTANDARD=LVTTL; |
---|
1036 | Net fpga_0_radio_bridge_slot_4_dac_spi_clk_pin LOC=G28; |
---|
1037 | Net fpga_0_radio_bridge_slot_4_dac_spi_clk_pin IOSTANDARD=LVTTL; |
---|
1038 | Net fpga_0_radio_bridge_slot_4_radio_spi_clk_pin LOC=J29; |
---|
1039 | Net fpga_0_radio_bridge_slot_4_radio_spi_clk_pin IOSTANDARD=LVTTL; |
---|
1040 | Net fpga_0_radio_bridge_slot_4_radio_spi_data_pin LOC=D24; |
---|
1041 | Net fpga_0_radio_bridge_slot_4_radio_spi_data_pin IOSTANDARD=LVTTL; |
---|
1042 | Net fpga_0_radio_bridge_slot_4_radio_spi_cs_pin LOC=H28; |
---|
1043 | Net fpga_0_radio_bridge_slot_4_radio_spi_cs_pin IOSTANDARD=LVTTL; |
---|
1044 | Net fpga_0_radio_bridge_slot_4_radio_SHDN_pin LOC=K34; |
---|
1045 | Net fpga_0_radio_bridge_slot_4_radio_SHDN_pin IOSTANDARD=LVTTL; |
---|
1046 | Net fpga_0_radio_bridge_slot_4_radio_TxEn_pin LOC=H30; |
---|
1047 | Net fpga_0_radio_bridge_slot_4_radio_TxEn_pin IOSTANDARD=LVTTL; |
---|
1048 | Net fpga_0_radio_bridge_slot_4_radio_RxEn_pin LOC=L34; |
---|
1049 | Net fpga_0_radio_bridge_slot_4_radio_RxEn_pin IOSTANDARD=LVTTL; |
---|
1050 | Net fpga_0_radio_bridge_slot_4_radio_RxHP_pin LOC=J26; |
---|
1051 | Net fpga_0_radio_bridge_slot_4_radio_RxHP_pin IOSTANDARD=LVTTL; |
---|
1052 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin LOC=H27; |
---|
1053 | Net fpga_0_radio_bridge_slot_4_radio_24PA_pin IOSTANDARD=LVTTL; |
---|
1054 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin LOC=L26; |
---|
1055 | Net fpga_0_radio_bridge_slot_4_radio_5PA_pin IOSTANDARD=LVTTL; |
---|
1056 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> LOC=U31; |
---|
1057 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<0> IOSTANDARD=LVTTL; |
---|
1058 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> LOC=V29; |
---|
1059 | Net fpga_0_radio_bridge_slot_4_radio_ANTSW_pin<1> IOSTANDARD=LVTTL; |
---|
1060 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> LOC=U26; |
---|
1061 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<0> IOSTANDARD=LVTTL; |
---|
1062 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> LOC=N35; |
---|
1063 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<1> IOSTANDARD=LVTTL; |
---|
1064 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> LOC=N34; |
---|
1065 | Net fpga_0_radio_bridge_slot_4_radio_LED_pin<2> IOSTANDARD=LVTTL; |
---|
1066 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin LOC=K32; |
---|
1067 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL; |
---|
1068 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin LOC=G31; |
---|
1069 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL; |
---|
1070 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin LOC=U30; |
---|
1071 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL; |
---|
1072 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin LOC=M32; |
---|
1073 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL; |
---|
1074 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<0> LOC=C30; |
---|
1075 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<0> IOSTANDARD=LVTTL; |
---|
1076 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<1> LOC=H25; |
---|
1077 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<1> IOSTANDARD=LVTTL; |
---|
1078 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<2> LOC=C24; |
---|
1079 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<2> IOSTANDARD=LVTTL; |
---|
1080 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<3> LOC=J27; |
---|
1081 | Net fpga_0_radio_bridge_slot_4_radio_DIPSW_pin<3> IOSTANDARD=LVTTL; |
---|
1082 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin LOC=L33; |
---|
1083 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL; |
---|
1084 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin LOC=J37; |
---|
1085 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL; |
---|
1086 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin LOC=H37; |
---|
1087 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL; |
---|
1088 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin LOC=C35; |
---|
1089 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL; |
---|
1090 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> LOC=J36; |
---|
1091 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL; |
---|
1092 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<0> PULLDOWN; |
---|
1093 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> LOC=C33; |
---|
1094 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL; |
---|
1095 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<1> PULLDOWN; |
---|
1096 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> LOC=G37; |
---|
1097 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL; |
---|
1098 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<2> PULLDOWN; |
---|
1099 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> LOC=C32; |
---|
1100 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL; |
---|
1101 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<3> PULLDOWN; |
---|
1102 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> LOC=G36; |
---|
1103 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL; |
---|
1104 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<4> PULLDOWN; |
---|
1105 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> LOC=D36; |
---|
1106 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL; |
---|
1107 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<5> PULLDOWN; |
---|
1108 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> LOC=D34; |
---|
1109 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL; |
---|
1110 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<6> PULLDOWN; |
---|
1111 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> LOC=E36; |
---|
1112 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL; |
---|
1113 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<7> PULLDOWN; |
---|
1114 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> LOC=E34; |
---|
1115 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL; |
---|
1116 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<8> PULLDOWN; |
---|
1117 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> LOC=H35; |
---|
1118 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL; |
---|
1119 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin<9> PULLDOWN; |
---|
1120 | Net fpga_0_radio_bridge_slot_4_radio_LD_pin LOC=E24; |
---|
1121 | Net fpga_0_radio_bridge_slot_4_radio_LD_pin IOSTANDARD=LVTTL; |
---|
1122 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin LOC=N32; |
---|
1123 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL; |
---|
1124 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin LOC=V27; |
---|
1125 | Net fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL; |
---|
1126 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin LOC=D35; |
---|
1127 | Net fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL; |
---|
1128 | Net fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin LOC=F30; |
---|
1129 | Net fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL; |
---|
1130 | Net fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin LOC=G26; |
---|
1131 | Net fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin IOSTANDARD=LVTTL; |
---|
1132 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO LOC=L31; |
---|
1133 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO IOSTANDARD=LVTTL; |
---|
1134 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO SLEW = SLOW; |
---|
1135 | Net fpga_0_radio_bridge_slot_4_radio_EEPROM_IO DRIVE = 8; |
---|
1136 | |
---|
1137 | #### Module eeprom_controller constraints |
---|
1138 | |
---|
1139 | Net fpga_0_eeprom_controller_DQ0_pin LOC=AH22; |
---|
1140 | Net fpga_0_eeprom_controller_DQ0_pin IOSTANDARD = LVTTL; |
---|
1141 | Net fpga_0_eeprom_controller_DQ0_pin SLEW = SLOW; |
---|
1142 | Net fpga_0_eeprom_controller_DQ0_pin DRIVE = 8; |
---|
1143 | |
---|
1144 | Net mgt_null_controller_0_rxn_mgt01_pin<0> LOC = A22; |
---|
1145 | Net mgt_null_controller_0_rxp_mgt01_pin<0> LOC = A21; |
---|
1146 | Net mgt_null_controller_0_txn_mgt01_pin<0> LOC = A25; |
---|
1147 | Net mgt_null_controller_0_txp_mgt01_pin<0> LOC = A24; |
---|
1148 | INST *mgt01*INST_A* LOC = GT11_X0Y9; |
---|
1149 | |
---|
1150 | Net mgt_null_controller_0_rxn_mgt01_pin<1> LOC = A30; |
---|
1151 | Net mgt_null_controller_0_rxp_mgt01_pin<1> LOC = A29; |
---|
1152 | Net mgt_null_controller_0_txn_mgt01_pin<1> LOC = A27; |
---|
1153 | Net mgt_null_controller_0_txp_mgt01_pin<1> LOC = A26; |
---|
1154 | INST *mgt01*INST_B* LOC = GT11_X0Y8; |
---|
1155 | |
---|
1156 | Net mgt_null_controller_0_rxn_mgt02_pin<0> LOC = A32; |
---|
1157 | Net mgt_null_controller_0_rxp_mgt02_pin<0> LOC = A31; |
---|
1158 | Net mgt_null_controller_0_txn_mgt02_pin<0> LOC = A35; |
---|
1159 | Net mgt_null_controller_0_txp_mgt02_pin<0> LOC = A34; |
---|
1160 | INST *mgt02*INST_A* LOC = GT11_X0Y7; |
---|
1161 | |
---|
1162 | Net mgt_null_controller_0_rxn_mgt02_pin<1> LOC = D39; |
---|
1163 | Net mgt_null_controller_0_rxp_mgt02_pin<1> LOC = C39; |
---|
1164 | Net mgt_null_controller_0_txn_mgt02_pin<1> LOC = A37; |
---|
1165 | Net mgt_null_controller_0_txp_mgt02_pin<1> LOC = A36; |
---|
1166 | INST *mgt02*INST_B* LOC = GT11_X0Y6; |
---|
1167 | |
---|
1168 | Net mgt_null_controller_0_rxn_mgt03_pin<0> LOC = K39; |
---|
1169 | Net mgt_null_controller_0_rxp_mgt03_pin<0> LOC = J39; |
---|
1170 | Net mgt_null_controller_0_txn_mgt03_pin<0> LOC = N39; |
---|
1171 | Net mgt_null_controller_0_txp_mgt03_pin<0> LOC = M39; |
---|
1172 | INST *mgt03*INST_A* LOC = GT11_X0Y5; |
---|
1173 | |
---|
1174 | Net mgt_null_controller_0_rxn_mgt03_pin<1> LOC = V39; |
---|
1175 | Net mgt_null_controller_0_rxp_mgt03_pin<1> LOC = U39; |
---|
1176 | Net mgt_null_controller_0_txn_mgt03_pin<1> LOC = R39; |
---|
1177 | Net mgt_null_controller_0_txp_mgt03_pin<1> LOC = P39; |
---|
1178 | INST *mgt03*INST_B* LOC = GT11_X0Y4; |
---|
1179 | |
---|
1180 | Net mgt_null_controller_0_rxn_mgt05_pin<0> LOC = AM39; |
---|
1181 | Net mgt_null_controller_0_rxp_mgt05_pin<0> LOC = AL39; |
---|
1182 | Net mgt_null_controller_0_txn_mgt05_pin<0> LOC = AR39; |
---|
1183 | Net mgt_null_controller_0_txp_mgt05_pin<0> LOC = AP39; |
---|
1184 | INST *mgt05*INST_A* LOC = GT11_X0Y3; |
---|
1185 | |
---|
1186 | Net mgt_null_controller_0_rxn_mgt05_pin<1> LOC = AW36; |
---|
1187 | Net mgt_null_controller_0_rxp_mgt05_pin<1> LOC = AW37; |
---|
1188 | Net mgt_null_controller_0_txn_mgt05_pin<1> LOC = AU39; |
---|
1189 | Net mgt_null_controller_0_txp_mgt05_pin<1> LOC = AT39; |
---|
1190 | INST *mgt05*INST_B* LOC = GT11_X0Y2; |
---|
1191 | |
---|
1192 | Net mgt_null_controller_0_rxn_mgt06_pin<0> LOC = AW30; |
---|
1193 | Net mgt_null_controller_0_rxp_mgt06_pin<0> LOC = AW31; |
---|
1194 | Net mgt_null_controller_0_txn_mgt06_pin<0> LOC = AW27; |
---|
1195 | Net mgt_null_controller_0_txp_mgt06_pin<0> LOC = AW28; |
---|
1196 | INST *mgt06*INST_A* LOC = GT11_X0Y1; |
---|
1197 | |
---|
1198 | Net mgt_null_controller_0_rxn_mgt06_pin<1> LOC = AW21; |
---|
1199 | Net mgt_null_controller_0_rxp_mgt06_pin<1> LOC = AW22; |
---|
1200 | Net mgt_null_controller_0_txn_mgt06_pin<1> LOC = AW24; |
---|
1201 | Net mgt_null_controller_0_txp_mgt06_pin<1> LOC = AW25; |
---|
1202 | INST *mgt06*INST_B* LOC = GT11_X0Y0; |
---|
1203 | |
---|
1204 | Net mgt_null_controller_0_rxn_mgt09_pin<0> LOC = AW10; |
---|
1205 | Net mgt_null_controller_0_rxp_mgt09_pin<0> LOC = AW9; |
---|
1206 | Net mgt_null_controller_0_txn_mgt09_pin<0> LOC = AW13; |
---|
1207 | Net mgt_null_controller_0_txp_mgt09_pin<0> LOC = AW12; |
---|
1208 | INST *mgt09*INST_A* LOC = GT11_X1Y1; |
---|
1209 | |
---|
1210 | Net mgt_null_controller_0_rxn_mgt09_pin<1> LOC = AW19; |
---|
1211 | Net mgt_null_controller_0_rxp_mgt09_pin<1> LOC = AW18; |
---|
1212 | Net mgt_null_controller_0_txn_mgt09_pin<1> LOC = AW16; |
---|
1213 | Net mgt_null_controller_0_txp_mgt09_pin<1> LOC = AW15; |
---|
1214 | INST *mgt09*INST_B* LOC = GT11_X1Y0; |
---|
1215 | |
---|
1216 | Net mgt_null_controller_0_rxn_mgt10_pin<0> LOC = AM1; |
---|
1217 | Net mgt_null_controller_0_rxp_mgt10_pin<0> LOC = AL1; |
---|
1218 | Net mgt_null_controller_0_txn_mgt10_pin<0> LOC = AR1; |
---|
1219 | Net mgt_null_controller_0_txp_mgt10_pin<0> LOC = AP1; |
---|
1220 | INST *mgt10*INST_A* LOC = GT11_X1Y3; |
---|
1221 | |
---|
1222 | Net mgt_null_controller_0_rxn_mgt10_pin<1> LOC = AW4; |
---|
1223 | Net mgt_null_controller_0_rxp_mgt10_pin<1> LOC = AW3; |
---|
1224 | Net mgt_null_controller_0_txn_mgt10_pin<1> LOC = AU1; |
---|
1225 | Net mgt_null_controller_0_txp_mgt10_pin<1> LOC = AT1; |
---|
1226 | INST *mgt10*INST_B* LOC = GT11_X1Y2; |
---|
1227 | |
---|
1228 | Net mgt_null_controller_0_rxn_mgt12_pin<0> LOC = K1; |
---|
1229 | Net mgt_null_controller_0_rxp_mgt12_pin<0> LOC = J1; |
---|
1230 | Net mgt_null_controller_0_txn_mgt12_pin<0> LOC = N1; |
---|
1231 | Net mgt_null_controller_0_txp_mgt12_pin<0> LOC = M1; |
---|
1232 | INST *mgt12*INST_A* LOC = GT11_X1Y5; |
---|
1233 | |
---|
1234 | Net mgt_null_controller_0_rxn_mgt12_pin<1> LOC = V1; |
---|
1235 | Net mgt_null_controller_0_rxp_mgt12_pin<1> LOC = U1; |
---|
1236 | Net mgt_null_controller_0_txn_mgt12_pin<1> LOC = R1; |
---|
1237 | Net mgt_null_controller_0_txp_mgt12_pin<1> LOC = P1; |
---|
1238 | INST *mgt12*INST_B* LOC = GT11_X1Y4; |
---|
1239 | |
---|
1240 | Net mgt_null_controller_0_rxn_mgt13_pin<0> LOC = A8; |
---|
1241 | Net mgt_null_controller_0_rxp_mgt13_pin<0> LOC = A9; |
---|
1242 | Net mgt_null_controller_0_txn_mgt13_pin<0> LOC = A5; |
---|
1243 | Net mgt_null_controller_0_txp_mgt13_pin<0> LOC = A6; |
---|
1244 | INST *mgt13*INST_A* LOC = GT11_X1Y7; |
---|
1245 | |
---|
1246 | Net mgt_null_controller_0_rxn_mgt13_pin<1> LOC = D1; |
---|
1247 | Net mgt_null_controller_0_rxp_mgt13_pin<1> LOC = C1; |
---|
1248 | Net mgt_null_controller_0_txn_mgt13_pin<1> LOC = A3; |
---|
1249 | Net mgt_null_controller_0_txp_mgt13_pin<1> LOC = A4; |
---|
1250 | INST *mgt13*INST_B* LOC = GT11_X1Y6; |
---|
1251 | |
---|
1252 | Net mgt_null_controller_0_rxn_mgt14_pin<0> LOC = A18; |
---|
1253 | Net mgt_null_controller_0_rxp_mgt14_pin<0> LOC = A19; |
---|
1254 | Net mgt_null_controller_0_txn_mgt14_pin<0> LOC = A15; |
---|
1255 | Net mgt_null_controller_0_txp_mgt14_pin<0> LOC = A16; |
---|
1256 | INST *mgt14*INST_A* LOC = GT11_X1Y9; |
---|
1257 | |
---|
1258 | Net mgt_null_controller_0_rxn_mgt14_pin<1> LOC = A10; |
---|
1259 | Net mgt_null_controller_0_rxp_mgt14_pin<1> LOC = A11; |
---|
1260 | Net mgt_null_controller_0_txn_mgt14_pin<1> LOC = A13; |
---|
1261 | Net mgt_null_controller_0_txp_mgt14_pin<1> LOC = A14; |
---|
1262 | INST *mgt14*INST_B* LOC = GT11_X1Y8; |
---|