1 | //////////////////////////////////////////////////////////////////////////////// |
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2 | // |
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3 | // File : warplab_mimo.c v6.1 |
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4 | // Date : 2012, July 11. |
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5 | // Author : P. Murphy, S. Gupta, M. Duarte, C. Hunter |
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6 | // |
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7 | // Changelog: |
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8 | // - Added support for WARPxilnet_v3_00 that adds support for the hard TEMACs |
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9 | // inside the Virtex4 |
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10 | // - v2 WARP hardware will use gigabit speeds by default. The Ethernet PHY |
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11 | // advertises its speed as gigabit, so there is no longer a need to |
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12 | // explicitly tell your computer to send at 100Mbit. |
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13 | // - Uses an XPS_Timer core to inact a timeout of WAITDURATION_SEC seconds |
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14 | // to wait for a sync packet. Previously, this timeout was handled by |
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15 | // waiting a set number of packets (e.g. 10 received packets). |
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16 | // - Moved the sync IP address up to a proper broadcast address of X.X.X.255. |
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17 | // This should obviate the need for explicit ARP table entries to handle |
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18 | // sync packets. The v06 WARPLAB M-Code Reference has correspondingly been |
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19 | // updated. |
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20 | // - This source file will compile for either v1 or v2 WARP hardware, assuming |
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21 | // the WARPxilnet and WARP_FPGA_BOARD software libraries are configured |
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22 | // |
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23 | //////////////////////////////////////////////////////////////////////////////// |
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24 | |
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25 | #include "xparameters.h" |
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26 | #include "warp_fpga_board.h" |
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27 | #include <xilnet_config.h> |
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28 | #include <xilnet_xilsock.h> |
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29 | #include <xilnet_mac.h> |
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30 | #include "xstatus.h" |
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31 | #include <stdlib.h> |
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32 | #include <string.h> |
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33 | #include "math.h" |
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34 | #include "radio_controller_basic.h" |
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35 | #include "radio_controller_ext.h" |
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36 | #include "radio_controller_adv.h" |
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37 | #include "radio_controller_5ghz.h" |
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38 | #include "warplab_defines.h" |
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39 | #include "EEPROM.h" |
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40 | #include "warplab_regmacros.h" |
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41 | #include "stdio.h" |
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42 | #include "xtmrctr.h" |
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43 | |
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44 | //#define WARPLAB_CONFIG_2x2 1 // Comment in if board in 2x2 configuration |
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45 | #define WARPLAB_CONFIG_4x4 1 // Comment in if board in 4x4 configuration |
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46 | |
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47 | //Includes for specific FPGA board versions |
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48 | #ifdef WARP_FPGA_BOARD_V1_2 |
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49 | #include "warp_userio.h" |
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50 | #include "xemaclite.h" |
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51 | #include "xemaclite_l.h" |
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52 | #include "xgpio.h" |
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53 | static XGpio GPIO_UserIO; //Instantiates the general-purpose input-output peripheral driver |
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54 | static XEmacLite EmacLiteInstance; /* Instance of the EmacLite */ |
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55 | static XEmacLite_Config *EmacLiteConfigPtr; |
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56 | #define XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ 80000000 //The 10.1 tools don't automatically generate this |
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57 | #elif defined WARP_FPGA_BOARD_V2_2 |
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58 | #define USERIO_BASEADDR XPAR_USERIO_BASEADDR |
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59 | #include "warp_v4_userio.h" |
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60 | #include "xlltemac.h" |
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61 | #include "xllfifo.h" |
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62 | #include "xdmacentral.h" |
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63 | #include "xdmacentral_l.h" |
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64 | static XDmaCentral DmaCentralInst; |
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65 | static XDmaCentral_Config *DMAConfigPtr; |
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66 | XLlTemac TemacInstance; |
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67 | XLlTemac_Config *MacCfgPtr; |
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68 | XLlFifo FifoInstance; |
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69 | #endif |
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70 | |
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71 | #define WARPLAB_TXBUFF_RADIO1 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXBUFF_RADIO1 |
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72 | #define WARPLAB_TXBUFF_RADIO2 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXBUFF_RADIO2 |
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73 | #define WARPLAB_TXBUFF_RADIO3 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXBUFF_RADIO3 |
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74 | #define WARPLAB_TXBUFF_RADIO4 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_TXBUFF_RADIO4 |
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75 | #define WARPLAB_RXBUFF_RADIO1 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RXBUFF_RADIO1 |
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76 | #define WARPLAB_RXBUFF_RADIO2 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RXBUFF_RADIO2 |
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77 | #define WARPLAB_RXBUFF_RADIO3 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RXBUFF_RADIO3 |
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78 | #define WARPLAB_RXBUFF_RADIO4 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RXBUFF_RADIO4 |
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79 | #define WARPLAB_RSSIBUFF_RADIO1 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RSSIBUFF_RADIO1 |
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80 | #define WARPLAB_RSSIBUFF_RADIO2 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RSSIBUFF_RADIO2 |
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81 | #define WARPLAB_RSSIBUFF_RADIO3 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RSSIBUFF_RADIO3 |
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82 | #define WARPLAB_RSSIBUFF_RADIO4 XPAR_WARPLAB_MIMO_4X4_PLBW_0_MEMMAP_RSSIBUFF_RADIO4 |
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83 | |
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84 | #define TEMAC_DEVICE_ID XPAR_LLTEMAC_0_DEVICE_ID |
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85 | #define FIFO_DEVICE_ID XPAR_LLFIFO_0_DEVICE_ID |
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86 | |
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87 | #define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID |
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88 | #define TIMER_COUNTER_0 0 |
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89 | |
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90 | |
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91 | #ifdef WARP_FPGA_BOARD_V1_2 |
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92 | |
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93 | #define ENET_LINK_SPEED 100 |
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94 | |
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95 | #elif defined WARP_FPGA_BOARD_V2_2 |
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96 | |
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97 | #include "warp_v4_userio.h" |
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98 | static XDmaCentral DmaCentralInst; |
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99 | static XDmaCentral_Config *DMAConfigPtr; |
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100 | XLlTemac TemacInstance; |
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101 | XLlTemac_Config *MacCfgPtr; |
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102 | XLlFifo FifoInstance; |
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103 | #define USERIO_BASEADDR XPAR_USERIO_BASEADDR |
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104 | #define ENET_LINK_SPEED 1000 |
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105 | |
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106 | #endif |
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107 | |
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108 | |
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109 | #define BUFSIZE 2000 |
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110 | #define DEBUG_LVL 2 |
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111 | |
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112 | #define WAITDURATION_SEC 2 |
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113 | |
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114 | unsigned int sendPtr32[(BUFSIZE+3)/4]; |
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115 | unsigned char * const sendBuffer = (unsigned char *) sendPtr32; |
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116 | unsigned int receivePtr32[(BUFSIZE+3)/4]; |
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117 | unsigned char * const receiveBuffer = (unsigned char *) receivePtr32; |
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118 | unsigned int myPort; |
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119 | |
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120 | XTmrCtr TmrCtrInstance; |
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121 | |
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122 | int sock; // UDP socket |
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123 | struct sockaddr_in addr; |
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124 | unsigned int alen = 0; |
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125 | char node; |
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126 | |
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127 | unsigned int ReadWrite; |
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128 | unsigned char Radios_WirelessChan; |
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129 | unsigned char Radios_Tx_LPF_Corn_Freq; |
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130 | unsigned char Radios_Rx_LPF_Corn_Freq; |
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131 | unsigned char Radio1_TxGain_BB, Radio1_TxGain_RF, Radio1_RxGain_BB, Radio1_RxGain_RF; |
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132 | unsigned char Radio2_TxGain_BB, Radio2_TxGain_RF, Radio2_RxGain_BB, Radio2_RxGain_RF; |
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133 | unsigned char Radio3_TxGain_BB, Radio3_TxGain_RF, Radio3_RxGain_BB, Radio3_RxGain_RF; |
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134 | unsigned char Radio4_TxGain_BB, Radio4_TxGain_RF, Radio4_RxGain_BB, Radio4_RxGain_RF; |
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135 | |
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136 | #ifdef WARPLAB_CONFIG_2x2 |
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137 | unsigned int radios = RADIO2_ADDR | RADIO3_ADDR; |
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138 | #elif defined WARPLAB_CONFIG_4x4 |
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139 | unsigned int radios = RADIO1_ADDR | RADIO2_ADDR | RADIO3_ADDR | RADIO4_ADDR; |
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140 | #endif |
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141 | unsigned int radio1 = RADIO1_ADDR; |
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142 | unsigned int radio2 = RADIO2_ADDR; |
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143 | unsigned int radio3 = RADIO3_ADDR; |
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144 | unsigned int radio4 = RADIO4_ADDR; |
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145 | |
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146 | unsigned int AgcIsDoneAddr; |
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147 | unsigned int MGC_AGC_Sel_Variable = 0; // By default MGC is selected |
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148 | |
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149 | //---------------------------------- |
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150 | // Functions |
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151 | void sendACK(unsigned int packetNo, unsigned int commandToACK); |
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152 | unsigned char sevenSegmentMap(unsigned char x); |
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153 | int warpphy_applyTxDCOCorrection(unsigned int radioSelection); |
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154 | void warplab_AGC_Reset(); |
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155 | void warplab_AGC_MasterReset(); |
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156 | void warplab_AGC_Start(); |
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157 | void warplab_AGC_Initialize(int noise_estimate); |
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158 | void warplab_AGC_setNoiseEstimate(int noise_estimate); |
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159 | unsigned int warplab_AGC_GetGains(void); |
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160 | void warplab_AGC_SetTarget(unsigned int target); |
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161 | void warplab_AGC_SetDCO(unsigned int AGCstate); |
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162 | int warpphy_applyTxDCOCalibration(unsigned int radioSelection); |
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163 | // In WARPLab there is no decimation filter in the AGC, there is a downsampling only, so in WARPLab a function equivalent to |
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164 | // ofdm_AGC_FiltSel is not needed |
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165 | |
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166 | void init_net() { |
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167 | int Status; |
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168 | xil_printf("Configuring network\n\r"); |
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169 | |
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170 | mb_hw_addr[0] = 0x00; |
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171 | mb_hw_addr[1] = 0x50; |
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172 | mb_hw_addr[2] = 0xc2; |
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173 | mb_hw_addr[3] = 0x63; |
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174 | mb_hw_addr[4] = 0x36; |
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175 | mb_hw_addr[5] = node+0x63; |
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176 | |
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177 | mb_ip_addr[0] = 10; |
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178 | mb_ip_addr[1] = 0; |
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179 | mb_ip_addr[2] = 0; |
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180 | mb_ip_addr[3] = node+1; |
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181 | |
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182 | //Define the last octet of the IP address used for SYNC packets. The first three will be the mb_ip_addr. |
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183 | sync_IP_octet = 255; |
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184 | |
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185 | myPort = 9000 + node; |
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186 | |
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187 | xilnet_eth_init_hw_addr_tbl(); |
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188 | |
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189 | #ifdef WARP_FPGA_BOARD_V1_2 |
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190 | // Initialize the MAC OPB base address (MAC driver in net/mac.c) |
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191 | xilnet_mac_init(XPAR_ETHERNET_MAC_BASEADDR); |
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192 | // xemac_l.h |
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193 | |
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194 | /*************************Ethernet***************************/ |
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195 | if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet"); |
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196 | //Initialize the EMAC config struct |
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197 | EmacLiteConfigPtr = XEmacLite_LookupConfig(XPAR_EMACLITE_0_DEVICE_ID); |
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198 | if (EmacLiteConfigPtr == NULL){ |
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199 | xil_printf("... ... EMAClite LookupConfig failed!\r\n"); |
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200 | return; |
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201 | } |
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202 | |
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203 | Status = XEmacLite_CfgInitialize(&EmacLiteInstance, EmacLiteConfigPtr, EmacLiteConfigPtr->BaseAddress); |
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204 | if (Status != XST_SUCCESS){ |
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205 | xil_printf("... ... EMAClite CfgInitialize failed!\r\n"); |
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206 | return; |
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207 | } |
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208 | |
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209 | XEmacLite_SetMacAddress(&EmacLiteInstance, mb_hw_addr); |
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210 | |
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211 | XEmacLite_FlushReceive(&EmacLiteInstance); |
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212 | if(DEBUG_LVL > 1) xil_printf("... ... complete!\r\n"); |
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213 | /************************************************************/ |
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214 | #elif defined WARP_FPGA_BOARD_V2_2 |
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215 | if(DEBUG_LVL > 1) xil_printf("... initializing DMA\r\n"); |
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216 | /**************************DMA*******************************/ |
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217 | //Lookup the DMA configuration information |
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218 | DMAConfigPtr = XDmaCentral_LookupConfig(XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID); |
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219 | |
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220 | //Initialize the config struct |
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221 | Status = XDmaCentral_CfgInitialize(&DmaCentralInst, DMAConfigPtr, DMAConfigPtr->BaseAddress); |
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222 | if (Status != XST_SUCCESS){ |
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223 | xil_printf("... ... DMA CfgInitialize failed!\r\n"); |
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224 | return; |
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225 | } |
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226 | |
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227 | //Disable Interrupts |
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228 | XDmaCentral_InterruptEnableSet(&DmaCentralInst, 0); |
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229 | if(DEBUG_LVL > 1) xil_printf("... ... complete!\r\n"); |
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230 | /************************************************************/ |
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231 | |
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232 | /*******************Ethernet**********************************/ |
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233 | if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet\r\n"); |
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234 | MacCfgPtr = XLlTemac_LookupConfig(TEMAC_DEVICE_ID); |
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235 | Status = XLlTemac_CfgInitialize(&TemacInstance, MacCfgPtr, MacCfgPtr->BaseAddress); |
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236 | XLlFifo_Initialize(&FifoInstance, XLlTemac_LlDevBaseAddress(&TemacInstance)); |
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237 | if (Status != XST_SUCCESS) |
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238 | xil_printf("... ... EMAC init error\r\n"); |
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239 | |
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240 | if (!XLlTemac_IsFifo(&TemacInstance)) |
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241 | xil_printf("... ... EMAC hw config incorrect\r\n"); |
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242 | |
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243 | |
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244 | |
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245 | Status = XLlTemac_ClearOptions(&TemacInstance, XTE_LENTYPE_ERR_OPTION | XTE_FLOW_CONTROL_OPTION | XTE_FCS_STRIP_OPTION);// | XTE_MULTICAST_OPTION); |
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246 | Status |= XLlTemac_SetOptions(&TemacInstance, XTE_PROMISC_OPTION | XTE_MULTICAST_OPTION | XTE_BROADCAST_OPTION | XTE_RECEIVER_ENABLE_OPTION | XTE_TRANSMITTER_ENABLE_OPTION); //| XTE_JUMBO_OPTION |
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247 | if (Status != XST_SUCCESS) |
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248 | xil_printf("... ... Error setting EMAC options\r\n, code %d", Status); |
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249 | |
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250 | // Make sure the TEMAC is ready |
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251 | Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET); |
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252 | while ((Status & XTE_RDY_HARD_ACS_RDY_MASK) == 0) |
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253 | { |
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254 | Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET); |
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255 | } |
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256 | |
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257 | XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED); |
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258 | usleep(1 * 10000); |
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259 | |
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260 | XLlTemac_Start(&TemacInstance); |
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261 | if(DEBUG_LVL > 1) xil_printf("... ... complete!\r\n"); |
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262 | /************************************************************/ |
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263 | |
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264 | // Initialize the MAC OPB base address (MAC driver in net/mac.c) |
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265 | xilnet_mac_init((void *)&FifoInstance,(void *)&DmaCentralInst); |
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266 | #endif |
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267 | |
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268 | if(DEBUG_LVL > 1) xil_printf("... complete!\r\n"); |
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269 | // Print IP address |
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270 | if(DEBUG_LVL > 0) xil_printf("IP Address: %d.%d.%d.%d \n\r", mb_ip_addr[0], mb_ip_addr[1],mb_ip_addr[2],mb_ip_addr[3]); |
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271 | } |
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272 | |
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273 | |
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274 | void init_socket() { |
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275 | |
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276 | sock = xilsock_socket(AF_INET, SOCK_DGRAM, 0); // Create UDP socket with domain Internet and UDP connection. |
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277 | if (sock == -1) { |
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278 | if(DEBUG_LVL > 0) xil_printf("Error in creating socket\r\n"); |
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279 | exit(-1); |
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280 | } |
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281 | |
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282 | addr.sin_family = AF_INET; |
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283 | addr.sin_port = myPort; |
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284 | addr.sin_addr.s_addr = INADDR_ANY; // Create the input socket with any incoming address. (0x00000000) |
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285 | |
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286 | XStatus bind = xilsock_bind(sock, (struct sockaddr *)&addr, sizeof(struct sockaddr)); |
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287 | if (bind == -1) { |
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288 | if(DEBUG_LVL > 0) xil_printf("Unable to bind socket\r\n"); |
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289 | exit(-1); |
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290 | } |
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291 | alen = sizeof(struct sockaddr); |
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292 | if(DEBUG_LVL > 0) xil_printf("Listening on UDP port %d.\r\n", myPort); |
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293 | } |
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294 | |
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295 | void shut_socket() { |
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296 | xilsock_close(sock); |
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297 | } |
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298 | |
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299 | int waitForSync() |
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300 | { |
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301 | unsigned int n; |
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302 | |
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303 | XTmrCtr_Start(&TmrCtrInstance, TMRCTR_DEVICE_ID); |
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304 | |
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305 | while(XTmrCtr_GetValue(&TmrCtrInstance, TMRCTR_DEVICE_ID)/XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ < WAITDURATION_SEC){ |
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306 | n = xilnet_eth_recv_frame(receiveBuffer, BUFSIZE); |
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307 | if(n==9999) |
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308 | { |
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309 | return 0; |
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310 | } |
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311 | } |
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312 | |
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313 | XTmrCtr_Stop(&TmrCtrInstance, TMRCTR_DEVICE_ID); |
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314 | |
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315 | xil_printf("NoSync\r\n"); |
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316 | return 1; |
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317 | } |
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318 | |
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319 | int main() { |
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320 | |
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321 | int bytesReceived; |
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322 | int bytesSend; |
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323 | int command; |
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324 | int packetNo; |
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325 | unsigned int rxArg0; |
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326 | char done = 0; |
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327 | unsigned char sevenSeg1 = 0x1; |
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328 | int agctarget = -14; |
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329 | int agcnoiseEst = -95; |
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330 | unsigned int agc_dco_state; |
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331 | |
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332 | |
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333 | #ifdef WARP_FPGA_BOARD_V1_2 |
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334 | unsigned int LEDHEX_Outputs = 0; |
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335 | //Initialize the driver instance for the GPIO core attached to the FPGA board's user I/O (switches, LEDs, etc) |
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336 | XGpio_Initialize(&GPIO_UserIO, XPAR_USER_IO_DEVICE_ID); |
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337 | |
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338 | //We use both channels in the GPIO core- one for inputs, one for outputs |
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339 | //A '1' in a bit position in the third argument marks the bit as an input |
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340 | XGpio_SetDataDirection(&GPIO_UserIO, USERIO_CHAN_INPUTS, USERIO_MASK_INPUTS); |
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341 | XGpio_SetDataDirection(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, 0); |
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342 | |
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343 | //Make sure the LEDs are all off by default |
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344 | XGpio_DiscreteClear(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, USERIO_MASK_OUTPUTS); |
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345 | |
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346 | //Read the 4-bit DIP switch, and use its value as this node's ID |
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347 | node = USERIO_MAP_DIPSW(XGpio_DiscreteRead(&GPIO_UserIO, USERIO_CHAN_INPUTS) & USERIO_MASK_INPUTS); |
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348 | |
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349 | //Display the node's ID + 1 (to match the IP address) on the right hex display |
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350 | LEDHEX_Outputs = ( |
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351 | USERIO_MAP_LEDS(0) | |
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352 | USERIO_MAP_DISPR(sevenSegmentMap(node+1)) | |
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353 | USERIO_MAP_DISPL(sevenSeg1) |
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354 | ); |
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355 | XGpio_DiscreteSet(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, LEDHEX_Outputs); |
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356 | |
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357 | #elif defined WARP_FPGA_BOARD_V2_2 |
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358 | //Set the modes for the three hex displays |
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359 | WarpV4_UserIO_NumberMode_LeftHex(USERIO_BASEADDR); |
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360 | WarpV4_UserIO_NumberMode_MiddleHex(USERIO_BASEADDR); |
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361 | WarpV4_UserIO_RawMode_RightHex(USERIO_BASEADDR); |
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362 | |
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363 | //Read the 4-bit DIP switch and use its value as this node's ID |
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364 | node = WarpV4_UserIO_DipSw(USERIO_BASEADDR); |
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365 | |
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366 | //Write the 2-digit node ID to the left and middle hex displays |
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367 | WarpV4_UserIO_WriteNumber_LeftHex(USERIO_BASEADDR, (node+1)/10, 0); |
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368 | WarpV4_UserIO_WriteNumber_MiddleHex(USERIO_BASEADDR, (node+1)%10, 0); |
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369 | #endif |
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370 | |
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371 | //Initialize the xilnet stack & default sockets |
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372 | init_net(); |
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373 | init_socket(); |
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374 | |
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375 | //Initialize the radio transceivers |
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376 | WarpRadio_v1_Reset((unsigned int*)XPAR_RADIO_CONTROLLER_0_BASEADDR, 2); |
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377 | WarpRadio_v1_SetCenterFreq2GHz(11, radios); |
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378 | WarpRadio_v1_SoftwareTxGainControl(1, radios); |
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379 | //By default, MGC (Manual Gain Control) is enabled. AGC is not enabled by default |
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380 | WarpRadio_v1_SoftwareRxGainControl(1, radios); |
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381 | WarpRadio_v1_RxHpSoftControlEnable(radios); |
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382 | //Set Rx bandwidth to nominal mode |
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383 | Radios_Tx_LPF_Corn_Freq = 1; |
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384 | WarpRadio_v1_RxLpfCornFreqCoarseAdj(Radios_Tx_LPF_Corn_Freq, radios); |
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385 | //Set Tx bandwidth to nominal mode |
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386 | Radios_Rx_LPF_Corn_Freq = 1; |
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387 | WarpRadio_v1_TxLpfCornFreqCoarseAdj(Radios_Rx_LPF_Corn_Freq, radios); |
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388 | |
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389 | //Apply the stored TX DC offset correction values for each radio |
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390 | warpphy_applyTxDCOCalibration(RADIO2_ADDR); |
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391 | warpphy_applyTxDCOCalibration(RADIO3_ADDR); |
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392 | #ifdef WARPLAB_CONFIG_4x4 |
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393 | warpphy_applyTxDCOCalibration(RADIO1_ADDR); |
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394 | warpphy_applyTxDCOCalibration(RADIO4_ADDR); |
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395 | #endif |
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396 | |
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397 | ///Timer Setup/// |
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398 | XTmrCtr_Initialize(&TmrCtrInstance, TMRCTR_DEVICE_ID); |
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399 | XTmrCtr_SetResetValue(&TmrCtrInstance,TMRCTR_DEVICE_ID,0); //Sets it so issuing a "start" command begins at counter=0 |
---|
400 | ///////////////// |
---|
401 | |
---|
402 | |
---|
403 | #ifdef WARPLAB_CONFIG_2x2 |
---|
404 | xil_printf("WARPLabv06_1 2x2 Started - Waiting for connection from MATLAB\r\n"); |
---|
405 | #elif defined WARPLAB_CONFIG_4x4 |
---|
406 | xil_printf("WARPLabv06_1 4x4 Started - Waiting for connection from MATLAB\r\n"); |
---|
407 | #endif |
---|
408 | |
---|
409 | #ifdef WARP_FPGA_BOARD_V2_2 |
---|
410 | XLlFifo_Reset(&FifoInstance); |
---|
411 | #endif |
---|
412 | |
---|
413 | while(done == 0) { |
---|
414 | |
---|
415 | if(DEBUG_LVL > 3) xil_printf("|"); |
---|
416 | |
---|
417 | bytesReceived = xilsock_recvfrom(sock, receiveBuffer, BUFSIZE, (struct sockaddr *)&addr, &alen); // Wait to receive data |
---|
418 | |
---|
419 | if (bytesReceived > 0) { // Check for valid packet |
---|
420 | |
---|
421 | packetNo = receivePtr32[0]; |
---|
422 | command = receivePtr32[1]; |
---|
423 | rxArg0 = receivePtr32[2]; |
---|
424 | |
---|
425 | //Rotate the single active bit |
---|
426 | sevenSeg1 = ( ((sevenSeg1<<1)&0x7E) | ((sevenSeg1>>5)&0x7E) ); |
---|
427 | |
---|
428 | #ifdef WARP_FPGA_BOARD_V1_2 |
---|
429 | //Update the hex displays to show the new values |
---|
430 | LEDHEX_Outputs = ( |
---|
431 | USERIO_MAP_LEDS(0) | |
---|
432 | USERIO_MAP_DISPR(sevenSegmentMap(node+1)) | |
---|
433 | USERIO_MAP_DISPL(sevenSeg1) |
---|
434 | ); |
---|
435 | XGpio_DiscreteSet(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, LEDHEX_Outputs); |
---|
436 | #elif defined WARP_FPGA_BOARD_V2_2 |
---|
437 | WarpV4_UserIO_WriteRaw_RightHex(USERIO_BASEADDR, sevenSeg1<<1); |
---|
438 | #endif |
---|
439 | if(DEBUG_LVL > 2) xil_printf("=============\r\nPacket Received\r\n Length: %d\r\n Packet No.: %d\r\n Command No: %d\r\n", bytesReceived, packetNo, command); |
---|
440 | |
---|
441 | switch(command) { // Decode on incoming command |
---|
442 | |
---|
443 | case INITIALIZE: |
---|
444 | //if(DEBUG_LVL > 1) xil_printf("Initializing Node..."); |
---|
445 | warplab_mimo_WriteReg_TxDelay(0); |
---|
446 | warplab_mimo_WriteReg_StartCapture(0); |
---|
447 | warplab_mimo_WriteReg_TxLength((unsigned int)16383); |
---|
448 | warplab_mimo_WriteReg_TransMode(0); |
---|
449 | warplab_mimo_WriteReg_RADIO2TXBUFF_TXEN(0); |
---|
450 | warplab_mimo_WriteReg_RADIO3TXBUFF_TXEN(0); |
---|
451 | warplab_mimo_WriteReg_RADIO2RXBUFF_RXEN(0); |
---|
452 | warplab_mimo_WriteReg_RADIO3RXBUFF_RXEN(0); |
---|
453 | warplab_mimo_WriteReg_DebugRx2Buffers(0); |
---|
454 | warplab_mimo_WriteReg_DebugRx3Buffers(0); |
---|
455 | warplab_AGC_WriteReg_RADIO1_AGC_EN(0); // No radio on slot 1 |
---|
456 | warplab_AGC_WriteReg_RADIO2_AGC_EN(0); |
---|
457 | warplab_AGC_WriteReg_RADIO3_AGC_EN(0); |
---|
458 | warplab_AGC_WriteReg_RADIO4_AGC_EN(0); // No radio on slot 4 |
---|
459 | warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)50); |
---|
460 | warplab_mimo_WriteReg_MGC_AGC_SEL(0);// Select MGC by default |
---|
461 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
462 | MGC_AGC_Sel_Variable = 0; |
---|
463 | #ifdef WARPLAB_CONFIG_4x4 |
---|
464 | warplab_mimo_WriteReg_RADIO1TXBUFF_TXEN(0); |
---|
465 | warplab_mimo_WriteReg_RADIO4TXBUFF_TXEN(0); |
---|
466 | warplab_mimo_WriteReg_RADIO1RXBUFF_RXEN(0); |
---|
467 | warplab_mimo_WriteReg_RADIO4RXBUFF_RXEN(0); |
---|
468 | warplab_mimo_WriteReg_DebugRx1Buffers(0); |
---|
469 | warplab_mimo_WriteReg_DebugRx4Buffers(0); |
---|
470 | #endif |
---|
471 | |
---|
472 | sendACK(packetNo, command); |
---|
473 | break; |
---|
474 | |
---|
475 | case TX_DELAY: |
---|
476 | |
---|
477 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
478 | if(0 == ReadWrite) |
---|
479 | { |
---|
480 | sendPtr32[0] = packetNo + 1; |
---|
481 | sendPtr32[1] = ACK; |
---|
482 | sendPtr32[2] = command; |
---|
483 | |
---|
484 | sendPtr32[3] = warplab_mimo_ReadReg_TxDelay(WARPLAB_BASEADDR); |
---|
485 | |
---|
486 | if(DEBUG_LVL > 2) xil_printf("Read capt offset of %d\r\n", (unsigned int)receivePtr32[3]); |
---|
487 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
488 | } |
---|
489 | if(1 == ReadWrite) |
---|
490 | { |
---|
491 | //If the user requests a TX_DELAY that's too big, write the maximum instead |
---|
492 | warplab_mimo_WriteReg_TxDelay((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]); |
---|
493 | if(DEBUG_LVL > 2) xil_printf("Set capt offset to %d\r\n", (unsigned int)receivePtr32[3]); |
---|
494 | sendACK(packetNo, command); |
---|
495 | } |
---|
496 | |
---|
497 | break; |
---|
498 | |
---|
499 | case TX_LENGTH: |
---|
500 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
501 | if(0 == ReadWrite) |
---|
502 | { |
---|
503 | sendPtr32[0] = packetNo + 1; |
---|
504 | sendPtr32[1] = ACK; |
---|
505 | sendPtr32[2] = command; |
---|
506 | |
---|
507 | sendPtr32[3] = warplab_mimo_ReadReg_TxLength(WARPLAB_BASEADDR); |
---|
508 | |
---|
509 | if(DEBUG_LVL > 2) xil_printf("Read TxLength of %d\r\n", (unsigned int)receivePtr32[3]); |
---|
510 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
511 | } |
---|
512 | if(1 == ReadWrite) |
---|
513 | { |
---|
514 | //If the user requests a TX_LENGTH that's too big, write the maximum instead |
---|
515 | warplab_mimo_WriteReg_TxLength((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]); |
---|
516 | if(DEBUG_LVL > 2) xil_printf("Set TxLength to %d\r\n", (unsigned int)receivePtr32[3]); |
---|
517 | sendACK(packetNo, command); |
---|
518 | } |
---|
519 | break; |
---|
520 | |
---|
521 | case TX_MODE: |
---|
522 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
523 | if(0 == ReadWrite) |
---|
524 | { |
---|
525 | sendPtr32[0] = packetNo + 1; |
---|
526 | sendPtr32[1] = ACK; |
---|
527 | sendPtr32[2] = command; |
---|
528 | |
---|
529 | sendPtr32[3] = warplab_mimo_ReadReg_TransMode(WARPLAB_BASEADDR); |
---|
530 | |
---|
531 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
532 | } |
---|
533 | if(1 == ReadWrite) |
---|
534 | { |
---|
535 | warplab_mimo_WriteReg_TransMode((unsigned int)receivePtr32[3]); |
---|
536 | sendACK(packetNo, command); |
---|
537 | } |
---|
538 | break; |
---|
539 | |
---|
540 | #ifdef WARPLAB_CONFIG_4x4 |
---|
541 | case RX1BUFFERS_DEBUG: |
---|
542 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
543 | if(0 == ReadWrite) |
---|
544 | { |
---|
545 | sendPtr32[0] = packetNo + 1; |
---|
546 | sendPtr32[1] = ACK; |
---|
547 | sendPtr32[2] = command; |
---|
548 | |
---|
549 | sendPtr32[3] = warplab_mimo_ReadReg_DebugRx1Buffers(WARPLAB_BASEADDR); |
---|
550 | |
---|
551 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
552 | } |
---|
553 | if(1 == ReadWrite) |
---|
554 | { |
---|
555 | warplab_mimo_WriteReg_DebugRx1Buffers((unsigned int)receivePtr32[3]); |
---|
556 | sendACK(packetNo, command); |
---|
557 | } |
---|
558 | break; |
---|
559 | #endif |
---|
560 | |
---|
561 | case RX2BUFFERS_DEBUG: |
---|
562 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
563 | if(0 == ReadWrite) |
---|
564 | { |
---|
565 | sendPtr32[0] = packetNo + 1; |
---|
566 | sendPtr32[1] = ACK; |
---|
567 | sendPtr32[2] = command; |
---|
568 | |
---|
569 | sendPtr32[3] = warplab_mimo_ReadReg_DebugRx2Buffers(WARPLAB_BASEADDR); |
---|
570 | |
---|
571 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
572 | } |
---|
573 | if(1 == ReadWrite) |
---|
574 | { |
---|
575 | warplab_mimo_WriteReg_DebugRx2Buffers((unsigned int)receivePtr32[3]); |
---|
576 | sendACK(packetNo, command); |
---|
577 | } |
---|
578 | break; |
---|
579 | |
---|
580 | case RX3BUFFERS_DEBUG: |
---|
581 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
582 | if(0 == ReadWrite) |
---|
583 | { |
---|
584 | sendPtr32[0] = packetNo + 1; |
---|
585 | sendPtr32[1] = ACK; |
---|
586 | sendPtr32[2] = command; |
---|
587 | |
---|
588 | sendPtr32[3] = warplab_mimo_ReadReg_DebugRx3Buffers(WARPLAB_BASEADDR); |
---|
589 | |
---|
590 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
591 | } |
---|
592 | if(1 == ReadWrite) |
---|
593 | { |
---|
594 | warplab_mimo_WriteReg_DebugRx3Buffers((unsigned int)receivePtr32[3]); |
---|
595 | sendACK(packetNo, command); |
---|
596 | } |
---|
597 | break; |
---|
598 | |
---|
599 | #ifdef WARPLAB_CONFIG_4x4 |
---|
600 | case RX4BUFFERS_DEBUG: |
---|
601 | ReadWrite = (unsigned int)receivePtr32[2]; |
---|
602 | if(0 == ReadWrite) |
---|
603 | { |
---|
604 | sendPtr32[0] = packetNo + 1; |
---|
605 | sendPtr32[1] = ACK; |
---|
606 | sendPtr32[2] = command; |
---|
607 | |
---|
608 | sendPtr32[3] = warplab_mimo_ReadReg_DebugRx4Buffers(WARPLAB_BASEADDR); |
---|
609 | |
---|
610 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
611 | } |
---|
612 | if(1 == ReadWrite) |
---|
613 | { |
---|
614 | warplab_mimo_WriteReg_DebugRx4Buffers((unsigned int)receivePtr32[3]); |
---|
615 | sendACK(packetNo, command); |
---|
616 | } |
---|
617 | break; |
---|
618 | #endif |
---|
619 | |
---|
620 | case MGC_AGC_SEL: |
---|
621 | //ReadWrite = (unsigned int)receivePtr32[2]; |
---|
622 | MGC_AGC_Sel_Variable = (unsigned int)receivePtr32[2]; |
---|
623 | //if(0 == ReadWrite) |
---|
624 | //{ |
---|
625 | // sendPtr32[0] = packetNo + 1; |
---|
626 | // sendPtr32[1] = ACK; |
---|
627 | // sendPtr32[2] = command; |
---|
628 | |
---|
629 | // sendPtr32[3] = warplab_mimo_4x4_ReadReg_MGC_AGC_SEL(XPAR_WARPLAB_MIMO_4X4_OPBW_0_BASEADDR); |
---|
630 | |
---|
631 | // xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
632 | //} |
---|
633 | //if(1 == ReadWrite) |
---|
634 | //{ |
---|
635 | warplab_mimo_WriteReg_MGC_AGC_SEL(MGC_AGC_Sel_Variable); |
---|
636 | |
---|
637 | if(0 == MGC_AGC_Sel_Variable) |
---|
638 | { |
---|
639 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
640 | //Set Radios for Manual Gain Control (MGC) |
---|
641 | WarpRadio_v1_SoftwareRxGainControl(1, radios); |
---|
642 | WarpRadio_v1_RxHpSoftControlEnable(radios); |
---|
643 | } |
---|
644 | if(1 == MGC_AGC_Sel_Variable) |
---|
645 | { |
---|
646 | //Set Radios for Automatic Gain Control (AGC) |
---|
647 | WarpRadio_v1_SoftwareRxGainControl(0, radios); // RxGains will be controlled by the AGC (AGC Change) |
---|
648 | WarpRadio_v1_RxHpSoftControlDisable(radios); // RxHp will be controlled by the AGC (AGC Change) |
---|
649 | WarpRadio_v1_RxHighPassCornerFreq(0, radios); // Will set the corner frequency when RxHp is 0? (AGC Change) |
---|
650 | //xil_printf("agctargetINIT = %d\r\n",agctarget); |
---|
651 | //Set Rx bandwidth; 19MHz |
---|
652 | WarpRadio_v1_RxLpfCornFreqCoarseAdj(1, radios); // (AGC Change) |
---|
653 | |
---|
654 | // Initialize the AGC |
---|
655 | warplab_AGC_Initialize(agcnoiseEst); |
---|
656 | warplab_AGC_setNoiseEstimate(agcnoiseEst); |
---|
657 | // ofdm_AGC_FiltSel(0); No decimation option in WARPLab AGC |
---|
658 | warplab_AGC_SetDCO(0); |
---|
659 | warplab_AGC_SetTarget(agctarget); |
---|
660 | warplab_AGC_Reset(); |
---|
661 | } |
---|
662 | |
---|
663 | sendACK(packetNo, command); |
---|
664 | //} |
---|
665 | break; |
---|
666 | |
---|
667 | case CARRIER_CHANNEL: |
---|
668 | Radios_WirelessChan = ((unsigned int)receivePtr32[2]); |
---|
669 | |
---|
670 | //Channels in [1...37] are valid |
---|
671 | // Values in [1...14] select 2.4GHz channels [1...14] |
---|
672 | // Values in [15...37] select a 5GHz channels [1...23] |
---|
673 | if(Radios_WirelessChan <= (14+23)) |
---|
674 | { |
---|
675 | if(Radios_WirelessChan <= 14) |
---|
676 | WarpRadio_v1_SetCenterFreq2GHz(Radios_WirelessChan, radios); |
---|
677 | else |
---|
678 | WarpRadio_v1_SetCenterFreq5GHz((Radios_WirelessChan-14), radios); |
---|
679 | } |
---|
680 | |
---|
681 | sendACK(packetNo, command); |
---|
682 | break; |
---|
683 | |
---|
684 | case TX_LPF_CORN_FREQ: |
---|
685 | Radios_Tx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]); |
---|
686 | //xil_printf("Radios_Tx_LPF_Corn_Freq = %d\r\n",Radios_Tx_LPF_Corn_Freq); |
---|
687 | WarpRadio_v1_TxLpfCornFreqCoarseAdj(Radios_Tx_LPF_Corn_Freq, radios); |
---|
688 | sendACK(packetNo, command); |
---|
689 | break; |
---|
690 | |
---|
691 | case RX_LPF_CORN_FREQ: |
---|
692 | Radios_Rx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]); |
---|
693 | //xil_printf("Radios_Rx_LPF_Corn_Freq = %d\r\n",Radios_Rx_LPF_Corn_Freq); |
---|
694 | WarpRadio_v1_RxLpfCornFreqCoarseAdj(Radios_Rx_LPF_Corn_Freq, radios); |
---|
695 | sendACK(packetNo, command); |
---|
696 | break; |
---|
697 | |
---|
698 | #ifdef WARPLAB_CONFIG_4x4 |
---|
699 | case RADIO1_TXGAINS: |
---|
700 | //Extract the radio gain config options from the received Ethernet packet |
---|
701 | Radio1_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
702 | Radio1_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F; |
---|
703 | WarpRadio_v1_BaseBandTxGain(Radio1_TxGain_BB, radio1); |
---|
704 | WarpRadio_v1_TxVGAGainControl(Radio1_TxGain_RF, radio1); |
---|
705 | sendACK(packetNo, command); |
---|
706 | break; |
---|
707 | |
---|
708 | case RADIO1_RXGAINS: |
---|
709 | //Extract the radio gain config options from the received Ethernet packet |
---|
710 | Radio1_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
711 | Radio1_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F; |
---|
712 | WarpRadio_v1_RxLNAGainControl(Radio1_RxGain_RF, radio1); |
---|
713 | WarpRadio_v1_RxVGAGainControl(Radio1_RxGain_BB, radio1); |
---|
714 | sendACK(packetNo, command); |
---|
715 | break; |
---|
716 | #endif |
---|
717 | |
---|
718 | case RADIO2_TXGAINS: |
---|
719 | //Extract the radio gain config options from the received Ethernet packet |
---|
720 | Radio2_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
721 | Radio2_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F; |
---|
722 | WarpRadio_v1_BaseBandTxGain(Radio2_TxGain_BB, radio2); |
---|
723 | WarpRadio_v1_TxVGAGainControl(Radio2_TxGain_RF, radio2); |
---|
724 | sendACK(packetNo, command); |
---|
725 | break; |
---|
726 | |
---|
727 | case RADIO2_RXGAINS: |
---|
728 | //Extract the radio gain config options from the received Ethernet packet |
---|
729 | Radio2_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
730 | Radio2_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F; |
---|
731 | WarpRadio_v1_RxLNAGainControl(Radio2_RxGain_RF, radio2); |
---|
732 | WarpRadio_v1_RxVGAGainControl(Radio2_RxGain_BB, radio2); |
---|
733 | sendACK(packetNo, command); |
---|
734 | break; |
---|
735 | |
---|
736 | case RADIO3_TXGAINS: |
---|
737 | //Extract the radio gain config options from the received Ethernet packet |
---|
738 | Radio3_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
739 | Radio3_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F; |
---|
740 | WarpRadio_v1_BaseBandTxGain(Radio3_TxGain_BB, radio3); |
---|
741 | WarpRadio_v1_TxVGAGainControl(Radio3_TxGain_RF, radio3); |
---|
742 | sendACK(packetNo, command); |
---|
743 | break; |
---|
744 | |
---|
745 | case RADIO3_RXGAINS: |
---|
746 | //Extract the radio gain config options from the received Ethernet packet |
---|
747 | Radio3_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
748 | Radio3_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F; |
---|
749 | WarpRadio_v1_RxLNAGainControl(Radio3_RxGain_RF, radio3); |
---|
750 | WarpRadio_v1_RxVGAGainControl(Radio3_RxGain_BB, radio3); |
---|
751 | sendACK(packetNo, command); |
---|
752 | break; |
---|
753 | |
---|
754 | #ifdef WARPLAB_CONFIG_4x4 |
---|
755 | case RADIO4_TXGAINS: |
---|
756 | //Extract the radio gain config options from the received Ethernet packet |
---|
757 | Radio4_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
758 | Radio4_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F; |
---|
759 | WarpRadio_v1_BaseBandTxGain(Radio4_TxGain_BB, radio4); |
---|
760 | WarpRadio_v1_TxVGAGainControl(Radio4_TxGain_RF, radio4); |
---|
761 | sendACK(packetNo, command); |
---|
762 | break; |
---|
763 | |
---|
764 | case RADIO4_RXGAINS: |
---|
765 | //Extract the radio gain config options from the received Ethernet packet |
---|
766 | Radio4_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3; |
---|
767 | Radio4_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F; |
---|
768 | WarpRadio_v1_RxLNAGainControl(Radio4_RxGain_RF, radio4); |
---|
769 | WarpRadio_v1_RxVGAGainControl(Radio4_RxGain_BB, radio4); |
---|
770 | sendACK(packetNo, command); |
---|
771 | break; |
---|
772 | #endif |
---|
773 | |
---|
774 | #ifdef WARPLAB_CONFIG_4x4 |
---|
775 | case RADIO1_TXEN: |
---|
776 | /***************** Setup the radio board ************/ |
---|
777 | |
---|
778 | WarpRadio_v1_BaseBandTxGain(Radio1_TxGain_BB, radio1); |
---|
779 | WarpRadio_v1_TxVGAGainControl(Radio1_TxGain_RF, radio1); |
---|
780 | |
---|
781 | //Enable the transmitter |
---|
782 | WarpRadio_v1_TxEnable(radio1); |
---|
783 | /***************** END Setup the radio board ************/ |
---|
784 | |
---|
785 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Enabled\r\n"); |
---|
786 | sendACK(packetNo, command); |
---|
787 | break; |
---|
788 | #endif |
---|
789 | |
---|
790 | case RADIO2_TXEN: |
---|
791 | /***************** Setup the radio board ************/ |
---|
792 | |
---|
793 | WarpRadio_v1_BaseBandTxGain(Radio2_TxGain_BB, radio2); |
---|
794 | WarpRadio_v1_TxVGAGainControl(Radio2_TxGain_RF, radio2); |
---|
795 | |
---|
796 | //Enable the transmitter |
---|
797 | WarpRadio_v1_TxEnable(radio2); |
---|
798 | /***************** END Setup the radio board ************/ |
---|
799 | |
---|
800 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Enabled\r\n"); |
---|
801 | sendACK(packetNo, command); |
---|
802 | break; |
---|
803 | |
---|
804 | case RADIO3_TXEN: |
---|
805 | /***************** Setup the radio board ************/ |
---|
806 | |
---|
807 | WarpRadio_v1_BaseBandTxGain(Radio3_TxGain_BB, radio3); |
---|
808 | WarpRadio_v1_TxVGAGainControl(Radio3_TxGain_RF, radio3); |
---|
809 | |
---|
810 | //Enable the transmitter |
---|
811 | WarpRadio_v1_TxEnable(radio3); |
---|
812 | /***************** END Setup the radio board ************/ |
---|
813 | |
---|
814 | if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Enabled\r\n"); |
---|
815 | sendACK(packetNo, command); |
---|
816 | break; |
---|
817 | |
---|
818 | #ifdef WARPLAB_CONFIG_4x4 |
---|
819 | case RADIO4_TXEN: |
---|
820 | /***************** Setup the radio board ************/ |
---|
821 | |
---|
822 | WarpRadio_v1_BaseBandTxGain(Radio4_TxGain_BB, radio4); |
---|
823 | WarpRadio_v1_TxVGAGainControl(Radio4_TxGain_RF, radio4); |
---|
824 | |
---|
825 | //Enable the transmitter |
---|
826 | WarpRadio_v1_TxEnable(radio4); |
---|
827 | /***************** END Setup the radio board ************/ |
---|
828 | |
---|
829 | if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Enabled\r\n"); |
---|
830 | sendACK(packetNo, command); |
---|
831 | break; |
---|
832 | #endif |
---|
833 | |
---|
834 | #ifdef WARPLAB_CONFIG_4x4 |
---|
835 | case RADIO1_TXDIS: |
---|
836 | WarpRadio_v1_TxRxDisable(radio1); |
---|
837 | //if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\r\n"); |
---|
838 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\r\n"); |
---|
839 | sendACK(packetNo, command); |
---|
840 | break; |
---|
841 | #endif |
---|
842 | |
---|
843 | case RADIO2_TXDIS: |
---|
844 | WarpRadio_v1_TxRxDisable(radio2); |
---|
845 | //if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\r\n"); |
---|
846 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\r\n"); |
---|
847 | sendACK(packetNo, command); |
---|
848 | break; |
---|
849 | |
---|
850 | case RADIO3_TXDIS: |
---|
851 | WarpRadio_v1_TxRxDisable(radio3); |
---|
852 | //if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Disabled\r\n"); |
---|
853 | if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Disabled\r\n"); |
---|
854 | sendACK(packetNo, command); |
---|
855 | break; |
---|
856 | |
---|
857 | #ifdef WARPLAB_CONFIG_4x4 |
---|
858 | case RADIO4_TXDIS: |
---|
859 | WarpRadio_v1_TxRxDisable(radio4); |
---|
860 | //if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Disabled\r\n"); |
---|
861 | if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Disabled\r\n"); |
---|
862 | sendACK(packetNo, command); |
---|
863 | break; |
---|
864 | #endif |
---|
865 | |
---|
866 | #ifdef WARPLAB_CONFIG_4x4 |
---|
867 | case RADIO1_RXEN: |
---|
868 | /***************** Setup the radio board ************/ |
---|
869 | if(0 == MGC_AGC_Sel_Variable) |
---|
870 | { |
---|
871 | // Disable the Rx HP filter |
---|
872 | // Only needed in Manual Gain Control (MGC) Mode |
---|
873 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
874 | // is controlled by the AGC core |
---|
875 | WarpRadio_v1_RxHpDisable(radio1); |
---|
876 | } |
---|
877 | |
---|
878 | usleep(10); |
---|
879 | |
---|
880 | //Enable the receiver |
---|
881 | WarpRadio_v1_RxEnable(radio1); |
---|
882 | |
---|
883 | if(1 == MGC_AGC_Sel_Variable) |
---|
884 | { |
---|
885 | //Enable this radio's AGC if user has set AGC Mode |
---|
886 | warplab_AGC_WriteReg_RADIO1_AGC_EN(1); |
---|
887 | } |
---|
888 | |
---|
889 | /***************** END Setup the radio board ************/ |
---|
890 | |
---|
891 | //if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\r\n"); |
---|
892 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\r\n"); |
---|
893 | sendACK(packetNo, command); |
---|
894 | break; |
---|
895 | #endif |
---|
896 | |
---|
897 | case RADIO2_RXEN: |
---|
898 | |
---|
899 | /***************** Setup the radio board ************/ |
---|
900 | if(0 == MGC_AGC_Sel_Variable) |
---|
901 | { |
---|
902 | // Disable the Rx HP filter |
---|
903 | // Only needed in Manual Gain Control (MGC) Mode |
---|
904 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
905 | // is controlled by the AGC core |
---|
906 | WarpRadio_v1_RxHpDisable(radio2); |
---|
907 | } |
---|
908 | |
---|
909 | usleep(10); |
---|
910 | |
---|
911 | //Enable the receiver |
---|
912 | WarpRadio_v1_RxEnable(radio2); |
---|
913 | |
---|
914 | if(1 == MGC_AGC_Sel_Variable) |
---|
915 | { |
---|
916 | //Enable this radio's AGC if user has set AGC Mode |
---|
917 | warplab_AGC_WriteReg_RADIO2_AGC_EN(1); |
---|
918 | } |
---|
919 | |
---|
920 | /***************** END Setup the radio board ************/ |
---|
921 | |
---|
922 | //if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\r\n"); |
---|
923 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\r\n"); |
---|
924 | sendACK(packetNo, command); |
---|
925 | break; |
---|
926 | |
---|
927 | case RADIO3_RXEN: |
---|
928 | |
---|
929 | /***************** Setup the radio board ************/ |
---|
930 | if(0 == MGC_AGC_Sel_Variable) |
---|
931 | { |
---|
932 | // Disable the Rx HP filter |
---|
933 | // Only needed in Manual Gain Control (MGC) Mode |
---|
934 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
935 | // is controlled by the AGC core |
---|
936 | WarpRadio_v1_RxHpDisable(radio3); |
---|
937 | } |
---|
938 | |
---|
939 | usleep(10); |
---|
940 | |
---|
941 | //Enable the receiver |
---|
942 | WarpRadio_v1_RxEnable(radio3); |
---|
943 | |
---|
944 | if(1 == MGC_AGC_Sel_Variable) |
---|
945 | { |
---|
946 | //Enable this radio's AGC if user has set AGC Mode |
---|
947 | warplab_AGC_WriteReg_RADIO3_AGC_EN(1); |
---|
948 | } |
---|
949 | |
---|
950 | /***************** END Setup the radio board ************/ |
---|
951 | |
---|
952 | //if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Enabled\r\n"); |
---|
953 | if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Enabled\r\n"); |
---|
954 | sendACK(packetNo, command); |
---|
955 | break; |
---|
956 | |
---|
957 | #ifdef WARPLAB_CONFIG_4x4 |
---|
958 | case RADIO4_RXEN: |
---|
959 | /***************** Setup the radio board ************/ |
---|
960 | if(0 == MGC_AGC_Sel_Variable) |
---|
961 | { |
---|
962 | // Disable the Rx HP filter |
---|
963 | // Only needed in Manual Gain Control (MGC) Mode |
---|
964 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
965 | // is controlled by the AGC core |
---|
966 | WarpRadio_v1_RxHpDisable(radio4); |
---|
967 | } |
---|
968 | |
---|
969 | usleep(10); |
---|
970 | |
---|
971 | //Enable the receiver |
---|
972 | WarpRadio_v1_RxEnable(radio4); |
---|
973 | |
---|
974 | if(1 == MGC_AGC_Sel_Variable) |
---|
975 | { |
---|
976 | //Enable this radio's AGC if user has set AGC Mode |
---|
977 | warplab_AGC_WriteReg_RADIO4_AGC_EN(1); |
---|
978 | } |
---|
979 | |
---|
980 | /***************** END Setup the radio board ************/ |
---|
981 | |
---|
982 | //if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Enabled\r\n"); |
---|
983 | if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Enabled\r\n"); |
---|
984 | sendACK(packetNo, command); |
---|
985 | break; |
---|
986 | #endif |
---|
987 | |
---|
988 | #ifdef WARPLAB_CONFIG_4x4 |
---|
989 | case RADIO1_RXDIS: |
---|
990 | WarpRadio_v1_TxRxDisable(radio1); |
---|
991 | |
---|
992 | if(0 == MGC_AGC_Sel_Variable) |
---|
993 | { |
---|
994 | //Enable the Rx HP filter |
---|
995 | // Only needed in Manual Gain Control (MGC) Mode |
---|
996 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
997 | // is controlled by the AGC core |
---|
998 | WarpRadio_v1_RxHpEnable(radio1); |
---|
999 | } |
---|
1000 | |
---|
1001 | if(1 == MGC_AGC_Sel_Variable) |
---|
1002 | { |
---|
1003 | //Disable this radio's AGC if user has set AGC Mode |
---|
1004 | warplab_AGC_WriteReg_RADIO1_AGC_EN(0); |
---|
1005 | } |
---|
1006 | |
---|
1007 | //if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\r\n"); |
---|
1008 | if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\r\n"); |
---|
1009 | sendACK(packetNo, command); |
---|
1010 | break; |
---|
1011 | #endif |
---|
1012 | |
---|
1013 | case RADIO2_RXDIS: |
---|
1014 | WarpRadio_v1_TxRxDisable(radio2); |
---|
1015 | |
---|
1016 | if(0 == MGC_AGC_Sel_Variable) |
---|
1017 | { |
---|
1018 | //Enable the Rx HP filter |
---|
1019 | // Only needed in Manual Gain Control (MGC) Mode |
---|
1020 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
1021 | // is controlled by the AGC core |
---|
1022 | WarpRadio_v1_RxHpEnable(radio2); |
---|
1023 | } |
---|
1024 | |
---|
1025 | if(1 == MGC_AGC_Sel_Variable) |
---|
1026 | { |
---|
1027 | //Disable this radio's AGC if user has set AGC Mode |
---|
1028 | warplab_AGC_WriteReg_RADIO2_AGC_EN(0); |
---|
1029 | } |
---|
1030 | |
---|
1031 | //if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\r\n"); |
---|
1032 | if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\r\n"); |
---|
1033 | sendACK(packetNo, command); |
---|
1034 | break; |
---|
1035 | |
---|
1036 | case RADIO3_RXDIS: |
---|
1037 | WarpRadio_v1_TxRxDisable(radio3); |
---|
1038 | |
---|
1039 | if(0 == MGC_AGC_Sel_Variable) |
---|
1040 | { |
---|
1041 | //Enable the Rx HP filter |
---|
1042 | // Only needed in Manual Gain Control (MGC) Mode |
---|
1043 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
1044 | // is controlled by the AGC core |
---|
1045 | WarpRadio_v1_RxHpEnable(radio3); |
---|
1046 | } |
---|
1047 | |
---|
1048 | if(1 == MGC_AGC_Sel_Variable) |
---|
1049 | { |
---|
1050 | //Disable this radio's AGC if user has set AGC Mode |
---|
1051 | warplab_AGC_WriteReg_RADIO3_AGC_EN(0); |
---|
1052 | } |
---|
1053 | |
---|
1054 | //if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\r\n"); |
---|
1055 | if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\r\n"); |
---|
1056 | sendACK(packetNo, command); |
---|
1057 | break; |
---|
1058 | |
---|
1059 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1060 | case RADIO4_RXDIS: |
---|
1061 | WarpRadio_v1_TxRxDisable(radio4); |
---|
1062 | |
---|
1063 | if(0 == MGC_AGC_Sel_Variable) |
---|
1064 | { |
---|
1065 | //Enable the Rx HP filter |
---|
1066 | // Only needed in Manual Gain Control (MGC) Mode |
---|
1067 | // In Automatic Gain Control (AGC) Mode, the RxHp |
---|
1068 | // is controlled by the AGC core |
---|
1069 | WarpRadio_v1_RxHpEnable(radio4); |
---|
1070 | } |
---|
1071 | |
---|
1072 | if(1 == MGC_AGC_Sel_Variable) |
---|
1073 | { |
---|
1074 | //Disable this radio's AGC if user has set AGC Mode |
---|
1075 | warplab_AGC_WriteReg_RADIO4_AGC_EN(0); |
---|
1076 | } |
---|
1077 | |
---|
1078 | //if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\r\n"); |
---|
1079 | if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\r\n"); |
---|
1080 | sendACK(packetNo, command); |
---|
1081 | break; |
---|
1082 | #endif |
---|
1083 | |
---|
1084 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1085 | case RADIO1_TXDATA: |
---|
1086 | memcpy |
---|
1087 | ( |
---|
1088 | (unsigned int *)(WARPLAB_TXBUFF_RADIO1 + 4*rxArg0),\ |
---|
1089 | (unsigned int *)(receivePtr32 + 3),\ |
---|
1090 | (bytesReceived-12) |
---|
1091 | ); |
---|
1092 | sendACK(packetNo, command); |
---|
1093 | break; |
---|
1094 | #endif |
---|
1095 | |
---|
1096 | case RADIO2_TXDATA: |
---|
1097 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\r\n",rxArg0); |
---|
1098 | //if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\r\n", *(unsigned int *)(receivePtr32 + 3), *(unsigned int *)(receivePtr32 + 4), *(unsigned int *)(receivePtr32 + 5), *(unsigned int *)(receivePtr32 + 6)); |
---|
1099 | |
---|
1100 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\r\n",rxArg0); |
---|
1101 | |
---|
1102 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\r\n",rxArg0); |
---|
1103 | |
---|
1104 | memcpy |
---|
1105 | ( |
---|
1106 | (unsigned int *)(WARPLAB_TXBUFF_RADIO2 + 4*rxArg0),\ |
---|
1107 | (unsigned int *)(receivePtr32 + 3),\ |
---|
1108 | (bytesReceived-12) |
---|
1109 | ); |
---|
1110 | |
---|
1111 | sendACK(packetNo, command); |
---|
1112 | break; |
---|
1113 | |
---|
1114 | case RADIO3_TXDATA: |
---|
1115 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\r\n",rxArg0); |
---|
1116 | //if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\r\n", *(unsigned int *)(receivePtr32 + 3), *(unsigned int *)(receivePtr32 + 4), *(unsigned int *)(receivePtr32 + 5), *(unsigned int *)(receivePtr32 + 6)); |
---|
1117 | |
---|
1118 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\r\n",rxArg0); |
---|
1119 | |
---|
1120 | //if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\r\n",rxArg0); |
---|
1121 | /* |
---|
1122 | memcpy |
---|
1123 | ( |
---|
1124 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMWO_TxBuff_Radio3_OFFSET + 4*rxArg0),\ |
---|
1125 | (unsigned int *)(receivePtr32 + 3),\ |
---|
1126 | (bytesReceived-12) |
---|
1127 | ); |
---|
1128 | */ |
---|
1129 | memcpy |
---|
1130 | ( |
---|
1131 | (unsigned int *)(WARPLAB_TXBUFF_RADIO3 + 4*rxArg0),\ |
---|
1132 | (unsigned int *)(receivePtr32 + 3),\ |
---|
1133 | (bytesReceived-12) |
---|
1134 | ); |
---|
1135 | sendACK(packetNo, command); |
---|
1136 | break; |
---|
1137 | |
---|
1138 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1139 | case RADIO4_TXDATA: |
---|
1140 | memcpy |
---|
1141 | ( |
---|
1142 | (unsigned int *)(WARPLAB_TXBUFF_RADIO4 + 4*rxArg0),\ |
---|
1143 | (unsigned int *)(receivePtr32 + 3),\ |
---|
1144 | (bytesReceived-12) |
---|
1145 | ); |
---|
1146 | sendACK(packetNo, command); |
---|
1147 | break; |
---|
1148 | #endif |
---|
1149 | |
---|
1150 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1151 | case RADIO1_RXDATA: |
---|
1152 | memcpy |
---|
1153 | ( |
---|
1154 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1155 | (unsigned int *)(WARPLAB_RXBUFF_RADIO1 + 4*rxArg0),\ |
---|
1156 | 1024 |
---|
1157 | ); |
---|
1158 | |
---|
1159 | sendPtr32[0] = packetNo + 1; |
---|
1160 | sendPtr32[1] = ACK; |
---|
1161 | sendPtr32[2] = command; |
---|
1162 | sendPtr32[3] = rxArg0; |
---|
1163 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1164 | break; |
---|
1165 | #endif |
---|
1166 | |
---|
1167 | case RADIO2_RXDATA: |
---|
1168 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
1169 | |
---|
1170 | /* |
---|
1171 | memcpy |
---|
1172 | ( |
---|
1173 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1174 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + 4*rxArg0),\ |
---|
1175 | 1024 |
---|
1176 | ); |
---|
1177 | */ |
---|
1178 | memcpy |
---|
1179 | ( |
---|
1180 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1181 | (unsigned int *)(WARPLAB_RXBUFF_RADIO2 + 4*rxArg0),\ |
---|
1182 | 1024 |
---|
1183 | ); |
---|
1184 | |
---|
1185 | //if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\r\n",rxArg0); |
---|
1186 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\r\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + rxArg0)); |
---|
1187 | |
---|
1188 | sendPtr32[0] = packetNo + 1; |
---|
1189 | sendPtr32[1] = ACK; |
---|
1190 | sendPtr32[2] = command; |
---|
1191 | sendPtr32[3] = rxArg0; |
---|
1192 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1193 | break; |
---|
1194 | |
---|
1195 | case RADIO3_RXDATA: |
---|
1196 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
1197 | |
---|
1198 | /* |
---|
1199 | memcpy |
---|
1200 | ( |
---|
1201 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1202 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET + 4*rxArg0),\ |
---|
1203 | 1024 |
---|
1204 | ); |
---|
1205 | */ |
---|
1206 | memcpy |
---|
1207 | ( |
---|
1208 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1209 | (unsigned int *)(WARPLAB_RXBUFF_RADIO3 + 4*rxArg0),\ |
---|
1210 | 1024 |
---|
1211 | ); |
---|
1212 | |
---|
1213 | |
---|
1214 | //if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\r\n",rxArg0); |
---|
1215 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\r\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET + rxArg0)); |
---|
1216 | |
---|
1217 | sendPtr32[0] = packetNo + 1; |
---|
1218 | sendPtr32[1] = ACK; |
---|
1219 | sendPtr32[2] = command; |
---|
1220 | sendPtr32[3] = rxArg0; |
---|
1221 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1222 | break; |
---|
1223 | |
---|
1224 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1225 | case RADIO4_RXDATA: |
---|
1226 | memcpy |
---|
1227 | ( |
---|
1228 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1229 | (unsigned int *)(WARPLAB_RXBUFF_RADIO4 + 4*rxArg0),\ |
---|
1230 | 1024 |
---|
1231 | ); |
---|
1232 | |
---|
1233 | sendPtr32[0] = packetNo + 1; |
---|
1234 | sendPtr32[1] = ACK; |
---|
1235 | sendPtr32[2] = command; |
---|
1236 | sendPtr32[3] = rxArg0; |
---|
1237 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1238 | break; |
---|
1239 | #endif |
---|
1240 | |
---|
1241 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1242 | case RADIO1_RSSIDATA: |
---|
1243 | memcpy |
---|
1244 | ( |
---|
1245 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1246 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO1 + 4*rxArg0),\ |
---|
1247 | 1024 |
---|
1248 | ); |
---|
1249 | sendPtr32[0] = packetNo + 1; |
---|
1250 | sendPtr32[1] = ACK; |
---|
1251 | sendPtr32[2] = command; |
---|
1252 | sendPtr32[3] = rxArg0; |
---|
1253 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1254 | break; |
---|
1255 | #endif |
---|
1256 | |
---|
1257 | case RADIO2_RSSIDATA: |
---|
1258 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
1259 | |
---|
1260 | /* |
---|
1261 | memcpy |
---|
1262 | ( |
---|
1263 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1264 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0),\ |
---|
1265 | 1024 |
---|
1266 | ); |
---|
1267 | */ |
---|
1268 | memcpy |
---|
1269 | ( |
---|
1270 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1271 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO2 + 4*rxArg0),\ |
---|
1272 | 1024 |
---|
1273 | ); |
---|
1274 | |
---|
1275 | |
---|
1276 | //if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\r\n",rxArg0); |
---|
1277 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\r\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0)); |
---|
1278 | |
---|
1279 | sendPtr32[0] = packetNo + 1; |
---|
1280 | sendPtr32[1] = ACK; |
---|
1281 | sendPtr32[2] = command; |
---|
1282 | sendPtr32[3] = rxArg0; |
---|
1283 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1284 | break; |
---|
1285 | |
---|
1286 | case RADIO3_RSSIDATA: |
---|
1287 | //while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {} |
---|
1288 | |
---|
1289 | /* |
---|
1290 | memcpy |
---|
1291 | ( |
---|
1292 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1293 | (unsigned int *)(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4*rxArg0),\ |
---|
1294 | 1024 |
---|
1295 | ); |
---|
1296 | */ |
---|
1297 | memcpy |
---|
1298 | ( |
---|
1299 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1300 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO3 + 4*rxArg0),\ |
---|
1301 | 1024 |
---|
1302 | ); |
---|
1303 | |
---|
1304 | |
---|
1305 | //if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\r\n",rxArg0); |
---|
1306 | //if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\r\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4*rxArg0)); |
---|
1307 | |
---|
1308 | sendPtr32[0] = packetNo + 1; |
---|
1309 | sendPtr32[1] = ACK; |
---|
1310 | sendPtr32[2] = command; |
---|
1311 | sendPtr32[3] = rxArg0; |
---|
1312 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1313 | break; |
---|
1314 | |
---|
1315 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1316 | case RADIO4_RSSIDATA: |
---|
1317 | memcpy |
---|
1318 | ( |
---|
1319 | (unsigned int *)(sendPtr32 + 4), \ |
---|
1320 | (unsigned int *)(WARPLAB_RSSIBUFF_RADIO4 + 4*rxArg0),\ |
---|
1321 | 1024 |
---|
1322 | ); |
---|
1323 | sendPtr32[0] = packetNo + 1; |
---|
1324 | sendPtr32[1] = ACK; |
---|
1325 | sendPtr32[2] = command; |
---|
1326 | sendPtr32[3] = rxArg0; |
---|
1327 | xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen); |
---|
1328 | break; |
---|
1329 | #endif |
---|
1330 | |
---|
1331 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1332 | case RADIO1TXBUFF_TXEN: |
---|
1333 | warplab_mimo_WriteReg_RADIO1TXBUFF_TXEN(1); |
---|
1334 | |
---|
1335 | sendACK(packetNo, command); |
---|
1336 | break; |
---|
1337 | #endif |
---|
1338 | |
---|
1339 | case RADIO2TXBUFF_TXEN: |
---|
1340 | warplab_mimo_WriteReg_RADIO2TXBUFF_TXEN(1); |
---|
1341 | |
---|
1342 | sendACK(packetNo, command); |
---|
1343 | break; |
---|
1344 | |
---|
1345 | case RADIO3TXBUFF_TXEN: |
---|
1346 | warplab_mimo_WriteReg_RADIO3TXBUFF_TXEN(1); |
---|
1347 | |
---|
1348 | sendACK(packetNo, command); |
---|
1349 | break; |
---|
1350 | |
---|
1351 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1352 | case RADIO4TXBUFF_TXEN: |
---|
1353 | warplab_mimo_WriteReg_RADIO4TXBUFF_TXEN(1); |
---|
1354 | |
---|
1355 | sendACK(packetNo, command); |
---|
1356 | break; |
---|
1357 | #endif |
---|
1358 | |
---|
1359 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1360 | case RADIO1TXBUFF_TXDIS: |
---|
1361 | warplab_mimo_WriteReg_RADIO1TXBUFF_TXEN(0); |
---|
1362 | |
---|
1363 | sendACK(packetNo, command); |
---|
1364 | break; |
---|
1365 | #endif |
---|
1366 | |
---|
1367 | case RADIO2TXBUFF_TXDIS: |
---|
1368 | warplab_mimo_WriteReg_RADIO2TXBUFF_TXEN(0); |
---|
1369 | |
---|
1370 | sendACK(packetNo, command); |
---|
1371 | break; |
---|
1372 | |
---|
1373 | case RADIO3TXBUFF_TXDIS: |
---|
1374 | warplab_mimo_WriteReg_RADIO3TXBUFF_TXEN(0); |
---|
1375 | |
---|
1376 | sendACK(packetNo, command); |
---|
1377 | break; |
---|
1378 | |
---|
1379 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1380 | case RADIO4TXBUFF_TXDIS: |
---|
1381 | warplab_mimo_WriteReg_RADIO4TXBUFF_TXEN(0); |
---|
1382 | |
---|
1383 | sendACK(packetNo, command); |
---|
1384 | break; |
---|
1385 | #endif |
---|
1386 | |
---|
1387 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1388 | case RADIO1RXBUFF_RXEN: |
---|
1389 | warplab_mimo_WriteReg_RADIO1RXBUFF_RXEN(1); |
---|
1390 | |
---|
1391 | sendACK(packetNo, command); |
---|
1392 | break; |
---|
1393 | #endif |
---|
1394 | |
---|
1395 | case RADIO2RXBUFF_RXEN: |
---|
1396 | warplab_mimo_WriteReg_RADIO2RXBUFF_RXEN(1); |
---|
1397 | |
---|
1398 | sendACK(packetNo, command); |
---|
1399 | break; |
---|
1400 | |
---|
1401 | case RADIO3RXBUFF_RXEN: |
---|
1402 | warplab_mimo_WriteReg_RADIO3RXBUFF_RXEN(1); |
---|
1403 | |
---|
1404 | sendACK(packetNo, command); |
---|
1405 | break; |
---|
1406 | |
---|
1407 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1408 | case RADIO4RXBUFF_RXEN: |
---|
1409 | warplab_mimo_WriteReg_RADIO4RXBUFF_RXEN(1); |
---|
1410 | |
---|
1411 | sendACK(packetNo, command); |
---|
1412 | break; |
---|
1413 | #endif |
---|
1414 | |
---|
1415 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1416 | case RADIO1RXBUFF_RXDIS: |
---|
1417 | warplab_mimo_WriteReg_RADIO1RXBUFF_RXEN(0); |
---|
1418 | |
---|
1419 | sendACK(packetNo, command); |
---|
1420 | break; |
---|
1421 | #endif |
---|
1422 | |
---|
1423 | case RADIO2RXBUFF_RXDIS: |
---|
1424 | warplab_mimo_WriteReg_RADIO2RXBUFF_RXEN(0); |
---|
1425 | |
---|
1426 | sendACK(packetNo, command); |
---|
1427 | break; |
---|
1428 | |
---|
1429 | case RADIO3RXBUFF_RXDIS: |
---|
1430 | warplab_mimo_WriteReg_RADIO3RXBUFF_RXEN(0); |
---|
1431 | |
---|
1432 | sendACK(packetNo, command); |
---|
1433 | break; |
---|
1434 | |
---|
1435 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1436 | case RADIO4RXBUFF_RXDIS: |
---|
1437 | warplab_mimo_WriteReg_RADIO4RXBUFF_RXEN(0); |
---|
1438 | |
---|
1439 | sendACK(packetNo, command); |
---|
1440 | break; |
---|
1441 | #endif |
---|
1442 | |
---|
1443 | case RX_DONECHECK: |
---|
1444 | |
---|
1445 | sendPtr32[0] = packetNo + 1; |
---|
1446 | sendPtr32[1] = ACK; |
---|
1447 | sendPtr32[2] = command; |
---|
1448 | |
---|
1449 | if(warplab_mimo_ReadReg_CaptureDone(WARPLAB_BASEADDR) == 0) |
---|
1450 | sendPtr32[3] = 0; |
---|
1451 | else |
---|
1452 | sendPtr32[3] = 1; |
---|
1453 | |
---|
1454 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1455 | break; |
---|
1456 | |
---|
1457 | case RX_DONEREADING: |
---|
1458 | //warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 1); |
---|
1459 | //warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 0); |
---|
1460 | |
---|
1461 | sendACK(packetNo, command); |
---|
1462 | break; |
---|
1463 | |
---|
1464 | case RX_START: |
---|
1465 | //if(DEBUG_LVL > 1) xil_printf("Starting Rx\r\n"); |
---|
1466 | //if(DEBUG_LVL > 1) xil_printf("Starting Rx\r\n"); |
---|
1467 | sendACK(packetNo, command); |
---|
1468 | |
---|
1469 | if(waitForSync() == 0) |
---|
1470 | { |
---|
1471 | warplab_mimo_WriteReg_StartCapture(1); |
---|
1472 | warplab_AGC_Start(); |
---|
1473 | warplab_mimo_WriteReg_StartCapture(0); |
---|
1474 | |
---|
1475 | //if(DEBUG_LVL > 1) xil_printf("Capture started\r\n"); |
---|
1476 | } |
---|
1477 | else |
---|
1478 | if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Rx Capture\r\n"); |
---|
1479 | break; |
---|
1480 | |
---|
1481 | case TX_START: |
---|
1482 | //if(DEBUG_LVL > 1) xil_printf("Starting Tx\r\n"); |
---|
1483 | if(DEBUG_LVL > 1) xil_printf("Starting Tx\r\n"); |
---|
1484 | sendACK(packetNo, command); |
---|
1485 | |
---|
1486 | if(waitForSync() == 0) |
---|
1487 | { |
---|
1488 | warplab_mimo_WriteReg_StartTx(1); |
---|
1489 | warplab_mimo_WriteReg_StartTx(0); |
---|
1490 | //if(DEBUG_LVL > 1) xil_printf("Transmit started\r\n"); |
---|
1491 | } |
---|
1492 | else |
---|
1493 | if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Tx\r\n"); |
---|
1494 | break; |
---|
1495 | |
---|
1496 | case TX_STOP: |
---|
1497 | sendACK(packetNo, command); |
---|
1498 | |
---|
1499 | warplab_mimo_WriteReg_StopTx(1); |
---|
1500 | warplab_mimo_WriteReg_StopTx(0); |
---|
1501 | |
---|
1502 | break; |
---|
1503 | |
---|
1504 | case TXRX_START: |
---|
1505 | if(DEBUG_LVL > 1) xil_printf("Starting TxRX\r\n"); |
---|
1506 | sendACK(packetNo, command); |
---|
1507 | |
---|
1508 | if(waitForSync() == 0) |
---|
1509 | { |
---|
1510 | warplab_mimo_WriteReg_StartTxRx(1); |
---|
1511 | warplab_mimo_WriteReg_StartTxRx(0); |
---|
1512 | } |
---|
1513 | else |
---|
1514 | if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling TxRx\r\n"); |
---|
1515 | break; |
---|
1516 | |
---|
1517 | case READ_AGC_DONE_ADDR: |
---|
1518 | sendPtr32[0] = packetNo + 1; |
---|
1519 | sendPtr32[1] = ACK; |
---|
1520 | sendPtr32[2] = command; |
---|
1521 | |
---|
1522 | sendPtr32[3] = warplab_mimo_ReadReg_AGCDoneAddr(WARPLAB_BASEADDR); |
---|
1523 | |
---|
1524 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1525 | break; |
---|
1526 | |
---|
1527 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1528 | case READ_RADIO1AGCDONERSSI: |
---|
1529 | sendPtr32[0] = packetNo + 1; |
---|
1530 | sendPtr32[1] = ACK; |
---|
1531 | sendPtr32[2] = command; |
---|
1532 | |
---|
1533 | sendPtr32[3] = warplab_mimo_ReadReg_Radio1AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
1534 | |
---|
1535 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1536 | break; |
---|
1537 | #endif |
---|
1538 | |
---|
1539 | case READ_RADIO2AGCDONERSSI: |
---|
1540 | sendPtr32[0] = packetNo + 1; |
---|
1541 | sendPtr32[1] = ACK; |
---|
1542 | sendPtr32[2] = command; |
---|
1543 | |
---|
1544 | sendPtr32[3] = warplab_mimo_ReadReg_Radio2AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
1545 | |
---|
1546 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1547 | break; |
---|
1548 | |
---|
1549 | case READ_RADIO3AGCDONERSSI: |
---|
1550 | sendPtr32[0] = packetNo + 1; |
---|
1551 | sendPtr32[1] = ACK; |
---|
1552 | sendPtr32[2] = command; |
---|
1553 | |
---|
1554 | sendPtr32[3] = warplab_mimo_ReadReg_Radio3AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
1555 | |
---|
1556 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1557 | break; |
---|
1558 | |
---|
1559 | #ifdef WARPLAB_CONFIG_4x4 |
---|
1560 | case READ_RADIO4AGCDONERSSI: |
---|
1561 | sendPtr32[0] = packetNo + 1; |
---|
1562 | sendPtr32[1] = ACK; |
---|
1563 | sendPtr32[2] = command; |
---|
1564 | |
---|
1565 | sendPtr32[3] = warplab_mimo_ReadReg_Radio4AGCDoneRSSI(WARPLAB_BASEADDR); |
---|
1566 | |
---|
1567 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1568 | break; |
---|
1569 | #endif |
---|
1570 | |
---|
1571 | case AGC_RESET: |
---|
1572 | warplab_AGC_Reset(); |
---|
1573 | sendACK(packetNo, command); |
---|
1574 | break; |
---|
1575 | |
---|
1576 | case READ_AGC_GAINS: |
---|
1577 | sendPtr32[0] = packetNo + 1; |
---|
1578 | sendPtr32[1] = ACK; |
---|
1579 | sendPtr32[2] = command; |
---|
1580 | |
---|
1581 | sendPtr32[3] = warplab_AGC_GetGains(); |
---|
1582 | |
---|
1583 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1584 | break; |
---|
1585 | |
---|
1586 | case SET_AGC_TARGET_dBm: |
---|
1587 | agctarget = (int)receivePtr32[2]; |
---|
1588 | warplab_AGC_SetTarget(agctarget); |
---|
1589 | xil_printf("agctarget = %d\r\n",agctarget); |
---|
1590 | sendACK(packetNo, command); |
---|
1591 | break; |
---|
1592 | |
---|
1593 | case SET_AGC_DCO_EN_DIS: |
---|
1594 | agc_dco_state = (unsigned int)receivePtr32[2]; |
---|
1595 | warplab_AGC_SetDCO(agc_dco_state); |
---|
1596 | warplab_mimo_WriteReg_DCO_EN_SEL(agc_dco_state); |
---|
1597 | xil_printf("agc_dco_state = %d\r\n",agc_dco_state); |
---|
1598 | sendACK(packetNo, command); |
---|
1599 | break; |
---|
1600 | |
---|
1601 | case SET_AGC_NOISEEST_dBm: |
---|
1602 | agcnoiseEst = (int)receivePtr32[2]; |
---|
1603 | warplab_AGC_setNoiseEstimate(agcnoiseEst); |
---|
1604 | xil_printf("agctarget = %d\r\n",agctarget); |
---|
1605 | sendACK(packetNo, command); |
---|
1606 | break; |
---|
1607 | |
---|
1608 | case SET_AGC_THRESHOLDS: |
---|
1609 | warplab_AGC_WriteReg_Thresholds((unsigned int)receivePtr32[2]); |
---|
1610 | sendACK(packetNo, command); |
---|
1611 | break; |
---|
1612 | |
---|
1613 | case SET_AGC_TRIG_DELAY: |
---|
1614 | warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)receivePtr32[2]); |
---|
1615 | sendACK(packetNo, command); |
---|
1616 | break; |
---|
1617 | |
---|
1618 | case READ_AGC_THRESHOLDS: |
---|
1619 | sendPtr32[0] = packetNo + 1; |
---|
1620 | sendPtr32[1] = ACK; |
---|
1621 | sendPtr32[2] = command; |
---|
1622 | |
---|
1623 | sendPtr32[3] = warplab_AGC_ReadReg_Thresholds(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1624 | |
---|
1625 | xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen); |
---|
1626 | break; |
---|
1627 | |
---|
1628 | case CLOSE: |
---|
1629 | if(DEBUG_LVL > 1) xil_printf("Closing sockets.\r\n"); |
---|
1630 | sendACK(packetNo, command); |
---|
1631 | done = 1; |
---|
1632 | |
---|
1633 | break; |
---|
1634 | |
---|
1635 | case TX_TEST: |
---|
1636 | if(DEBUG_LVL > 1) xil_printf("Starting Tx Test\r\n"); |
---|
1637 | sendACK(packetNo, command); |
---|
1638 | |
---|
1639 | break; |
---|
1640 | |
---|
1641 | default: |
---|
1642 | if(DEBUG_LVL > 1) xil_printf("Received command (%d) is not recognized. Please retry transmission.\r\n", command); |
---|
1643 | |
---|
1644 | sendPtr32[0] = packetNo + 1; |
---|
1645 | sendPtr32[1] = NOACK; |
---|
1646 | bytesSend = 8; |
---|
1647 | xilsock_sendto(sock, sendBuffer, bytesSend, (struct sockaddr *)&addr, alen); |
---|
1648 | } |
---|
1649 | } |
---|
1650 | } |
---|
1651 | |
---|
1652 | shut_socket(); |
---|
1653 | |
---|
1654 | return 0; |
---|
1655 | } |
---|
1656 | |
---|
1657 | void sendACK(unsigned int packetNo, unsigned int commandToACK) |
---|
1658 | { |
---|
1659 | sendPtr32[0] = packetNo + 1; |
---|
1660 | sendPtr32[1] = ACK; |
---|
1661 | sendPtr32[2] = commandToACK; |
---|
1662 | xilsock_sendto(sock, sendBuffer, 12, (struct sockaddr *)&addr, alen); |
---|
1663 | return; |
---|
1664 | } |
---|
1665 | |
---|
1666 | unsigned char sevenSegmentMap(unsigned char x) |
---|
1667 | { |
---|
1668 | switch(x) |
---|
1669 | { |
---|
1670 | case(0x0) : return 0x007E; |
---|
1671 | case(0x1) : return 0x0030; |
---|
1672 | case(0x2) : return 0x006D; |
---|
1673 | case(0x3) : return 0x0079; |
---|
1674 | case(0x4) : return 0x0033; |
---|
1675 | case(0x5) : return 0x005B; |
---|
1676 | case(0x6) : return 0x005F; |
---|
1677 | case(0x7) : return 0x0070; |
---|
1678 | case(0x8) : return 0x007F; |
---|
1679 | case(0x9) : return 0x007B; |
---|
1680 | |
---|
1681 | case(0xA) : return 0x0077; |
---|
1682 | case(0xB) : return 0x007F; |
---|
1683 | case(0xC) : return 0x004E; |
---|
1684 | case(0xD) : return 0x007E; |
---|
1685 | case(0xE) : return 0x004F; |
---|
1686 | case(0xF) : return 0x0047; |
---|
1687 | default : return 0x0000; |
---|
1688 | } |
---|
1689 | } |
---|
1690 | |
---|
1691 | #define XPAR_EEPROM_CONTROLLER_BASEADDR XPAR_EEPROM_CONTROLLER_MEM0_BASEADDR |
---|
1692 | //New TxDCO calibration code |
---|
1693 | int warpphy_applyTxDCOCalibration(unsigned int radioSelection) |
---|
1694 | { |
---|
1695 | int eepromStatus = 0; |
---|
1696 | short calReadback = 0; |
---|
1697 | signed short best_I, best_Q; |
---|
1698 | unsigned char radioNum; |
---|
1699 | Xuint8 memory[8], version, revision, valid, i; |
---|
1700 | Xuint16 serial; |
---|
1701 | |
---|
1702 | //Radio selection will be 0x11111111, 0x22222222, 0x44444444 or 0x88888888 |
---|
1703 | // corresponding to radios in slots 1, 2, 3 or 4 |
---|
1704 | // We need the slot number to initialize the EEPROM |
---|
1705 | radioNum = (radioSelection & 0xF) == 1 ? 1 : ( (radioSelection & 0xF) == 2 ? 2 : ( (radioSelection & 0xF) == 4 ? 3 : 4 ) ); |
---|
1706 | if(DEBUG_LVL>2) xil_printf("Applying TxDCO correction for radio %d\r\n", radioNum); |
---|
1707 | |
---|
1708 | //Mimic the radio test code, in hopes of a more stable EEPROM read... |
---|
1709 | //Choose the EEPROM on the selected radio board; second arg is [0,1,2,3,4] for [FPGA, radio1, radio2, radio3, radio4] |
---|
1710 | eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR, 0); |
---|
1711 | if(eepromStatus != 0) |
---|
1712 | { |
---|
1713 | if(DEBUG_LVL>2) xil_printf("EEPROM Select Failed!\r\n"); |
---|
1714 | return -1; |
---|
1715 | } |
---|
1716 | |
---|
1717 | //Initialize the EEPROM controller |
---|
1718 | eepromStatus = WarpEEPROM_Initialize((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR); |
---|
1719 | if(eepromStatus != 0) |
---|
1720 | { |
---|
1721 | if(DEBUG_LVL>2) xil_printf("EEPROM Init Returned %x\r\n", eepromStatus); |
---|
1722 | if(DEBUG_LVL>2) xil_printf("EEPROM Init Failed!\r\n"); |
---|
1723 | return -1; |
---|
1724 | } |
---|
1725 | |
---|
1726 | //Select the EEPROM on the current radio board |
---|
1727 | eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, radioNum); |
---|
1728 | |
---|
1729 | if(eepromStatus != 0) |
---|
1730 | { |
---|
1731 | if(DEBUG_LVL>2) xil_printf("TxDCO: EEPROM error\r\n"); |
---|
1732 | return -1; |
---|
1733 | } |
---|
1734 | |
---|
1735 | //Read the first page from the EERPOM |
---|
1736 | WarpEEPROM_ReadMem((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 0, 0, memory); |
---|
1737 | version = (memory[0] & 0xE0) >> 5; |
---|
1738 | revision = (memory[1] & 0xE0) >> 5; |
---|
1739 | valid = memory[1] & 0x1F; |
---|
1740 | |
---|
1741 | if(DEBUG_LVL>2) xil_printf("\r\n\r\nEEPROM Values for Radio Board in Slot %d\r\n", radioNum); |
---|
1742 | |
---|
1743 | if(DEBUG_LVL>2) xil_printf(" WARP Radio Board Version %d.%d\r\n", version, revision); |
---|
1744 | |
---|
1745 | serial = WarpEEPROM_ReadWARPSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR); |
---|
1746 | |
---|
1747 | if(DEBUG_LVL>2) xil_printf(" Serial Number (WARP): WR-a-%05d\r\n", serial); |
---|
1748 | |
---|
1749 | WarpEEPROM_ReadDSSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, memory); |
---|
1750 | if(DEBUG_LVL>2) print(" EEPROM Hard-wired Serial Number: "); |
---|
1751 | if(DEBUG_LVL>2){ |
---|
1752 | for(i=1;i<7;i++) |
---|
1753 | xil_printf(" %x",memory[7-i]); |
---|
1754 | xil_printf("\r\n\r\n"); |
---|
1755 | } |
---|
1756 | //Read the Tx DCO values |
---|
1757 | calReadback = WarpEEPROM_ReadRadioCal((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 2, 1); |
---|
1758 | |
---|
1759 | //Scale the stored values |
---|
1760 | best_I = (signed short)(((signed char)(calReadback & 0xFF))<<1); |
---|
1761 | best_Q = (signed short)(((signed char)((calReadback>>8) & 0xFF))<<1); |
---|
1762 | |
---|
1763 | if(DEBUG_LVL>2) xil_printf("TxDCO: Applied values to radio %d - I: %d\tQ: %d\r\n", radioNum, best_I, best_Q); |
---|
1764 | |
---|
1765 | //Finally, write the Tx DCO values to the DAC |
---|
1766 | WarpRadio_v1_DACOffsetAdj(ICHAN, best_I, radioSelection); |
---|
1767 | WarpRadio_v1_DACOffsetAdj(QCHAN, best_Q, radioSelection); |
---|
1768 | |
---|
1769 | return 0; |
---|
1770 | } |
---|
1771 | |
---|
1772 | |
---|
1773 | void warplab_AGC_Reset() |
---|
1774 | { |
---|
1775 | // Cycle the agc's software reset port |
---|
1776 | |
---|
1777 | warplab_AGC_WriteReg_SRESET_IN(1); |
---|
1778 | usleep(10); |
---|
1779 | warplab_AGC_WriteReg_SRESET_IN(0); |
---|
1780 | usleep(100); |
---|
1781 | |
---|
1782 | return; |
---|
1783 | } |
---|
1784 | |
---|
1785 | void warplab_AGC_MasterReset() |
---|
1786 | { |
---|
1787 | // Cycle the master reset register in the AGC and enable it |
---|
1788 | |
---|
1789 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
1790 | usleep(10); |
---|
1791 | warplab_AGC_WriteReg_MRESET_IN(0); |
---|
1792 | usleep(10); |
---|
1793 | warplab_AGC_WriteReg_MRESET_IN(1); |
---|
1794 | usleep(10); |
---|
1795 | warplab_AGC_WriteReg_MRESET_IN(0); |
---|
1796 | usleep(10); |
---|
1797 | warplab_AGC_WriteReg_AGC_EN(1); |
---|
1798 | |
---|
1799 | return; |
---|
1800 | } |
---|
1801 | |
---|
1802 | void warplab_AGC_Start() |
---|
1803 | { |
---|
1804 | // Cycle the agc's packet in port |
---|
1805 | warplab_AGC_WriteReg_PACKET_IN(1); |
---|
1806 | usleep(10); |
---|
1807 | warplab_AGC_WriteReg_PACKET_IN(0); |
---|
1808 | usleep(100); |
---|
1809 | |
---|
1810 | return; |
---|
1811 | } |
---|
1812 | |
---|
1813 | void warplab_AGC_Initialize(int noise_estimate) |
---|
1814 | { |
---|
1815 | int g_bbset = 0; |
---|
1816 | |
---|
1817 | // First set all standard parameters |
---|
1818 | |
---|
1819 | // Turn off both resets and the master enable |
---|
1820 | warplab_AGC_WriteReg_AGC_EN(0); |
---|
1821 | warplab_AGC_WriteReg_SRESET_IN(0); |
---|
1822 | warplab_AGC_WriteReg_MRESET_IN(0); |
---|
1823 | |
---|
1824 | // An adjustment parameter |
---|
1825 | warplab_AGC_WriteReg_ADJ(8); |
---|
1826 | |
---|
1827 | // Timing for the DC-offset correction |
---|
1828 | warplab_AGC_WriteReg_DCO_Timing(0x12001000); |
---|
1829 | |
---|
1830 | // Initial baseband gain setting |
---|
1831 | warplab_AGC_WriteReg_GBB_init(52); |
---|
1832 | |
---|
1833 | // RF gain AGCstate thresholds |
---|
1834 | warplab_AGC_WriteReg_Thresholds(0xD5CBA6); |
---|
1835 | |
---|
1836 | // Overall AGC timing |
---|
1837 | warplab_AGC_WriteReg_Timing(0x9A962A28);//0x826E3C0A; |
---|
1838 | |
---|
1839 | // vIQ and RSSI average lengths |
---|
1840 | warplab_AGC_WriteReg_AVG_LEN(0x10F); //103 |
---|
1841 | |
---|
1842 | // Disable DCO, disable DCO subtraction |
---|
1843 | warplab_AGC_WriteReg_Bits(0x0); |
---|
1844 | |
---|
1845 | // Compute and set the initial g_BB gain value from the noise estimate |
---|
1846 | // The initial g_bb sets noise to -19 db, assuming 32 db RF gain |
---|
1847 | |
---|
1848 | g_bbset = -19 - 32 - noise_estimate; |
---|
1849 | warplab_AGC_WriteReg_GBB_init(g_bbset); |
---|
1850 | |
---|
1851 | // Perform a master reset |
---|
1852 | warplab_AGC_MasterReset(); |
---|
1853 | |
---|
1854 | // Agc is now reset and enabled, ready to go! |
---|
1855 | return; |
---|
1856 | } |
---|
1857 | |
---|
1858 | void warplab_AGC_setNoiseEstimate(int noise_estimate) |
---|
1859 | { |
---|
1860 | int g_bbset; |
---|
1861 | |
---|
1862 | g_bbset = -19 - 32 - noise_estimate; |
---|
1863 | |
---|
1864 | warplab_AGC_WriteReg_GBB_init(g_bbset); |
---|
1865 | |
---|
1866 | return; |
---|
1867 | } |
---|
1868 | |
---|
1869 | unsigned int warplab_AGC_GetGains(void) |
---|
1870 | { |
---|
1871 | unsigned int gBB_A, gRF_A, gBB_B, gRF_B, gBB_C, gRF_C, gBB_D, gRF_D, gains; |
---|
1872 | |
---|
1873 | // Get the gains from the registers |
---|
1874 | gBB_A = warplab_AGC_ReadReg_GBB_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1875 | gRF_A = warplab_AGC_ReadReg_GRF_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1876 | |
---|
1877 | gBB_B = warplab_AGC_ReadReg_GBB_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1878 | gRF_B = warplab_AGC_ReadReg_GRF_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1879 | |
---|
1880 | gBB_C = warplab_AGC_ReadReg_GBB_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1881 | gRF_C = warplab_AGC_ReadReg_GRF_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1882 | |
---|
1883 | gBB_D = warplab_AGC_ReadReg_GBB_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1884 | gRF_D = warplab_AGC_ReadReg_GRF_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1885 | |
---|
1886 | // First concatenate the two radios together, into the gRF register |
---|
1887 | // 2 lowest bits are RF, 5 higher bits are BB, last bit is unused |
---|
1888 | // Multiply by 2^2, shift gBB right by 2 bits |
---|
1889 | |
---|
1890 | gRF_A = gRF_A + (gBB_A * 4); |
---|
1891 | gRF_B = gRF_B + (gBB_B * 4); |
---|
1892 | gRF_C = gRF_C + (gBB_C * 4); |
---|
1893 | gRF_D = gRF_D + (gBB_D * 4); |
---|
1894 | |
---|
1895 | // Multiply by 2^8 shift gRF right by 8 bits |
---|
1896 | |
---|
1897 | gains = gRF_A + (gRF_B * 256) + (gRF_C * 65536) + (gRF_D * 16777216); |
---|
1898 | |
---|
1899 | return gains; |
---|
1900 | } |
---|
1901 | |
---|
1902 | void warplab_AGC_SetTarget(unsigned int target) |
---|
1903 | { |
---|
1904 | warplab_AGC_WriteReg_T_dB(target); |
---|
1905 | return; |
---|
1906 | } |
---|
1907 | |
---|
1908 | void warplab_AGC_SetDCO(unsigned int AGCstate) |
---|
1909 | { |
---|
1910 | // Enables DCO and DCO subtraction (correction scheme and butterworth hipass are active) |
---|
1911 | |
---|
1912 | unsigned int bits; |
---|
1913 | |
---|
1914 | bits = warplab_AGC_ReadReg_Bits(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR); |
---|
1915 | |
---|
1916 | if(AGCstate) |
---|
1917 | bits = bits | 0x6; |
---|
1918 | else |
---|
1919 | bits = bits & 0x1; |
---|
1920 | |
---|
1921 | warplab_AGC_WriteReg_Bits(bits); |
---|
1922 | |
---|
1923 | return; |
---|
1924 | } |
---|