1 | ############################################################################ |
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2 | ## This system.ucf file is generated by Base System Builder based on the |
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3 | ## settings in the selected Xilinx Board Definition file. Please add other |
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4 | ## user constraints to this file based on customer design specifications. |
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5 | ############################################################################ |
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6 | |
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7 | Net sys_clk_pin LOC=AT20; |
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8 | Net sys_clk_pin IOSTANDARD = LVTTL; |
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9 | Net sys_rst_pin LOC=AM16; |
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10 | Net sys_rst_pin IOSTANDARD = LVTTL; |
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11 | ## System level constraints |
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12 | Net sys_clk_pin TNM_NET = sys_clk_pin; |
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13 | TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 ps; |
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14 | Net sys_rst_pin TIG; |
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15 | NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; |
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16 | NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; |
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17 | NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; |
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18 | TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; |
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19 | |
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20 | ## IO Devices constraints |
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21 | |
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22 | #Debug header LOC constraints (manually entered) |
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23 | NET "debug<0>" LOC = "K28" | IOSTANDARD = LVTTL; #pin 0 |
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24 | NET "debug<1>" LOC = "G30" | IOSTANDARD = LVTTL; #pin 1 |
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25 | NET "debug<2>" LOC = "H29" | IOSTANDARD = LVTTL; #pin 2 |
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26 | NET "debug<3>" LOC = "H30" | IOSTANDARD = LVTTL; #pin 3 |
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27 | NET "debug<4>" LOC = "J28" | IOSTANDARD = LVTTL; #pin 4 |
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28 | NET "debug<5>" LOC = "F30" | IOSTANDARD = LVTTL; #pin 5 |
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29 | NET "debug<6>" LOC = "E29" | IOSTANDARD = LVTTL; #pin 6 |
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30 | NET "debug<7>" LOC = "D30" | IOSTANDARD = LVTTL; #pin 7 |
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31 | NET "debug<8>" LOC = "K30" | IOSTANDARD = LVTTL; #pin 8 |
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32 | NET "debug<9>" LOC = "J30" | IOSTANDARD = LVTTL; #pin 9 |
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33 | NET "debug<10>" LOC = "K29" | IOSTANDARD = LVTTL; #pin 10 |
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34 | NET "debug<11>" LOC = "J29" | IOSTANDARD = LVTTL; #pin 11 |
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35 | NET "debug<12>" LOC = "G29" | IOSTANDARD = LVTTL; #pin 12 |
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36 | NET "debug<13>" LOC = "H28" | IOSTANDARD = LVTTL; #pin 13 |
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37 | NET "debug<14>" LOC = "F29" | IOSTANDARD = LVTTL; #pin 14 |
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38 | NET "debug<15>" LOC = "E30" | IOSTANDARD = LVTTL; #pin 15 |
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39 | |
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40 | #### Module USER_IO constraints |
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41 | |
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42 | Net fpga_0_USER_IO_GPIO_in_pin<0> LOC=Y27; |
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43 | Net fpga_0_USER_IO_GPIO_in_pin<0> IOSTANDARD = LVTTL; |
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44 | Net fpga_0_USER_IO_GPIO_in_pin<1> LOC=Y28; |
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45 | Net fpga_0_USER_IO_GPIO_in_pin<1> IOSTANDARD = LVTTL; |
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46 | Net fpga_0_USER_IO_GPIO_in_pin<2> LOC=AA27; |
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47 | Net fpga_0_USER_IO_GPIO_in_pin<2> IOSTANDARD = LVTTL; |
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48 | Net fpga_0_USER_IO_GPIO_in_pin<3> LOC=Y29; |
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49 | Net fpga_0_USER_IO_GPIO_in_pin<3> IOSTANDARD = LVTTL; |
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50 | Net fpga_0_USER_IO_GPIO_in_pin<4> LOC=AJ22; |
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51 | Net fpga_0_USER_IO_GPIO_in_pin<4> IOSTANDARD = LVTTL; |
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52 | Net fpga_0_USER_IO_GPIO_in_pin<5> LOC=AJ15; |
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53 | Net fpga_0_USER_IO_GPIO_in_pin<5> IOSTANDARD = LVTTL; |
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54 | Net fpga_0_USER_IO_GPIO_in_pin<6> LOC=AG18; |
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55 | Net fpga_0_USER_IO_GPIO_in_pin<6> IOSTANDARD = LVTTL; |
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56 | Net fpga_0_USER_IO_GPIO_in_pin<7> LOC=AG17; |
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57 | Net fpga_0_USER_IO_GPIO_in_pin<7> IOSTANDARD = LVTTL; |
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58 | Net fpga_0_USER_IO_GPIO2_d_out_pin<0> LOC=AJ26; |
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59 | Net fpga_0_USER_IO_GPIO2_d_out_pin<0> IOSTANDARD = LVTTL; |
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60 | Net fpga_0_USER_IO_GPIO2_d_out_pin<1> LOC=AH26; |
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61 | Net fpga_0_USER_IO_GPIO2_d_out_pin<1> IOSTANDARD = LVTTL; |
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62 | Net fpga_0_USER_IO_GPIO2_d_out_pin<2> LOC=AH24; |
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63 | Net fpga_0_USER_IO_GPIO2_d_out_pin<2> IOSTANDARD = LVTTL; |
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64 | Net fpga_0_USER_IO_GPIO2_d_out_pin<3> LOC=AH25; |
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65 | Net fpga_0_USER_IO_GPIO2_d_out_pin<3> IOSTANDARD = LVTTL; |
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66 | Net fpga_0_USER_IO_GPIO2_d_out_pin<4> LOC=AH23; |
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67 | Net fpga_0_USER_IO_GPIO2_d_out_pin<4> IOSTANDARD = LVTTL; |
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68 | Net fpga_0_USER_IO_GPIO2_d_out_pin<5> LOC=AG22; |
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69 | Net fpga_0_USER_IO_GPIO2_d_out_pin<5> IOSTANDARD = LVTTL; |
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70 | Net fpga_0_USER_IO_GPIO2_d_out_pin<6> LOC=AG23; |
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71 | Net fpga_0_USER_IO_GPIO2_d_out_pin<6> IOSTANDARD = LVTTL; |
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72 | Net fpga_0_USER_IO_GPIO2_d_out_pin<7> LOC=AG19; |
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73 | Net fpga_0_USER_IO_GPIO2_d_out_pin<7> IOSTANDARD = LVTTL; |
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74 | Net fpga_0_USER_IO_GPIO2_d_out_pin<8> LOC=AG21; |
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75 | Net fpga_0_USER_IO_GPIO2_d_out_pin<8> IOSTANDARD = LVTTL; |
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76 | Net fpga_0_USER_IO_GPIO2_d_out_pin<9> LOC=AH19; |
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77 | Net fpga_0_USER_IO_GPIO2_d_out_pin<9> IOSTANDARD = LVTTL; |
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78 | Net fpga_0_USER_IO_GPIO2_d_out_pin<10> LOC=AJ19; |
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79 | Net fpga_0_USER_IO_GPIO2_d_out_pin<10> IOSTANDARD = LVTTL; |
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80 | Net fpga_0_USER_IO_GPIO2_d_out_pin<11> LOC=AP12; |
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81 | Net fpga_0_USER_IO_GPIO2_d_out_pin<11> IOSTANDARD = LVTTL; |
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82 | Net fpga_0_USER_IO_GPIO2_d_out_pin<12> LOC=AN13; |
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83 | Net fpga_0_USER_IO_GPIO2_d_out_pin<12> IOSTANDARD = LVTTL; |
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84 | Net fpga_0_USER_IO_GPIO2_d_out_pin<13> LOC=AL15; |
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85 | Net fpga_0_USER_IO_GPIO2_d_out_pin<13> IOSTANDARD = LVTTL; |
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86 | Net fpga_0_USER_IO_GPIO2_d_out_pin<14> LOC=AJ14; |
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87 | Net fpga_0_USER_IO_GPIO2_d_out_pin<14> IOSTANDARD = LVTTL; |
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88 | Net fpga_0_USER_IO_GPIO2_d_out_pin<15> LOC=AM13; |
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89 | Net fpga_0_USER_IO_GPIO2_d_out_pin<15> IOSTANDARD = LVTTL; |
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90 | Net fpga_0_USER_IO_GPIO2_d_out_pin<16> LOC=AR12; |
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91 | Net fpga_0_USER_IO_GPIO2_d_out_pin<16> IOSTANDARD = LVTTL; |
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92 | Net fpga_0_USER_IO_GPIO2_d_out_pin<17> LOC=AH13; |
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93 | Net fpga_0_USER_IO_GPIO2_d_out_pin<17> IOSTANDARD = LVTTL; |
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94 | |
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95 | #### Module rs232 constraints |
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96 | |
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97 | Net fpga_0_rs232_RX_pin LOC=AA29; |
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98 | Net fpga_0_rs232_RX_pin IOSTANDARD = LVTTL; |
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99 | Net fpga_0_rs232_TX_pin LOC=AA28; |
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100 | Net fpga_0_rs232_TX_pin IOSTANDARD = LVTTL; |
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101 | |
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102 | #### Module clk_board_config constraints |
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103 | |
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104 | Net fpga_0_clk_board_config_sys_clk_pin LOC=AH21; |
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105 | Net fpga_0_clk_board_config_sys_clk_pin IOSTANDARD = LVTTL; |
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106 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN25; |
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107 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin IOSTANDARD=LVTTL; |
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108 | Net fpga_0_clk_board_config_cfg_radio_dat_out_pin SLEW = SLOW; |
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109 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AK26; |
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110 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin IOSTANDARD=LVTTL; |
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111 | Net fpga_0_clk_board_config_cfg_radio_csb_out_pin SLEW = SLOW; |
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112 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AJ25; |
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113 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin IOSTANDARD=LVTTL; |
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114 | Net fpga_0_clk_board_config_cfg_radio_en_out_pin SLEW = SLOW; |
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115 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AL26; |
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116 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin IOSTANDARD=LVTTL; |
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117 | Net fpga_0_clk_board_config_cfg_radio_clk_out_pin SLEW = SLOW; |
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118 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AT27; |
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119 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin IOSTANDARD=LVTTL; |
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120 | Net fpga_0_clk_board_config_cfg_logic_dat_out_pin SLEW = SLOW; |
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121 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AR27; |
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122 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin IOSTANDARD=LVTTL; |
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123 | Net fpga_0_clk_board_config_cfg_logic_csb_out_pin SLEW = SLOW; |
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124 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AN27; |
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125 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin IOSTANDARD=LVTTL; |
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126 | Net fpga_0_clk_board_config_cfg_logic_en_out_pin SLEW = SLOW; |
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127 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AM27; |
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128 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin IOSTANDARD=LVTTL; |
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129 | Net fpga_0_clk_board_config_cfg_logic_clk_out_pin SLEW = SLOW; |
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130 | |
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131 | #### Module eeprom_controller constraints |
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132 | |
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133 | Net fpga_0_eeprom_controller_DQ0_pin LOC=AB28; |
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134 | Net fpga_0_eeprom_controller_DQ0_pin IOSTANDARD = LVTTL; |
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135 | Net fpga_0_eeprom_controller_DQ0_pin SLEW = SLOW; |
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136 | Net fpga_0_eeprom_controller_DQ0_pin DRIVE = 8; |
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137 | |
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138 | #### Module Ethernet_MAC constraints |
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139 | |
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140 | Net fpga_0_Ethernet_MAC_slew1_pin LOC=H20; |
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141 | Net fpga_0_Ethernet_MAC_slew1_pin IOSTANDARD = LVTTL; |
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142 | Net fpga_0_Ethernet_MAC_slew1_pin SLEW = SLOW; |
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143 | Net fpga_0_Ethernet_MAC_slew1_pin DRIVE = 8; |
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144 | Net fpga_0_Ethernet_MAC_slew2_pin LOC=J22; |
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145 | Net fpga_0_Ethernet_MAC_slew2_pin IOSTANDARD = LVTTL; |
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146 | Net fpga_0_Ethernet_MAC_slew2_pin SLEW = SLOW; |
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147 | Net fpga_0_Ethernet_MAC_slew2_pin DRIVE = 8; |
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148 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin LOC=J27; |
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149 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin IOSTANDARD = LVTTL; |
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150 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin SLEW = SLOW; |
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151 | Net fpga_0_Ethernet_MAC_PHY_rst_n_pin DRIVE = 8; |
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152 | Net fpga_0_Ethernet_MAC_PHY_crs_pin LOC=D29; |
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153 | Net fpga_0_Ethernet_MAC_PHY_crs_pin IOSTANDARD = LVTTL; |
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154 | Net fpga_0_Ethernet_MAC_PHY_col_pin LOC=J26; |
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155 | Net fpga_0_Ethernet_MAC_PHY_col_pin IOSTANDARD = LVTTL; |
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156 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> LOC=G26; |
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157 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> IOSTANDARD = LVTTL; |
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158 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> SLEW = SLOW; |
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159 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<3> DRIVE = 8; |
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160 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> LOC=D26; |
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161 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> IOSTANDARD = LVTTL; |
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162 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> SLEW = SLOW; |
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163 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<2> DRIVE = 8; |
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164 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> LOC=H23; |
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165 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> IOSTANDARD = LVTTL; |
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166 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> SLEW = SLOW; |
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167 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<1> DRIVE = 8; |
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168 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> LOC=D22; |
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169 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> IOSTANDARD = LVTTL; |
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170 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> SLEW = SLOW; |
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171 | Net fpga_0_Ethernet_MAC_PHY_tx_data_pin<0> DRIVE = 8; |
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172 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin LOC=H22; |
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173 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin IOSTANDARD = LVTTL; |
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174 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin SLEW = SLOW; |
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175 | Net fpga_0_Ethernet_MAC_PHY_tx_en_pin DRIVE = 8; |
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176 | Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin LOC=F20; |
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177 | Net fpga_0_Ethernet_MAC_PHY_tx_clk_pin IOSTANDARD = LVTTL; |
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178 | Net fpga_0_Ethernet_MAC_PHY_rx_er_pin LOC=F21; |
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179 | Net fpga_0_Ethernet_MAC_PHY_rx_er_pin IOSTANDARD = LVTTL; |
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180 | Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin LOC=E24; |
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181 | Net fpga_0_Ethernet_MAC_PHY_rx_clk_pin IOSTANDARD = LVTTL; |
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182 | Net fpga_0_Ethernet_MAC_PHY_dv_pin LOC=F22; |
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183 | Net fpga_0_Ethernet_MAC_PHY_dv_pin IOSTANDARD = LVTTL; |
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184 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> LOC=C22; |
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185 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<0> IOSTANDARD = LVTTL; |
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186 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> LOC=E21; |
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187 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<1> IOSTANDARD = LVTTL; |
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188 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> LOC=C21; |
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189 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<2> IOSTANDARD = LVTTL; |
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190 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> LOC=D23; |
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191 | Net fpga_0_Ethernet_MAC_PHY_rx_data_pin<3> IOSTANDARD = LVTTL; |
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192 | |
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193 | #### Module radio_controller_0 constraints |
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194 | |
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195 | #### Module radio_bridge_slot_2 constraints |
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196 | |
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197 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AG2; |
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198 | Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin IOSTANDARD=LVTTL; |
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199 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AB7; |
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200 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> IOSTANDARD = LVTTL; |
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201 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> SLEW = SLOW; |
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202 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AB8; |
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203 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> IOSTANDARD = LVTTL; |
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204 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> SLEW = SLOW; |
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205 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=AC10; |
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206 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> IOSTANDARD = LVTTL; |
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207 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> SLEW = SLOW; |
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208 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=AB9; |
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209 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> IOSTANDARD = LVTTL; |
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210 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> SLEW = SLOW; |
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211 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AF3; |
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212 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> IOSTANDARD = LVTTL; |
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213 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> SLEW = SLOW; |
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214 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=AL1; |
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215 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> IOSTANDARD = LVTTL; |
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216 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> SLEW = SLOW; |
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217 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AE4; |
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218 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> IOSTANDARD = LVTTL; |
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219 | Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> SLEW = SLOW; |
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220 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=AD4; |
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221 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> IOSTANDARD = LVTTL; |
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222 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> PULLDOWN; |
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223 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=AB11; |
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224 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> IOSTANDARD = LVTTL; |
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225 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> PULLDOWN; |
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226 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=AB10; |
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227 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> IOSTANDARD = LVTTL; |
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228 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> PULLDOWN; |
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229 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG20; |
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230 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> IOSTANDARD = LVTTL; |
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231 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> PULLDOWN; |
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232 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=AG1; |
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233 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> IOSTANDARD = LVTTL; |
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234 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> PULLDOWN; |
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235 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=AE3; |
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236 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> IOSTANDARD = LVTTL; |
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237 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> PULLDOWN; |
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238 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AC5; |
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239 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> IOSTANDARD = LVTTL; |
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240 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> PULLDOWN; |
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241 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=AE1; |
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242 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> IOSTANDARD = LVTTL; |
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243 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> PULLDOWN; |
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244 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AB5; |
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245 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> IOSTANDARD = LVTTL; |
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246 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> PULLDOWN; |
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247 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=AB4; |
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248 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> IOSTANDARD = LVTTL; |
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249 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> PULLDOWN; |
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250 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=AB6; |
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251 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> IOSTANDARD = LVTTL; |
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252 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> PULLDOWN; |
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253 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AD2; |
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254 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> IOSTANDARD = LVTTL; |
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255 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> PULLDOWN; |
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256 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=AA7; |
---|
257 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> IOSTANDARD = LVTTL; |
---|
258 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> PULLDOWN; |
---|
259 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=AB3; |
---|
260 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> IOSTANDARD = LVTTL; |
---|
261 | Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> PULLDOWN; |
---|
262 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AE7; |
---|
263 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
264 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> PULLDOWN; |
---|
265 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AC12; |
---|
266 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
267 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> PULLDOWN; |
---|
268 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AJ2; |
---|
269 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
270 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> PULLDOWN; |
---|
271 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AG5; |
---|
272 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
273 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> PULLDOWN; |
---|
274 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AJ1; |
---|
275 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
276 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> PULLDOWN; |
---|
277 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AH3; |
---|
278 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
279 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> PULLDOWN; |
---|
280 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AH4; |
---|
281 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
282 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> PULLDOWN; |
---|
283 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AJ3; |
---|
284 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
285 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> PULLDOWN; |
---|
286 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=AA10; |
---|
287 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
288 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> PULLDOWN; |
---|
289 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=AE2; |
---|
290 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
291 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> PULLDOWN; |
---|
292 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=AA12; |
---|
293 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
294 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> PULLDOWN; |
---|
295 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AF1; |
---|
296 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
297 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> PULLDOWN; |
---|
298 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=AD3; |
---|
299 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
300 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> PULLDOWN; |
---|
301 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=AF2; |
---|
302 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
303 | Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> PULLDOWN; |
---|
304 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AD13; |
---|
305 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> IOSTANDARD = LVTTL; |
---|
306 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AT8; |
---|
307 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> IOSTANDARD = LVTTL; |
---|
308 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AR8; |
---|
309 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> IOSTANDARD = LVTTL; |
---|
310 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AT5; |
---|
311 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> IOSTANDARD = LVTTL; |
---|
312 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AH11; |
---|
313 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> IOSTANDARD = LVTTL; |
---|
314 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AT6; |
---|
315 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> IOSTANDARD = LVTTL; |
---|
316 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AD12; |
---|
317 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> IOSTANDARD = LVTTL; |
---|
318 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5; |
---|
319 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> IOSTANDARD = LVTTL; |
---|
320 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AN9; |
---|
321 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> IOSTANDARD = LVTTL; |
---|
322 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AE13; |
---|
323 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> IOSTANDARD = LVTTL; |
---|
324 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AK9; |
---|
325 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> IOSTANDARD = LVTTL; |
---|
326 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AR7; |
---|
327 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> IOSTANDARD = LVTTL; |
---|
328 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AP7; |
---|
329 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> IOSTANDARD = LVTTL; |
---|
330 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AF12; |
---|
331 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> IOSTANDARD = LVTTL; |
---|
332 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AH10; |
---|
333 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> IOSTANDARD = LVTTL; |
---|
334 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AM6; |
---|
335 | Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> IOSTANDARD = LVTTL; |
---|
336 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AE10; |
---|
337 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
338 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AH8; |
---|
339 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
340 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AM4; |
---|
341 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
342 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AL7; |
---|
343 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
344 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AE11; |
---|
345 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
346 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AL6; |
---|
347 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
348 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AN6; |
---|
349 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
350 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AK8; |
---|
351 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
352 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AG9; |
---|
353 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
354 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AM7; |
---|
355 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
356 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AL9; |
---|
357 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
358 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AE12; |
---|
359 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
360 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AN7; |
---|
361 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
362 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AH7; |
---|
363 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
364 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AR6; |
---|
365 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL; |
---|
366 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AM8; |
---|
367 | Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL; |
---|
368 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AL5; |
---|
369 | Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin IOSTANDARD=LVTTL; |
---|
370 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AJ6; |
---|
371 | Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin IOSTANDARD=LVTTL; |
---|
372 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK6; |
---|
373 | Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin IOSTANDARD=LVTTL; |
---|
374 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AL3; |
---|
375 | Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin IOSTANDARD=LVTTL; |
---|
376 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AK4; |
---|
377 | Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin IOSTANDARD=LVTTL; |
---|
378 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AF9; |
---|
379 | Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin IOSTANDARD=LVTTL; |
---|
380 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AF5; |
---|
381 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin IOSTANDARD=LVTTL; |
---|
382 | Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin SLEW = SLOW; |
---|
383 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=AM2; |
---|
384 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin IOSTANDARD=LVTTL; |
---|
385 | Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin SLEW = SLOW; |
---|
386 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AD10; |
---|
387 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin IOSTANDARD=LVTTL; |
---|
388 | Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin SLEW = SLOW; |
---|
389 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AE6; |
---|
390 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin IOSTANDARD=LVTTL; |
---|
391 | Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin SLEW = SLOW; |
---|
392 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=AA9; |
---|
393 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin IOSTANDARD=LVTTL; |
---|
394 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin SLEW = SLOW; |
---|
395 | Net fpga_0_radio_bridge_slot_2_radio_24PA_pin DRIVE = 2; |
---|
396 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AB2; |
---|
397 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin IOSTANDARD=LVTTL; |
---|
398 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin SLEW = SLOW; |
---|
399 | Net fpga_0_radio_bridge_slot_2_radio_5PA_pin DRIVE = 2; |
---|
400 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=AB1; |
---|
401 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> IOSTANDARD=LVTTL; |
---|
402 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> SLEW = SLOW; |
---|
403 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> DRIVE = 2; |
---|
404 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=AA6; |
---|
405 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> IOSTANDARD=LVTTL; |
---|
406 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> SLEW = SLOW; |
---|
407 | Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> DRIVE = 2; |
---|
408 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA5; |
---|
409 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> IOSTANDARD=LVTTL; |
---|
410 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> SLEW = SLOW; |
---|
411 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> DRIVE = 2; |
---|
412 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=AA8; |
---|
413 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> IOSTANDARD=LVTTL; |
---|
414 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> SLEW = SLOW; |
---|
415 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> DRIVE = 2; |
---|
416 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=AC2; |
---|
417 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> IOSTANDARD=LVTTL; |
---|
418 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> SLEW = SLOW; |
---|
419 | Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> DRIVE = 2; |
---|
420 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AD8; |
---|
421 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL; |
---|
422 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AK1; |
---|
423 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL; |
---|
424 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=AA3; |
---|
425 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL; |
---|
426 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AF6; |
---|
427 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL; |
---|
428 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=AG7; |
---|
429 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> IOSTANDARD=LVTTL; |
---|
430 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AL2; |
---|
431 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> IOSTANDARD=LVTTL; |
---|
432 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=AJ4; |
---|
433 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> IOSTANDARD=LVTTL; |
---|
434 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AK3; |
---|
435 | Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> IOSTANDARD=LVTTL; |
---|
436 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AK2; |
---|
437 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL; |
---|
438 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AH6; |
---|
439 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL; |
---|
440 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AF8; |
---|
441 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL; |
---|
442 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AF7; |
---|
443 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL; |
---|
444 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AF11; |
---|
445 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL; |
---|
446 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> PULLDOWN; |
---|
447 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AE8; |
---|
448 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL; |
---|
449 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> PULLDOWN; |
---|
450 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AF10; |
---|
451 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL; |
---|
452 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> PULLDOWN; |
---|
453 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AD11; |
---|
454 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL; |
---|
455 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> PULLDOWN; |
---|
456 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AJ7; |
---|
457 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL; |
---|
458 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> PULLDOWN; |
---|
459 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AJ5; |
---|
460 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL; |
---|
461 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> PULLDOWN; |
---|
462 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AJ8; |
---|
463 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL; |
---|
464 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> PULLDOWN; |
---|
465 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AG11; |
---|
466 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL; |
---|
467 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> PULLDOWN; |
---|
468 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AM9; |
---|
469 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL; |
---|
470 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> PULLDOWN; |
---|
471 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AK7; |
---|
472 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL; |
---|
473 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> PULLDOWN; |
---|
474 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AK5; |
---|
475 | Net fpga_0_radio_bridge_slot_2_radio_LD_pin IOSTANDARD=LVTTL; |
---|
476 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=AA4; |
---|
477 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL; |
---|
478 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=AC4; |
---|
479 | Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL; |
---|
480 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AJ9; |
---|
481 | Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL; |
---|
482 | Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin LOC=AG10; |
---|
483 | Net fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL; |
---|
484 | Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin LOC=AM3; |
---|
485 | Net fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin IOSTANDARD=LVTTL; |
---|
486 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO LOC=AG3; |
---|
487 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO IOSTANDARD=LVTTL; |
---|
488 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO SLEW = SLOW; |
---|
489 | Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO DRIVE = 8; |
---|
490 | |
---|
491 | #### Module radio_bridge_slot_3 constraints |
---|
492 | |
---|
493 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AP33; |
---|
494 | Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin IOSTANDARD=LVTTL; |
---|
495 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AJ33; |
---|
496 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> IOSTANDARD = LVTTL; |
---|
497 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> SLEW = SLOW; |
---|
498 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AL37; |
---|
499 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> IOSTANDARD = LVTTL; |
---|
500 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> SLEW = SLOW; |
---|
501 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AK36; |
---|
502 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> IOSTANDARD = LVTTL; |
---|
503 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> SLEW = SLOW; |
---|
504 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AM38; |
---|
505 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> IOSTANDARD = LVTTL; |
---|
506 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> SLEW = SLOW; |
---|
507 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AK37; |
---|
508 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> IOSTANDARD = LVTTL; |
---|
509 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> SLEW = SLOW; |
---|
510 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AJ36; |
---|
511 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> IOSTANDARD = LVTTL; |
---|
512 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> SLEW = SLOW; |
---|
513 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AL38; |
---|
514 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> IOSTANDARD = LVTTL; |
---|
515 | Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> SLEW = SLOW; |
---|
516 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AG29; |
---|
517 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> IOSTANDARD = LVTTL; |
---|
518 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> PULLDOWN; |
---|
519 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AR34; |
---|
520 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> IOSTANDARD = LVTTL; |
---|
521 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> PULLDOWN; |
---|
522 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AU35; |
---|
523 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> IOSTANDARD = LVTTL; |
---|
524 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> PULLDOWN; |
---|
525 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AJ21; |
---|
526 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> IOSTANDARD = LVTTL; |
---|
527 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> PULLDOWN; |
---|
528 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AT32; |
---|
529 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> IOSTANDARD = LVTTL; |
---|
530 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> PULLDOWN; |
---|
531 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AT34; |
---|
532 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> IOSTANDARD = LVTTL; |
---|
533 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> PULLDOWN; |
---|
534 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AR33; |
---|
535 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> IOSTANDARD = LVTTL; |
---|
536 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> PULLDOWN; |
---|
537 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AM36; |
---|
538 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> IOSTANDARD = LVTTL; |
---|
539 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> PULLDOWN; |
---|
540 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AD28; |
---|
541 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> IOSTANDARD = LVTTL; |
---|
542 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> PULLDOWN; |
---|
543 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AL33; |
---|
544 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> IOSTANDARD = LVTTL; |
---|
545 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> PULLDOWN; |
---|
546 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AH32; |
---|
547 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> IOSTANDARD = LVTTL; |
---|
548 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> PULLDOWN; |
---|
549 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AD29; |
---|
550 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> IOSTANDARD = LVTTL; |
---|
551 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> PULLDOWN; |
---|
552 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AK33; |
---|
553 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> IOSTANDARD = LVTTL; |
---|
554 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> PULLDOWN; |
---|
555 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AE31; |
---|
556 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> IOSTANDARD = LVTTL; |
---|
557 | Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> PULLDOWN; |
---|
558 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AH29; |
---|
559 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
560 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> PULLDOWN; |
---|
561 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AK31; |
---|
562 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
563 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> PULLDOWN; |
---|
564 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AE28; |
---|
565 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
566 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> PULLDOWN; |
---|
567 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AF28; |
---|
568 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
569 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> PULLDOWN; |
---|
570 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AE27; |
---|
571 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
572 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> PULLDOWN; |
---|
573 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AD27; |
---|
574 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
575 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> PULLDOWN; |
---|
576 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AN33; |
---|
577 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
578 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> PULLDOWN; |
---|
579 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AL31; |
---|
580 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
581 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> PULLDOWN; |
---|
582 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AR32; |
---|
583 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
584 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> PULLDOWN; |
---|
585 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AM33; |
---|
586 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
587 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> PULLDOWN; |
---|
588 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AG30; |
---|
589 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
590 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> PULLDOWN; |
---|
591 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AM32; |
---|
592 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
593 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> PULLDOWN; |
---|
594 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AE29; |
---|
595 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
596 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> PULLDOWN; |
---|
597 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AN31; |
---|
598 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
599 | Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> PULLDOWN; |
---|
600 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB30; |
---|
601 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> IOSTANDARD = LVTTL; |
---|
602 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AF38; |
---|
603 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> IOSTANDARD = LVTTL; |
---|
604 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AD37; |
---|
605 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> IOSTANDARD = LVTTL; |
---|
606 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=AF37; |
---|
607 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> IOSTANDARD = LVTTL; |
---|
608 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB34; |
---|
609 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> IOSTANDARD = LVTTL; |
---|
610 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=AF39; |
---|
611 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> IOSTANDARD = LVTTL; |
---|
612 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA30; |
---|
613 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> IOSTANDARD = LVTTL; |
---|
614 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=AC35; |
---|
615 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> IOSTANDARD = LVTTL; |
---|
616 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC36; |
---|
617 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> IOSTANDARD = LVTTL; |
---|
618 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=AE38; |
---|
619 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> IOSTANDARD = LVTTL; |
---|
620 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AE36; |
---|
621 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> IOSTANDARD = LVTTL; |
---|
622 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=AB36; |
---|
623 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> IOSTANDARD = LVTTL; |
---|
624 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=AB33; |
---|
625 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> IOSTANDARD = LVTTL; |
---|
626 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=AE39; |
---|
627 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> IOSTANDARD = LVTTL; |
---|
628 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=AB35; |
---|
629 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> IOSTANDARD = LVTTL; |
---|
630 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=AB32; |
---|
631 | Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> IOSTANDARD = LVTTL; |
---|
632 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=AD32; |
---|
633 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> IOSTANDARD = LVTTL; |
---|
634 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AK39; |
---|
635 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> IOSTANDARD = LVTTL; |
---|
636 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=AF34; |
---|
637 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> IOSTANDARD = LVTTL; |
---|
638 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=AB29; |
---|
639 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> IOSTANDARD = LVTTL; |
---|
640 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=AC27; |
---|
641 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> IOSTANDARD = LVTTL; |
---|
642 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AE34; |
---|
643 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> IOSTANDARD = LVTTL; |
---|
644 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=AJ37; |
---|
645 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> IOSTANDARD = LVTTL; |
---|
646 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=AC30; |
---|
647 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> IOSTANDARD = LVTTL; |
---|
648 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=AH36; |
---|
649 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> IOSTANDARD = LVTTL; |
---|
650 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AJ38; |
---|
651 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> IOSTANDARD = LVTTL; |
---|
652 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=AJ39; |
---|
653 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> IOSTANDARD = LVTTL; |
---|
654 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AG39; |
---|
655 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> IOSTANDARD = LVTTL; |
---|
656 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=AF33; |
---|
657 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> IOSTANDARD = LVTTL; |
---|
658 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=AH37; |
---|
659 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> IOSTANDARD = LVTTL; |
---|
660 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=AG34; |
---|
661 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> IOSTANDARD = LVTTL; |
---|
662 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=AG38; |
---|
663 | Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> IOSTANDARD = LVTTL; |
---|
664 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=AC32; |
---|
665 | Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin IOSTANDARD=LVTTL; |
---|
666 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=AB31; |
---|
667 | Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin IOSTANDARD=LVTTL; |
---|
668 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AC31; |
---|
669 | Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin IOSTANDARD=LVTTL; |
---|
670 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AD33; |
---|
671 | Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin IOSTANDARD=LVTTL; |
---|
672 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AK38; |
---|
673 | Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin IOSTANDARD=LVTTL; |
---|
674 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AC28; |
---|
675 | Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin IOSTANDARD=LVTTL; |
---|
676 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AE30; |
---|
677 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin IOSTANDARD=LVTTL; |
---|
678 | Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin SLEW = SLOW; |
---|
679 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AC34; |
---|
680 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin IOSTANDARD=LVTTL; |
---|
681 | Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin SLEW = SLOW; |
---|
682 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=AL34; |
---|
683 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin IOSTANDARD=LVTTL; |
---|
684 | Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin SLEW = SLOW; |
---|
685 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AK32; |
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686 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin IOSTANDARD=LVTTL; |
---|
687 | Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin SLEW = SLOW; |
---|
688 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AE33; |
---|
689 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin IOSTANDARD=LVTTL; |
---|
690 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin SLEW = SLOW; |
---|
691 | Net fpga_0_radio_bridge_slot_3_radio_24PA_pin DRIVE = 2; |
---|
692 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AH34; |
---|
693 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin IOSTANDARD=LVTTL; |
---|
694 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin SLEW = SLOW; |
---|
695 | Net fpga_0_radio_bridge_slot_3_radio_5PA_pin DRIVE = 2; |
---|
696 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AG33; |
---|
697 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> IOSTANDARD=LVTTL; |
---|
698 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> SLEW = SLOW; |
---|
699 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> DRIVE = 2; |
---|
700 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AH33; |
---|
701 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> IOSTANDARD=LVTTL; |
---|
702 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> SLEW = SLOW; |
---|
703 | Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> DRIVE = 2; |
---|
704 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AN34; |
---|
705 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> IOSTANDARD=LVTTL; |
---|
706 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> SLEW = SLOW; |
---|
707 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> DRIVE = 2; |
---|
708 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AK35; |
---|
709 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> IOSTANDARD=LVTTL; |
---|
710 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> SLEW = SLOW; |
---|
711 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> DRIVE = 2; |
---|
712 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AK34; |
---|
713 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> IOSTANDARD=LVTTL; |
---|
714 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> SLEW = SLOW; |
---|
715 | Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> DRIVE = 2; |
---|
716 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AH30; |
---|
717 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin IOSTANDARD=LVTTL; |
---|
718 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AM34; |
---|
719 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin IOSTANDARD=LVTTL; |
---|
720 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AD30; |
---|
721 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin IOSTANDARD=LVTTL; |
---|
722 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AF29; |
---|
723 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin IOSTANDARD=LVTTL; |
---|
724 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG37; |
---|
725 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> IOSTANDARD=LVTTL; |
---|
726 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AD34; |
---|
727 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> IOSTANDARD=LVTTL; |
---|
728 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=AF36; |
---|
729 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> IOSTANDARD=LVTTL; |
---|
730 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AL39; |
---|
731 | Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> IOSTANDARD=LVTTL; |
---|
732 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AM37; |
---|
733 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin IOSTANDARD=LVTTL; |
---|
734 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=AA32; |
---|
735 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin IOSTANDARD=LVTTL; |
---|
736 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=AB38; |
---|
737 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin IOSTANDARD=LVTTL; |
---|
738 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=AA37; |
---|
739 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin IOSTANDARD=LVTTL; |
---|
740 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=AA33; |
---|
741 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> IOSTANDARD=LVTTL; |
---|
742 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> PULLDOWN; |
---|
743 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AD36; |
---|
744 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> IOSTANDARD=LVTTL; |
---|
745 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> PULLDOWN; |
---|
746 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=AC38; |
---|
747 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> IOSTANDARD=LVTTL; |
---|
748 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> PULLDOWN; |
---|
749 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AB37; |
---|
750 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> IOSTANDARD=LVTTL; |
---|
751 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> PULLDOWN; |
---|
752 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=AA36; |
---|
753 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> IOSTANDARD=LVTTL; |
---|
754 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> PULLDOWN; |
---|
755 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=AC39; |
---|
756 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> IOSTANDARD=LVTTL; |
---|
757 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> PULLDOWN; |
---|
758 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=AA34; |
---|
759 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> IOSTANDARD=LVTTL; |
---|
760 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> PULLDOWN; |
---|
761 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=AA31; |
---|
762 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> IOSTANDARD=LVTTL; |
---|
763 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> PULLDOWN; |
---|
764 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AA35; |
---|
765 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> IOSTANDARD=LVTTL; |
---|
766 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> PULLDOWN; |
---|
767 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=AE37; |
---|
768 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> IOSTANDARD=LVTTL; |
---|
769 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> PULLDOWN; |
---|
770 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AG35; |
---|
771 | Net fpga_0_radio_bridge_slot_3_radio_LD_pin IOSTANDARD=LVTTL; |
---|
772 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AG31; |
---|
773 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin IOSTANDARD=LVTTL; |
---|
774 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AF30; |
---|
775 | Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin IOSTANDARD=LVTTL; |
---|
776 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=AD38; |
---|
777 | Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin IOSTANDARD=LVTTL; |
---|
778 | Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin LOC=AH38; |
---|
779 | Net fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin IOSTANDARD=LVTTL; |
---|
780 | Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin LOC=AE35; |
---|
781 | Net fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin IOSTANDARD=LVTTL; |
---|
782 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO LOC=AJ31; |
---|
783 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO IOSTANDARD=LVTTL; |
---|
784 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO SLEW = SLOW; |
---|
785 | Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO DRIVE = 8; |
---|
786 | |
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