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2 | # ##############################################################################
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3 | # Created by Base System Builder Wizard for Xilinx EDK 10.1.03 Build EDK_K_SP3.6
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4 | # Thu Jan 08 11:25:14 2009
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5 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 1.2 / Radio 1.4 / Clock 1.1
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6 | # Family: virtex2p
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7 | # Device: XC2VP70
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8 | # Package: FF1517
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9 | # Speed Grade: -6
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10 | # Processor: ppc405_0
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11 | # Processor clock frequency: 240.00 MHz
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12 | # Bus clock frequency: 80.00 MHz
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13 | # On Chip Memory : 96 KB
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14 | # ##############################################################################
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15 | # ##############################################################################
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16 | # Template for PPC405 v3 with PLBv46 bus interface
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17 | # ##############################################################################
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18 | PARAMETER VERSION = 2.1.0
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19 |
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20 |
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21 | PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk, DIR = I
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22 | PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out, DIR = O
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23 | PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out, DIR = O
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24 | PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out, DIR = O
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25 | PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out, DIR = O
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26 | PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out, DIR = O
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27 | PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out, DIR = O
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28 | PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out, DIR = O
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29 | PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out, DIR = O
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30 | PORT fpga_0_radio_bridge_slot_1_converter_clock_out_pin = fpga_0_radio_bridge_slot_1_converter_clock_out, DIR = O
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31 | PORT fpga_0_radio_bridge_slot_1_radio_EEPROM_IO = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO, DIR = IO
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32 | PORT fpga_0_radio_bridge_slot_1_dac_spi_clk_pin = fpga_0_radio_bridge_slot_1_dac_spi_clk, DIR = O
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33 | PORT fpga_0_radio_bridge_slot_1_dac_spi_cs_pin = fpga_0_radio_bridge_slot_1_dac_spi_cs, DIR = O
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34 | PORT fpga_0_radio_bridge_slot_1_dac_spi_data_pin = fpga_0_radio_bridge_slot_1_dac_spi_data, DIR = O
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35 | PORT fpga_0_radio_bridge_slot_1_radio_24PA_pin = fpga_0_radio_bridge_slot_1_radio_24PA, DIR = O
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36 | PORT fpga_0_radio_bridge_slot_1_radio_5PA_pin = fpga_0_radio_bridge_slot_1_radio_5PA, DIR = O
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37 | PORT fpga_0_radio_bridge_slot_1_radio_ANTSW_pin = fpga_0_radio_bridge_slot_1_radio_ANTSW, DIR = O, VEC = [1:0]
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38 | PORT fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK, DIR = I
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39 | PORT fpga_0_radio_bridge_slot_1_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_1_radio_dac_RESET, DIR = O
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40 | PORT fpga_0_radio_bridge_slot_1_radio_DIPSW_pin = fpga_0_radio_bridge_slot_1_radio_DIPSW, DIR = I, VEC = [3:0]
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41 | PORT fpga_0_radio_bridge_slot_1_radio_LD_pin = fpga_0_radio_bridge_slot_1_radio_LD, DIR = I
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42 | PORT fpga_0_radio_bridge_slot_1_radio_LED_pin = fpga_0_radio_bridge_slot_1_radio_LED, DIR = O, VEC = [2:0]
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43 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk, DIR = O
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44 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP, DIR = O
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45 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
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46 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ, DIR = O
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47 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR, DIR = I
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48 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP, DIR = O
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49 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS, DIR = O
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50 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS, DIR = O
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51 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA, DIR = I
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52 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB, DIR = I
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53 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA, DIR = O
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54 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB, DIR = O
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55 | PORT fpga_0_radio_bridge_slot_1_radio_TxEn_pin = fpga_0_radio_bridge_slot_1_radio_TxEn, DIR = O
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56 | PORT fpga_0_radio_bridge_slot_1_radio_RxEn_pin = fpga_0_radio_bridge_slot_1_radio_RxEn, DIR = O
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57 | PORT fpga_0_radio_bridge_slot_1_radio_RxHP_pin = fpga_0_radio_bridge_slot_1_radio_RxHP, DIR = O
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58 | PORT fpga_0_radio_bridge_slot_1_radio_SHDN_pin = fpga_0_radio_bridge_slot_1_radio_SHDN, DIR = O
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59 | PORT fpga_0_radio_bridge_slot_1_radio_spi_clk_pin = fpga_0_radio_bridge_slot_1_radio_spi_clk, DIR = O
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60 | PORT fpga_0_radio_bridge_slot_1_radio_spi_cs_pin = fpga_0_radio_bridge_slot_1_radio_spi_cs, DIR = O
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61 | PORT fpga_0_radio_bridge_slot_1_radio_spi_data_pin = fpga_0_radio_bridge_slot_1_radio_spi_data, DIR = O
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62 | PORT fpga_0_radio_bridge_slot_1_radio_B_pin = fpga_0_radio_bridge_slot_1_radio_B, DIR = O, VEC = [6:0]
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63 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_I_pin = fpga_0_radio_bridge_slot_1_radio_DAC_I, DIR = O, VEC = [15:0]
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64 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_1_radio_DAC_Q, DIR = O, VEC = [15:0]
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65 | PORT fpga_0_radio_bridge_slot_1_radio_ADC_I_pin = fpga_0_radio_bridge_slot_1_radio_ADC_I, DIR = I, VEC = [13:0]
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66 | PORT fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_1_radio_ADC_Q, DIR = I, VEC = [13:0]
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67 | PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out, DIR = O
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68 | PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO, DIR = IO
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69 | PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk, DIR = O
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70 | PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs, DIR = O
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71 | PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data, DIR = O
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72 | PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA, DIR = O
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73 | PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA, DIR = O
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74 | PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW, DIR = O, VEC = [1:0]
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75 | PORT fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK, DIR = I
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76 | PORT fpga_0_radio_bridge_slot_2_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_2_radio_dac_RESET, DIR = O
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77 | PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW, DIR = I, VEC = [3:0]
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78 | PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD, DIR = I
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79 | PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED, DIR = O, VEC = [2:0]
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80 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk, DIR = O
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81 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP, DIR = O
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82 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
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83 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ, DIR = O
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84 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR, DIR = I
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85 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP, DIR = O
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86 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS, DIR = O
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87 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS, DIR = O
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88 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA, DIR = I
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89 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB, DIR = I
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90 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA, DIR = O
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91 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB, DIR = O
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92 | PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn, DIR = O
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93 | PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn, DIR = O
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94 | PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP, DIR = O
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95 | PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN, DIR = O
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96 | PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk, DIR = O
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97 | PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs, DIR = O
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98 | PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data, DIR = O
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99 | PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B, DIR = O, VEC = [6:0]
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100 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I, DIR = O, VEC = [15:0]
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101 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q, DIR = O, VEC = [15:0]
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102 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I, DIR = I, VEC = [13:0]
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103 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q, DIR = I, VEC = [13:0]
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104 | PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out, DIR = O
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105 | PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO, DIR = IO
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106 | PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk, DIR = O
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107 | PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs, DIR = O
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108 | PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data, DIR = O
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109 | PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA, DIR = O
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110 | PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA, DIR = O
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111 | PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW, DIR = O, VEC = [1:0]
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112 | PORT fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK, DIR = I
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113 | PORT fpga_0_radio_bridge_slot_3_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_3_radio_dac_RESET, DIR = O
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114 | PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW, DIR = I, VEC = [3:0]
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115 | PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD, DIR = I
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116 | PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED, DIR = O, VEC = [2:0]
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117 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk, DIR = O
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118 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP, DIR = O
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119 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
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120 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ, DIR = O
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121 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR, DIR = I
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122 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP, DIR = O
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123 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS, DIR = O
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124 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS, DIR = O
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125 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA, DIR = I
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126 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB, DIR = I
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127 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA, DIR = O
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128 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB, DIR = O
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129 | PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn, DIR = O
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130 | PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn, DIR = O
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131 | PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP, DIR = O
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132 | PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN, DIR = O
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133 | PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk, DIR = O
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134 | PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs, DIR = O
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135 | PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data, DIR = O
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136 | PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B, DIR = O, VEC = [6:0]
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137 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I, DIR = O, VEC = [15:0]
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138 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q, DIR = O, VEC = [15:0]
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139 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I, DIR = I, VEC = [13:0]
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140 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q, DIR = I, VEC = [13:0]
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141 | PORT fpga_0_radio_bridge_slot_4_converter_clock_out_pin = fpga_0_radio_bridge_slot_4_converter_clock_out, DIR = O
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142 | PORT fpga_0_radio_bridge_slot_4_radio_EEPROM_IO = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO, DIR = IO
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143 | PORT fpga_0_radio_bridge_slot_4_dac_spi_clk_pin = fpga_0_radio_bridge_slot_4_dac_spi_clk, DIR = O
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144 | PORT fpga_0_radio_bridge_slot_4_dac_spi_cs_pin = fpga_0_radio_bridge_slot_4_dac_spi_cs, DIR = O
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145 | PORT fpga_0_radio_bridge_slot_4_dac_spi_data_pin = fpga_0_radio_bridge_slot_4_dac_spi_data, DIR = O
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146 | PORT fpga_0_radio_bridge_slot_4_radio_24PA_pin = fpga_0_radio_bridge_slot_4_radio_24PA, DIR = O
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147 | PORT fpga_0_radio_bridge_slot_4_radio_5PA_pin = fpga_0_radio_bridge_slot_4_radio_5PA, DIR = O
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148 | PORT fpga_0_radio_bridge_slot_4_radio_ANTSW_pin = fpga_0_radio_bridge_slot_4_radio_ANTSW, DIR = O, VEC = [1:0]
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149 | PORT fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK_pin = fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK, DIR = I
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150 | PORT fpga_0_radio_bridge_slot_4_radio_dac_RESET_pin = fpga_0_radio_bridge_slot_4_radio_dac_RESET, DIR = O
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151 | PORT fpga_0_radio_bridge_slot_4_radio_DIPSW_pin = fpga_0_radio_bridge_slot_4_radio_DIPSW, DIR = I, VEC = [3:0]
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152 | PORT fpga_0_radio_bridge_slot_4_radio_LD_pin = fpga_0_radio_bridge_slot_4_radio_LD, DIR = I
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153 | PORT fpga_0_radio_bridge_slot_4_radio_LED_pin = fpga_0_radio_bridge_slot_4_radio_LED, DIR = O, VEC = [2:0]
|
---|
154 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk, DIR = O
|
---|
155 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP, DIR = O
|
---|
156 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D, DIR = I, VEC = [9:0]
|
---|
157 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ, DIR = O
|
---|
158 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR, DIR = I
|
---|
159 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP, DIR = O
|
---|
160 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS, DIR = O
|
---|
161 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS, DIR = O
|
---|
162 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA, DIR = I
|
---|
163 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB, DIR = I
|
---|
164 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA, DIR = O
|
---|
165 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB, DIR = O
|
---|
166 | PORT fpga_0_radio_bridge_slot_4_radio_TxEn_pin = fpga_0_radio_bridge_slot_4_radio_TxEn, DIR = O
|
---|
167 | PORT fpga_0_radio_bridge_slot_4_radio_RxEn_pin = fpga_0_radio_bridge_slot_4_radio_RxEn, DIR = O
|
---|
168 | PORT fpga_0_radio_bridge_slot_4_radio_RxHP_pin = fpga_0_radio_bridge_slot_4_radio_RxHP, DIR = O
|
---|
169 | PORT fpga_0_radio_bridge_slot_4_radio_SHDN_pin = fpga_0_radio_bridge_slot_4_radio_SHDN, DIR = O
|
---|
170 | PORT fpga_0_radio_bridge_slot_4_radio_spi_clk_pin = fpga_0_radio_bridge_slot_4_radio_spi_clk, DIR = O
|
---|
171 | PORT fpga_0_radio_bridge_slot_4_radio_spi_cs_pin = fpga_0_radio_bridge_slot_4_radio_spi_cs, DIR = O
|
---|
172 | PORT fpga_0_radio_bridge_slot_4_radio_spi_data_pin = fpga_0_radio_bridge_slot_4_radio_spi_data, DIR = O
|
---|
173 | PORT fpga_0_radio_bridge_slot_4_radio_B_pin = fpga_0_radio_bridge_slot_4_radio_B, DIR = O, VEC = [6:0]
|
---|
174 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_I_pin = fpga_0_radio_bridge_slot_4_radio_DAC_I, DIR = O, VEC = [15:0]
|
---|
175 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_4_radio_DAC_Q, DIR = O, VEC = [15:0]
|
---|
176 | PORT fpga_0_radio_bridge_slot_4_radio_ADC_I_pin = fpga_0_radio_bridge_slot_4_radio_ADC_I, DIR = I, VEC = [13:0]
|
---|
177 | PORT fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_4_radio_ADC_Q, DIR = I, VEC = [13:0]
|
---|
178 | PORT fpga_0_USER_IO_GPIO2_d_out_pin = fpga_0_USER_IO_GPIO2_d_out, DIR = O, VEC = [0:17]
|
---|
179 | PORT fpga_0_USER_IO_GPIO_in_pin = fpga_0_USER_IO_GPIO_in, DIR = I, VEC = [0:7]
|
---|
180 | PORT fpga_0_rs232_RX_pin = fpga_0_rs232_RX, DIR = I
|
---|
181 | PORT fpga_0_rs232_TX_pin = fpga_0_rs232_TX, DIR = O
|
---|
182 | PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0, DIR = IO
|
---|
183 | PORT fpga_0_Ethernet_MAC_slew1_pin = net_vcc, DIR = O
|
---|
184 | PORT fpga_0_Ethernet_MAC_slew2_pin = net_vcc, DIR = O
|
---|
185 | PORT fpga_0_Ethernet_MAC_PHY_rst_n_pin = fpga_0_Ethernet_MAC_PHY_rst_n, DIR = O
|
---|
186 | PORT fpga_0_Ethernet_MAC_PHY_crs_pin = fpga_0_Ethernet_MAC_PHY_crs, DIR = I
|
---|
187 | PORT fpga_0_Ethernet_MAC_PHY_col_pin = fpga_0_Ethernet_MAC_PHY_col, DIR = I
|
---|
188 | PORT fpga_0_Ethernet_MAC_PHY_tx_data_pin = fpga_0_Ethernet_MAC_PHY_tx_data, DIR = O, VEC = [3:0]
|
---|
189 | PORT fpga_0_Ethernet_MAC_PHY_tx_en_pin = fpga_0_Ethernet_MAC_PHY_tx_en, DIR = O
|
---|
190 | PORT fpga_0_Ethernet_MAC_PHY_tx_clk_pin = fpga_0_Ethernet_MAC_PHY_tx_clk, DIR = I
|
---|
191 | PORT fpga_0_Ethernet_MAC_PHY_rx_er_pin = fpga_0_Ethernet_MAC_PHY_rx_er, DIR = I
|
---|
192 | PORT fpga_0_Ethernet_MAC_PHY_rx_clk_pin = fpga_0_Ethernet_MAC_PHY_rx_clk, DIR = I
|
---|
193 | PORT fpga_0_Ethernet_MAC_PHY_dv_pin = fpga_0_Ethernet_MAC_PHY_dv, DIR = I
|
---|
194 | PORT fpga_0_Ethernet_MAC_PHY_rx_data_pin = fpga_0_Ethernet_MAC_PHY_rx_data, DIR = I, VEC = [3:0]
|
---|
195 | PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
|
---|
196 | PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 1, SIGIS = RST
|
---|
197 | PORT debug = rxrun & txrun & agcsetdone & ff_fpga_0_Ethernet_MAC_PHY_ensigs & 0b0 & 0b0 & 0b0 & debug_sw_gpio_O, VEC = [0:15], DIR = O
|
---|
198 |
|
---|
199 |
|
---|
200 | BEGIN ppc405
|
---|
201 | PARAMETER INSTANCE = ppc405_0
|
---|
202 | PARAMETER HW_VER = 3.00.a
|
---|
203 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
|
---|
204 | BUS_INTERFACE DPLB0 = plb0
|
---|
205 | BUS_INTERFACE IPLB0 = plb0
|
---|
206 | BUS_INTERFACE JTAGPPC = jtagppc_cntlr_0_0
|
---|
207 | BUS_INTERFACE ISOCM = ppc405_0_iocm
|
---|
208 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
209 | BUS_INTERFACE RESETPPC = ppc_reset_bus
|
---|
210 | PORT BRAMISOCMCLK = sys_clk_s
|
---|
211 | PORT BRAMDSOCMCLK = sys_clk_s
|
---|
212 | PORT CPMC405CLOCK = proc_clk_s
|
---|
213 | END
|
---|
214 |
|
---|
215 | BEGIN jtagppc_cntlr
|
---|
216 | PARAMETER INSTANCE = jtagppc_cntlr_0
|
---|
217 | PARAMETER HW_VER = 2.01.c
|
---|
218 | BUS_INTERFACE JTAGPPC0 = jtagppc_cntlr_0_0
|
---|
219 | END
|
---|
220 |
|
---|
221 | BEGIN plb_v46
|
---|
222 | PARAMETER INSTANCE = plb0
|
---|
223 | PARAMETER C_DCR_INTFCE = 0
|
---|
224 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
225 | PARAMETER HW_VER = 1.03.a
|
---|
226 | PORT PLB_Clk = sys_clk_s
|
---|
227 | PORT SYS_Rst = sys_bus_reset
|
---|
228 | END
|
---|
229 |
|
---|
230 | BEGIN xps_gpio
|
---|
231 | PARAMETER INSTANCE = USER_IO
|
---|
232 | PARAMETER HW_VER = 1.00.a
|
---|
233 | PARAMETER C_GPIO_WIDTH = 18
|
---|
234 | PARAMETER C_IS_DUAL = 1
|
---|
235 | PARAMETER C_IS_BIDIR = 0
|
---|
236 | PARAMETER C_ALL_INPUTS = 1
|
---|
237 | PARAMETER C_IS_BIDIR_2 = 1
|
---|
238 | PARAMETER C_ALL_INPUTS_2 = 0
|
---|
239 | PARAMETER C_BASEADDR = 0x81420000
|
---|
240 | PARAMETER C_HIGHADDR = 0x8142ffff
|
---|
241 | BUS_INTERFACE SPLB = plb0
|
---|
242 | PORT GPIO_in = fpga_0_USER_IO_GPIO_in & 0b0000000000
|
---|
243 | PORT GPIO2_d_out = fpga_0_USER_IO_GPIO2_d_out
|
---|
244 | END
|
---|
245 |
|
---|
246 | BEGIN xps_uartlite
|
---|
247 | PARAMETER INSTANCE = rs232
|
---|
248 | PARAMETER HW_VER = 1.00.a
|
---|
249 | PARAMETER C_BAUDRATE = 57600
|
---|
250 | PARAMETER C_DATA_BITS = 8
|
---|
251 | PARAMETER C_ODD_PARITY = 0
|
---|
252 | PARAMETER C_USE_PARITY = 0
|
---|
253 | PARAMETER C_SPLB_CLK_FREQ_HZ = 80000000
|
---|
254 | PARAMETER C_BASEADDR = 0x84000000
|
---|
255 | PARAMETER C_HIGHADDR = 0x8400ffff
|
---|
256 | BUS_INTERFACE SPLB = plb0
|
---|
257 | PORT RX = fpga_0_rs232_RX
|
---|
258 | PORT TX = fpga_0_rs232_TX
|
---|
259 | END
|
---|
260 |
|
---|
261 | BEGIN clock_board_config
|
---|
262 | PARAMETER INSTANCE = clk_board_config
|
---|
263 | PARAMETER HW_VER = 1.04.a
|
---|
264 | PARAMETER radio_clk_out4_mode = 0x1eff
|
---|
265 | PARAMETER radio_clk_out7_mode = 0x1eff
|
---|
266 | PARAMETER logic_clk_out0_mode = 0x08ff
|
---|
267 | PARAMETER logic_clk_out1_mode = 0x08ff
|
---|
268 | PORT sys_clk = fpga_0_clk_board_config_sys_clk
|
---|
269 | PORT sys_rst = net_gnd
|
---|
270 | PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out
|
---|
271 | PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out
|
---|
272 | PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out
|
---|
273 | PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out
|
---|
274 | PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out
|
---|
275 | PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out
|
---|
276 | PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out
|
---|
277 | PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out
|
---|
278 | PORT config_invalid = clk_board_config_config_invalid
|
---|
279 | END
|
---|
280 |
|
---|
281 | BEGIN eeprom
|
---|
282 | PARAMETER INSTANCE = eeprom_controller
|
---|
283 | PARAMETER HW_VER = 1.07.a
|
---|
284 | PARAMETER C_MEM0_BASEADDR = 0xc5400000
|
---|
285 | PARAMETER C_MEM0_HIGHADDR = 0xc540ffff
|
---|
286 | BUS_INTERFACE SPLB = plb_32b_40MHz
|
---|
287 | PORT DQ0 = fpga_0_eeprom_controller_DQ0
|
---|
288 | PORT DQ1_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T
|
---|
289 | PORT DQ1_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O
|
---|
290 | PORT DQ1_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I
|
---|
291 | PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
|
---|
292 | PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
|
---|
293 | PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
|
---|
294 | PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
|
---|
295 | PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
|
---|
296 | PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
|
---|
297 | PORT DQ4_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T
|
---|
298 | PORT DQ4_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O
|
---|
299 | PORT DQ4_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I
|
---|
300 | PORT DQ5_I = net_vcc
|
---|
301 | PORT DQ6_I = net_vcc
|
---|
302 | PORT DQ7_I = net_vcc
|
---|
303 | PORT SPLB_Rst = net_gnd
|
---|
304 | END
|
---|
305 |
|
---|
306 | BEGIN xps_ethernetlite
|
---|
307 | PARAMETER INSTANCE = Ethernet_MAC
|
---|
308 | PARAMETER HW_VER = 2.00.b
|
---|
309 | PARAMETER C_SPLB_CLK_PERIOD_PS = 12500
|
---|
310 | PARAMETER C_BASEADDR = 0x81000000
|
---|
311 | PARAMETER C_HIGHADDR = 0x8100ffff
|
---|
312 | BUS_INTERFACE SPLB = plb0
|
---|
313 | PORT PHY_rst_n = fpga_0_Ethernet_MAC_PHY_rst_n
|
---|
314 | PORT PHY_crs = fpga_0_Ethernet_MAC_PHY_crs
|
---|
315 | PORT PHY_col = fpga_0_Ethernet_MAC_PHY_col
|
---|
316 | PORT PHY_tx_data = fpga_0_Ethernet_MAC_PHY_tx_data
|
---|
317 | PORT PHY_tx_en = fpga_0_Ethernet_MAC_PHY_tx_en
|
---|
318 | PORT PHY_tx_clk = fpga_0_Ethernet_MAC_PHY_tx_clk
|
---|
319 | PORT PHY_rx_er = fpga_0_Ethernet_MAC_PHY_rx_er
|
---|
320 | PORT PHY_rx_clk = fpga_0_Ethernet_MAC_PHY_rx_clk
|
---|
321 | PORT PHY_dv = fpga_0_Ethernet_MAC_PHY_dv
|
---|
322 | PORT PHY_rx_data = fpga_0_Ethernet_MAC_PHY_rx_data
|
---|
323 | END
|
---|
324 |
|
---|
325 | BEGIN radio_controller
|
---|
326 | PARAMETER INSTANCE = radio_controller_0
|
---|
327 | PARAMETER HW_VER = 1.22.a
|
---|
328 | PARAMETER C_BASEADDR = 0xcac00000
|
---|
329 | PARAMETER C_HIGHADDR = 0xcac0ffff
|
---|
330 | BUS_INTERFACE SPLB = plb_32b_40MHz
|
---|
331 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk
|
---|
332 | PORT spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
|
---|
333 | PORT data_out = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
|
---|
334 | PORT radio1_cs = radio_bridge_slot_1_controller_radio_cs_radio_controller_0_radio1_cs
|
---|
335 | PORT radio2_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs
|
---|
336 | PORT radio3_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs
|
---|
337 | PORT radio4_cs = radio_bridge_slot_4_controller_radio_cs_radio_controller_0_radio4_cs
|
---|
338 | PORT dac1_cs = radio_bridge_slot_1_controller_dac_cs_radio_controller_0_dac1_cs
|
---|
339 | PORT dac2_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs
|
---|
340 | PORT dac3_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs
|
---|
341 | PORT dac4_cs = radio_bridge_slot_4_controller_dac_cs_radio_controller_0_dac4_cs
|
---|
342 | PORT radio1_SHDN = radio_bridge_slot_1_controller_SHDN_radio_controller_0_radio1_SHDN
|
---|
343 | PORT radio1_TxEn = radio_bridge_slot_1_controller_TxEn_radio_controller_0_radio1_TxEn
|
---|
344 | PORT radio1_RxEn = radio_bridge_slot_1_controller_RxEn_radio_controller_0_radio1_RxEn
|
---|
345 | PORT radio1_RxHP = radio_bridge_slot_1_controller_RxHP_radio_controller_0_radio1_RxHP
|
---|
346 | PORT radio1_LD = radio_bridge_slot_1_controller_LD_radio_controller_0_radio1_LD
|
---|
347 | PORT radio1_24PA = radio_bridge_slot_1_controller_24PA_radio_controller_0_radio1_24PA
|
---|
348 | PORT radio1_5PA = radio_bridge_slot_1_controller_5PA_radio_controller_0_radio1_5PA
|
---|
349 | PORT radio1_ANTSW = radio_bridge_slot_1_controller_ANTSW_radio_controller_0_radio1_ANTSW
|
---|
350 | PORT radio1_LED = radio_bridge_slot_1_controller_LED_radio_controller_0_radio1_LED
|
---|
351 | PORT radio1_ADC_RX_DCS = radio_bridge_slot_1_controller_RX_ADC_DCS_radio_controller_0_radio1_ADC_RX_DCS
|
---|
352 | PORT radio1_ADC_RX_DFS = radio_bridge_slot_1_controller_RX_ADC_DFS_radio_controller_0_radio1_ADC_RX_DFS
|
---|
353 | PORT radio1_ADC_RX_OTRA = radio_bridge_slot_1_controller_RX_ADC_OTRA_radio_controller_0_radio1_ADC_RX_OTRA
|
---|
354 | PORT radio1_ADC_RX_OTRB = radio_bridge_slot_1_controller_RX_ADC_OTRB_radio_controller_0_radio1_ADC_RX_OTRB
|
---|
355 | PORT radio1_ADC_RX_PWDNA = radio_bridge_slot_1_controller_RX_ADC_PWDNA_radio_controller_0_radio1_ADC_RX_PWDNA
|
---|
356 | PORT radio1_ADC_RX_PWDNB = radio_bridge_slot_1_controller_RX_ADC_PWDNB_radio_controller_0_radio1_ADC_RX_PWDNB
|
---|
357 | PORT radio1_DIPSW = radio_bridge_slot_1_controller_DIPSW_radio_controller_0_radio1_DIPSW
|
---|
358 | PORT radio1_RSSI_ADC_CLAMP = radio_bridge_slot_1_controller_RSSI_ADC_CLAMP_radio_controller_0_radio1_RSSI_ADC_CLAMP
|
---|
359 | PORT radio1_RSSI_ADC_HIZ = radio_bridge_slot_1_controller_RSSI_ADC_HIZ_radio_controller_0_radio1_RSSI_ADC_HIZ
|
---|
360 | PORT radio1_RSSI_ADC_OTR = radio_bridge_slot_1_controller_RSSI_ADC_OTR_radio_controller_0_radio1_RSSI_ADC_OTR
|
---|
361 | PORT radio1_RSSI_ADC_SLEEP = radio_bridge_slot_1_controller_RSSI_ADC_SLEEP_radio_controller_0_radio1_RSSI_ADC_SLEEP
|
---|
362 | PORT radio1_RSSI_ADC_D = radio_bridge_slot_1_controller_RSSI_ADC_D_radio_controller_0_radio1_RSSI_ADC_D
|
---|
363 | PORT radio1_TX_DAC_PLL_LOCK = radio_bridge_slot_1_controller_dac_PLL_LOCK_radio_controller_0_radio1_TX_DAC_PLL_LOCK
|
---|
364 | PORT radio1_TX_DAC_RESET = radio_bridge_slot_1_controller_dac_RESET_radio_controller_0_radio1_TX_DAC_RESET
|
---|
365 | PORT radio1_SHDN_external = radio_bridge_slot_1_controller_SHDN_external_radio_controller_0_radio1_SHDN_external
|
---|
366 | PORT radio1_TxEn_external = radio_bridge_slot_1_controller_TxEn_external_radio_controller_0_radio1_TxEn_external
|
---|
367 | PORT radio1_RxEn_external = radio_bridge_slot_1_controller_RxEn_external_radio_controller_0_radio1_RxEn_external
|
---|
368 | PORT radio1_RxHP_external = radio_bridge_slot_1_controller_RxHP_external_radio_controller_0_radio1_RxHP_external
|
---|
369 | PORT radio1_TxGain = radio_bridge_slot_1_user_Tx_gain_radio_controller_0_radio1_TxGain
|
---|
370 | PORT radio1_TxStart = radio_bridge_slot_1_controller_TxStart_radio_controller_0_radio1_TxStart
|
---|
371 | PORT radio2_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN
|
---|
372 | PORT radio2_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn
|
---|
373 | PORT radio2_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn
|
---|
374 | PORT radio2_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP
|
---|
375 | PORT radio2_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD
|
---|
376 | PORT radio2_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA
|
---|
377 | PORT radio2_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA
|
---|
378 | PORT radio2_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW
|
---|
379 | PORT radio2_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED
|
---|
380 | PORT radio2_ADC_RX_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS
|
---|
381 | PORT radio2_ADC_RX_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS
|
---|
382 | PORT radio2_ADC_RX_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA
|
---|
383 | PORT radio2_ADC_RX_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB
|
---|
384 | PORT radio2_ADC_RX_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA
|
---|
385 | PORT radio2_ADC_RX_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB
|
---|
386 | PORT radio2_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW
|
---|
387 | PORT radio2_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP
|
---|
388 | PORT radio2_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ
|
---|
389 | PORT radio2_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR
|
---|
390 | PORT radio2_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP
|
---|
391 | PORT radio2_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D
|
---|
392 | PORT radio2_TX_DAC_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK
|
---|
393 | PORT radio2_TX_DAC_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET
|
---|
394 | PORT radio2_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external
|
---|
395 | PORT radio2_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external
|
---|
396 | PORT radio2_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external
|
---|
397 | PORT radio2_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external
|
---|
398 | PORT radio2_TxGain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain
|
---|
399 | PORT radio2_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart
|
---|
400 | PORT radio3_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN
|
---|
401 | PORT radio3_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn
|
---|
402 | PORT radio3_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn
|
---|
403 | PORT radio3_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP
|
---|
404 | PORT radio3_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD
|
---|
405 | PORT radio3_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA
|
---|
406 | PORT radio3_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA
|
---|
407 | PORT radio3_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW
|
---|
408 | PORT radio3_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED
|
---|
409 | PORT radio3_ADC_RX_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS
|
---|
410 | PORT radio3_ADC_RX_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS
|
---|
411 | PORT radio3_ADC_RX_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA
|
---|
412 | PORT radio3_ADC_RX_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB
|
---|
413 | PORT radio3_ADC_RX_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA
|
---|
414 | PORT radio3_ADC_RX_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB
|
---|
415 | PORT radio3_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW
|
---|
416 | PORT radio3_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP
|
---|
417 | PORT radio3_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ
|
---|
418 | PORT radio3_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR
|
---|
419 | PORT radio3_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP
|
---|
420 | PORT radio3_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D
|
---|
421 | PORT radio3_TX_DAC_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK
|
---|
422 | PORT radio3_TX_DAC_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET
|
---|
423 | PORT radio3_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external
|
---|
424 | PORT radio3_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external
|
---|
425 | PORT radio3_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external
|
---|
426 | PORT radio3_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external
|
---|
427 | PORT radio3_TxGain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain
|
---|
428 | PORT radio3_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart
|
---|
429 | PORT radio4_SHDN = radio_bridge_slot_4_controller_SHDN_radio_controller_0_radio4_SHDN
|
---|
430 | PORT radio4_TxEn = radio_bridge_slot_4_controller_TxEn_radio_controller_0_radio4_TxEn
|
---|
431 | PORT radio4_RxEn = radio_bridge_slot_4_controller_RxEn_radio_controller_0_radio4_RxEn
|
---|
432 | PORT radio4_RxHP = radio_bridge_slot_4_controller_RxHP_radio_controller_0_radio4_RxHP
|
---|
433 | PORT radio4_LD = radio_bridge_slot_4_controller_LD_radio_controller_0_radio4_LD
|
---|
434 | PORT radio4_24PA = radio_bridge_slot_4_controller_24PA_radio_controller_0_radio4_24PA
|
---|
435 | PORT radio4_5PA = radio_bridge_slot_4_controller_5PA_radio_controller_0_radio4_5PA
|
---|
436 | PORT radio4_ANTSW = radio_bridge_slot_4_controller_ANTSW_radio_controller_0_radio4_ANTSW
|
---|
437 | PORT radio4_LED = radio_bridge_slot_4_controller_LED_radio_controller_0_radio4_LED
|
---|
438 | PORT radio4_ADC_RX_DCS = radio_bridge_slot_4_controller_RX_ADC_DCS_radio_controller_0_radio4_ADC_RX_DCS
|
---|
439 | PORT radio4_ADC_RX_DFS = radio_bridge_slot_4_controller_RX_ADC_DFS_radio_controller_0_radio4_ADC_RX_DFS
|
---|
440 | PORT radio4_ADC_RX_OTRA = radio_bridge_slot_4_controller_RX_ADC_OTRA_radio_controller_0_radio4_ADC_RX_OTRA
|
---|
441 | PORT radio4_ADC_RX_OTRB = radio_bridge_slot_4_controller_RX_ADC_OTRB_radio_controller_0_radio4_ADC_RX_OTRB
|
---|
442 | PORT radio4_ADC_RX_PWDNA = radio_bridge_slot_4_controller_RX_ADC_PWDNA_radio_controller_0_radio4_ADC_RX_PWDNA
|
---|
443 | PORT radio4_ADC_RX_PWDNB = radio_bridge_slot_4_controller_RX_ADC_PWDNB_radio_controller_0_radio4_ADC_RX_PWDNB
|
---|
444 | PORT radio4_DIPSW = radio_bridge_slot_4_controller_DIPSW_radio_controller_0_radio4_DIPSW
|
---|
445 | PORT radio4_RSSI_ADC_CLAMP = radio_bridge_slot_4_controller_RSSI_ADC_CLAMP_radio_controller_0_radio4_RSSI_ADC_CLAMP
|
---|
446 | PORT radio4_RSSI_ADC_HIZ = radio_bridge_slot_4_controller_RSSI_ADC_HIZ_radio_controller_0_radio4_RSSI_ADC_HIZ
|
---|
447 | PORT radio4_RSSI_ADC_OTR = radio_bridge_slot_4_controller_RSSI_ADC_OTR_radio_controller_0_radio4_RSSI_ADC_OTR
|
---|
448 | PORT radio4_RSSI_ADC_SLEEP = radio_bridge_slot_4_controller_RSSI_ADC_SLEEP_radio_controller_0_radio4_RSSI_ADC_SLEEP
|
---|
449 | PORT radio4_RSSI_ADC_D = radio_bridge_slot_4_controller_RSSI_ADC_D_radio_controller_0_radio4_RSSI_ADC_D
|
---|
450 | PORT radio4_TX_DAC_PLL_LOCK = radio_bridge_slot_4_controller_dac_PLL_LOCK_radio_controller_0_radio4_TX_DAC_PLL_LOCK
|
---|
451 | PORT radio4_TX_DAC_RESET = radio_bridge_slot_4_controller_dac_RESET_radio_controller_0_radio4_TX_DAC_RESET
|
---|
452 | PORT radio4_SHDN_external = radio_bridge_slot_4_controller_SHDN_external_radio_controller_0_radio4_SHDN_external
|
---|
453 | PORT radio4_TxEn_external = radio_bridge_slot_4_controller_TxEn_external_radio_controller_0_radio4_TxEn_external
|
---|
454 | PORT radio4_RxEn_external = radio_bridge_slot_4_controller_RxEn_external_radio_controller_0_radio4_RxEn_external
|
---|
455 | PORT radio4_RxHP_external = radio_bridge_slot_4_controller_RxHP_external_radio_controller_0_radio4_RxHP_external
|
---|
456 | PORT radio4_TxGain = radio_bridge_slot_4_user_Tx_gain_radio_controller_0_radio4_TxGain
|
---|
457 | PORT radio4_TxStart = radio_bridge_slot_4_controller_TxStart_radio_controller_0_radio4_TxStart
|
---|
458 | END
|
---|
459 |
|
---|
460 | BEGIN radio_bridge
|
---|
461 | PARAMETER INSTANCE = radio_bridge_slot_1
|
---|
462 | PARAMETER HW_VER = 1.22.a
|
---|
463 | PORT converter_clock_out = fpga_0_radio_bridge_slot_1_converter_clock_out
|
---|
464 | PORT radio_B = fpga_0_radio_bridge_slot_1_radio_B
|
---|
465 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_1_radio_ADC_I
|
---|
466 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_1_radio_ADC_Q
|
---|
467 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_1_radio_DAC_I
|
---|
468 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_1_radio_DAC_Q
|
---|
469 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk
|
---|
470 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
|
---|
471 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
|
---|
472 | PORT controller_radio_cs = radio_bridge_slot_1_controller_radio_cs_radio_controller_0_radio1_cs
|
---|
473 | PORT controller_dac_cs = radio_bridge_slot_1_controller_dac_cs_radio_controller_0_dac1_cs
|
---|
474 | PORT controller_SHDN = radio_bridge_slot_1_controller_SHDN_radio_controller_0_radio1_SHDN
|
---|
475 | PORT controller_TxEn = radio_bridge_slot_1_controller_TxEn_radio_controller_0_radio1_TxEn
|
---|
476 | PORT controller_RxEn = radio_bridge_slot_1_controller_RxEn_radio_controller_0_radio1_RxEn
|
---|
477 | PORT controller_RxHP = radio_bridge_slot_1_controller_RxHP_radio_controller_0_radio1_RxHP
|
---|
478 | PORT controller_24PA = radio_bridge_slot_1_controller_24PA_radio_controller_0_radio1_24PA
|
---|
479 | PORT controller_5PA = radio_bridge_slot_1_controller_5PA_radio_controller_0_radio1_5PA
|
---|
480 | PORT controller_ANTSW = radio_bridge_slot_1_controller_ANTSW_radio_controller_0_radio1_ANTSW
|
---|
481 | PORT controller_LED = radio_bridge_slot_1_controller_LED_radio_controller_0_radio1_LED
|
---|
482 | PORT controller_RX_ADC_DCS = radio_bridge_slot_1_controller_RX_ADC_DCS_radio_controller_0_radio1_ADC_RX_DCS
|
---|
483 | PORT controller_RX_ADC_DFS = radio_bridge_slot_1_controller_RX_ADC_DFS_radio_controller_0_radio1_ADC_RX_DFS
|
---|
484 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_1_controller_RX_ADC_PWDNA_radio_controller_0_radio1_ADC_RX_PWDNA
|
---|
485 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_1_controller_RX_ADC_PWDNB_radio_controller_0_radio1_ADC_RX_PWDNB
|
---|
486 | PORT controller_DIPSW = radio_bridge_slot_1_controller_DIPSW_radio_controller_0_radio1_DIPSW
|
---|
487 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_1_controller_RSSI_ADC_CLAMP_radio_controller_0_radio1_RSSI_ADC_CLAMP
|
---|
488 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_1_controller_RSSI_ADC_HIZ_radio_controller_0_radio1_RSSI_ADC_HIZ
|
---|
489 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_1_controller_RSSI_ADC_SLEEP_radio_controller_0_radio1_RSSI_ADC_SLEEP
|
---|
490 | PORT controller_RSSI_ADC_D = radio_bridge_slot_1_controller_RSSI_ADC_D_radio_controller_0_radio1_RSSI_ADC_D
|
---|
491 | PORT controller_LD = radio_bridge_slot_1_controller_LD_radio_controller_0_radio1_LD
|
---|
492 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_1_controller_RX_ADC_OTRA_radio_controller_0_radio1_ADC_RX_OTRA
|
---|
493 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_1_controller_RX_ADC_OTRB_radio_controller_0_radio1_ADC_RX_OTRB
|
---|
494 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_1_controller_RSSI_ADC_OTR_radio_controller_0_radio1_RSSI_ADC_OTR
|
---|
495 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_1_controller_dac_PLL_LOCK_radio_controller_0_radio1_TX_DAC_PLL_LOCK
|
---|
496 | PORT controller_dac_RESET = radio_bridge_slot_1_controller_dac_RESET_radio_controller_0_radio1_TX_DAC_RESET
|
---|
497 | PORT user_Tx_gain = radio_bridge_slot_1_user_Tx_gain_radio_controller_0_radio1_TxGain
|
---|
498 | PORT controller_TxStart = radio_bridge_slot_1_controller_TxStart_radio_controller_0_radio1_TxStart
|
---|
499 | PORT controller_SHDN_external = radio_bridge_slot_1_controller_SHDN_external_radio_controller_0_radio1_SHDN_external
|
---|
500 | PORT controller_RxEn_external = radio_bridge_slot_1_controller_RxEn_external_radio_controller_0_radio1_RxEn_external
|
---|
501 | PORT controller_TxEn_external = radio_bridge_slot_1_controller_TxEn_external_radio_controller_0_radio1_TxEn_external
|
---|
502 | PORT controller_RxHP_external = radio_bridge_slot_1_controller_RxHP_external_radio_controller_0_radio1_RxHP_external
|
---|
503 | PORT dac_spi_data = fpga_0_radio_bridge_slot_1_dac_spi_data
|
---|
504 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_1_dac_spi_cs
|
---|
505 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_1_dac_spi_clk
|
---|
506 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_1_radio_spi_clk
|
---|
507 | PORT radio_spi_data = fpga_0_radio_bridge_slot_1_radio_spi_data
|
---|
508 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_1_radio_spi_cs
|
---|
509 | PORT radio_SHDN = fpga_0_radio_bridge_slot_1_radio_SHDN
|
---|
510 | PORT radio_TxEn = fpga_0_radio_bridge_slot_1_radio_TxEn
|
---|
511 | PORT radio_RxEn = fpga_0_radio_bridge_slot_1_radio_RxEn
|
---|
512 | PORT radio_RxHP = fpga_0_radio_bridge_slot_1_radio_RxHP
|
---|
513 | PORT radio_24PA = fpga_0_radio_bridge_slot_1_radio_24PA
|
---|
514 | PORT radio_5PA = fpga_0_radio_bridge_slot_1_radio_5PA
|
---|
515 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_1_radio_ANTSW
|
---|
516 | PORT radio_LED = fpga_0_radio_bridge_slot_1_radio_LED
|
---|
517 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS
|
---|
518 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS
|
---|
519 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA
|
---|
520 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB
|
---|
521 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_1_radio_DIPSW
|
---|
522 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk
|
---|
523 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP
|
---|
524 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ
|
---|
525 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP
|
---|
526 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D
|
---|
527 | PORT radio_LD = fpga_0_radio_bridge_slot_1_radio_LD
|
---|
528 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA
|
---|
529 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB
|
---|
530 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR
|
---|
531 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_1_radio_dac_PLL_LOCK
|
---|
532 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_1_radio_dac_RESET
|
---|
533 | PORT user_EEPROM_IO_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T
|
---|
534 | PORT user_EEPROM_IO_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O
|
---|
535 | PORT user_EEPROM_IO_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I
|
---|
536 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO
|
---|
537 | PORT user_ADC_I = radio_bridge_slot_1_user_ADC_I
|
---|
538 | PORT user_ADC_Q = radio_bridge_slot_1_user_ADC_Q
|
---|
539 | PORT user_DAC_I = radio_bridge_slot_1_user_DAC_I
|
---|
540 | PORT user_DAC_Q = radio_bridge_slot_1_user_DAC_Q
|
---|
541 | PORT user_TxModelStart = radio1_txStart
|
---|
542 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
543 | PORT user_RSSI_ADC_D = radio_bridge_slot_1_user_RSSI_ADC_D
|
---|
544 | PORT converter_clock_in = clk_40MHz
|
---|
545 | PORT user_RxHP_external = agc_rxhp_a
|
---|
546 | PORT user_RxBB_gain = agc_g_bb_a
|
---|
547 | PORT user_RxRF_gain = agc_g_rf_a
|
---|
548 | END
|
---|
549 |
|
---|
550 | BEGIN radio_bridge
|
---|
551 | PARAMETER INSTANCE = radio_bridge_slot_2
|
---|
552 | PARAMETER HW_VER = 1.22.a
|
---|
553 | PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out
|
---|
554 | PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B
|
---|
555 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I
|
---|
556 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q
|
---|
557 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I
|
---|
558 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q
|
---|
559 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk
|
---|
560 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
|
---|
561 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
|
---|
562 | PORT controller_radio_cs = radio_bridge_slot_2_controller_radio_cs_radio_controller_0_radio2_cs
|
---|
563 | PORT controller_dac_cs = radio_bridge_slot_2_controller_dac_cs_radio_controller_0_dac2_cs
|
---|
564 | PORT controller_SHDN = radio_bridge_slot_2_controller_SHDN_radio_controller_0_radio2_SHDN
|
---|
565 | PORT controller_TxEn = radio_bridge_slot_2_controller_TxEn_radio_controller_0_radio2_TxEn
|
---|
566 | PORT controller_RxEn = radio_bridge_slot_2_controller_RxEn_radio_controller_0_radio2_RxEn
|
---|
567 | PORT controller_RxHP = radio_bridge_slot_2_controller_RxHP_radio_controller_0_radio2_RxHP
|
---|
568 | PORT controller_24PA = radio_bridge_slot_2_controller_24PA_radio_controller_0_radio2_24PA
|
---|
569 | PORT controller_5PA = radio_bridge_slot_2_controller_5PA_radio_controller_0_radio2_5PA
|
---|
570 | PORT controller_ANTSW = radio_bridge_slot_2_controller_ANTSW_radio_controller_0_radio2_ANTSW
|
---|
571 | PORT controller_LED = radio_bridge_slot_2_controller_LED_radio_controller_0_radio2_LED
|
---|
572 | PORT controller_RX_ADC_DCS = radio_bridge_slot_2_controller_RX_ADC_DCS_radio_controller_0_radio2_ADC_RX_DCS
|
---|
573 | PORT controller_RX_ADC_DFS = radio_bridge_slot_2_controller_RX_ADC_DFS_radio_controller_0_radio2_ADC_RX_DFS
|
---|
574 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_2_controller_RX_ADC_PWDNA_radio_controller_0_radio2_ADC_RX_PWDNA
|
---|
575 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_2_controller_RX_ADC_PWDNB_radio_controller_0_radio2_ADC_RX_PWDNB
|
---|
576 | PORT controller_DIPSW = radio_bridge_slot_2_controller_DIPSW_radio_controller_0_radio2_DIPSW
|
---|
577 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_2_controller_RSSI_ADC_CLAMP_radio_controller_0_radio2_RSSI_ADC_CLAMP
|
---|
578 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_2_controller_RSSI_ADC_HIZ_radio_controller_0_radio2_RSSI_ADC_HIZ
|
---|
579 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_2_controller_RSSI_ADC_SLEEP_radio_controller_0_radio2_RSSI_ADC_SLEEP
|
---|
580 | PORT controller_RSSI_ADC_D = radio_bridge_slot_2_controller_RSSI_ADC_D_radio_controller_0_radio2_RSSI_ADC_D
|
---|
581 | PORT controller_LD = radio_bridge_slot_2_controller_LD_radio_controller_0_radio2_LD
|
---|
582 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA
|
---|
583 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB
|
---|
584 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_2_controller_RSSI_ADC_OTR_radio_controller_0_radio2_RSSI_ADC_OTR
|
---|
585 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_2_controller_dac_PLL_LOCK_radio_controller_0_radio2_TX_DAC_PLL_LOCK
|
---|
586 | PORT controller_dac_RESET = radio_bridge_slot_2_controller_dac_RESET_radio_controller_0_radio2_TX_DAC_RESET
|
---|
587 | PORT user_Tx_gain = radio_bridge_slot_2_user_Tx_gain_radio_controller_0_radio2_TxGain
|
---|
588 | PORT controller_TxStart = radio_bridge_slot_2_controller_TxStart_radio_controller_0_radio2_TxStart
|
---|
589 | PORT controller_SHDN_external = radio_bridge_slot_2_controller_SHDN_external_radio_controller_0_radio2_SHDN_external
|
---|
590 | PORT controller_RxEn_external = radio_bridge_slot_2_controller_RxEn_external_radio_controller_0_radio2_RxEn_external
|
---|
591 | PORT controller_TxEn_external = radio_bridge_slot_2_controller_TxEn_external_radio_controller_0_radio2_TxEn_external
|
---|
592 | PORT controller_RxHP_external = radio_bridge_slot_2_controller_RxHP_external_radio_controller_0_radio2_RxHP_external
|
---|
593 | PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data
|
---|
594 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs
|
---|
595 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk
|
---|
596 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk
|
---|
597 | PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data
|
---|
598 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs
|
---|
599 | PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN
|
---|
600 | PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn
|
---|
601 | PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn
|
---|
602 | PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP
|
---|
603 | PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA
|
---|
604 | PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA
|
---|
605 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW
|
---|
606 | PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED
|
---|
607 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS
|
---|
608 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS
|
---|
609 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA
|
---|
610 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB
|
---|
611 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW
|
---|
612 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk
|
---|
613 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP
|
---|
614 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ
|
---|
615 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP
|
---|
616 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D
|
---|
617 | PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD
|
---|
618 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA
|
---|
619 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB
|
---|
620 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR
|
---|
621 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_dac_PLL_LOCK
|
---|
622 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_2_radio_dac_RESET
|
---|
623 | PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
|
---|
624 | PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
|
---|
625 | PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
|
---|
626 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO
|
---|
627 | PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I
|
---|
628 | PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q
|
---|
629 | PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I
|
---|
630 | PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q
|
---|
631 | PORT user_TxModelStart = radio2_txStart
|
---|
632 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
633 | PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
634 | PORT converter_clock_in = clk_40MHz
|
---|
635 | PORT user_RxHP_external = agc_rxhp_b
|
---|
636 | PORT user_RxBB_gain = agc_g_bb_b
|
---|
637 | PORT user_RxRF_gain = agc_g_rf_b
|
---|
638 | END
|
---|
639 |
|
---|
640 | BEGIN radio_bridge
|
---|
641 | PARAMETER INSTANCE = radio_bridge_slot_3
|
---|
642 | PARAMETER HW_VER = 1.22.a
|
---|
643 | PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out
|
---|
644 | PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B
|
---|
645 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I
|
---|
646 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q
|
---|
647 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I
|
---|
648 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q
|
---|
649 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk
|
---|
650 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
|
---|
651 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
|
---|
652 | PORT controller_radio_cs = radio_bridge_slot_3_controller_radio_cs_radio_controller_0_radio3_cs
|
---|
653 | PORT controller_dac_cs = radio_bridge_slot_3_controller_dac_cs_radio_controller_0_dac3_cs
|
---|
654 | PORT controller_SHDN = radio_bridge_slot_3_controller_SHDN_radio_controller_0_radio3_SHDN
|
---|
655 | PORT controller_TxEn = radio_bridge_slot_3_controller_TxEn_radio_controller_0_radio3_TxEn
|
---|
656 | PORT controller_RxEn = radio_bridge_slot_3_controller_RxEn_radio_controller_0_radio3_RxEn
|
---|
657 | PORT controller_RxHP = radio_bridge_slot_3_controller_RxHP_radio_controller_0_radio3_RxHP
|
---|
658 | PORT controller_24PA = radio_bridge_slot_3_controller_24PA_radio_controller_0_radio3_24PA
|
---|
659 | PORT controller_5PA = radio_bridge_slot_3_controller_5PA_radio_controller_0_radio3_5PA
|
---|
660 | PORT controller_ANTSW = radio_bridge_slot_3_controller_ANTSW_radio_controller_0_radio3_ANTSW
|
---|
661 | PORT controller_LED = radio_bridge_slot_3_controller_LED_radio_controller_0_radio3_LED
|
---|
662 | PORT controller_RX_ADC_DCS = radio_bridge_slot_3_controller_RX_ADC_DCS_radio_controller_0_radio3_ADC_RX_DCS
|
---|
663 | PORT controller_RX_ADC_DFS = radio_bridge_slot_3_controller_RX_ADC_DFS_radio_controller_0_radio3_ADC_RX_DFS
|
---|
664 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_3_controller_RX_ADC_PWDNA_radio_controller_0_radio3_ADC_RX_PWDNA
|
---|
665 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_3_controller_RX_ADC_PWDNB_radio_controller_0_radio3_ADC_RX_PWDNB
|
---|
666 | PORT controller_DIPSW = radio_bridge_slot_3_controller_DIPSW_radio_controller_0_radio3_DIPSW
|
---|
667 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_3_controller_RSSI_ADC_CLAMP_radio_controller_0_radio3_RSSI_ADC_CLAMP
|
---|
668 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_3_controller_RSSI_ADC_HIZ_radio_controller_0_radio3_RSSI_ADC_HIZ
|
---|
669 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_3_controller_RSSI_ADC_SLEEP_radio_controller_0_radio3_RSSI_ADC_SLEEP
|
---|
670 | PORT controller_RSSI_ADC_D = radio_bridge_slot_3_controller_RSSI_ADC_D_radio_controller_0_radio3_RSSI_ADC_D
|
---|
671 | PORT controller_LD = radio_bridge_slot_3_controller_LD_radio_controller_0_radio3_LD
|
---|
672 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA
|
---|
673 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB
|
---|
674 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_3_controller_RSSI_ADC_OTR_radio_controller_0_radio3_RSSI_ADC_OTR
|
---|
675 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_3_controller_dac_PLL_LOCK_radio_controller_0_radio3_TX_DAC_PLL_LOCK
|
---|
676 | PORT controller_dac_RESET = radio_bridge_slot_3_controller_dac_RESET_radio_controller_0_radio3_TX_DAC_RESET
|
---|
677 | PORT user_Tx_gain = radio_bridge_slot_3_user_Tx_gain_radio_controller_0_radio3_TxGain
|
---|
678 | PORT controller_TxStart = radio_bridge_slot_3_controller_TxStart_radio_controller_0_radio3_TxStart
|
---|
679 | PORT controller_SHDN_external = radio_bridge_slot_3_controller_SHDN_external_radio_controller_0_radio3_SHDN_external
|
---|
680 | PORT controller_RxEn_external = radio_bridge_slot_3_controller_RxEn_external_radio_controller_0_radio3_RxEn_external
|
---|
681 | PORT controller_TxEn_external = radio_bridge_slot_3_controller_TxEn_external_radio_controller_0_radio3_TxEn_external
|
---|
682 | PORT controller_RxHP_external = radio_bridge_slot_3_controller_RxHP_external_radio_controller_0_radio3_RxHP_external
|
---|
683 | PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data
|
---|
684 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs
|
---|
685 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk
|
---|
686 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk
|
---|
687 | PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data
|
---|
688 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs
|
---|
689 | PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN
|
---|
690 | PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn
|
---|
691 | PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn
|
---|
692 | PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP
|
---|
693 | PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA
|
---|
694 | PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA
|
---|
695 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW
|
---|
696 | PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED
|
---|
697 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS
|
---|
698 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS
|
---|
699 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA
|
---|
700 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB
|
---|
701 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW
|
---|
702 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk
|
---|
703 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP
|
---|
704 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ
|
---|
705 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP
|
---|
706 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D
|
---|
707 | PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD
|
---|
708 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA
|
---|
709 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB
|
---|
710 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR
|
---|
711 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_dac_PLL_LOCK
|
---|
712 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_3_radio_dac_RESET
|
---|
713 | PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
|
---|
714 | PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
|
---|
715 | PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
|
---|
716 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO
|
---|
717 | PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I
|
---|
718 | PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q
|
---|
719 | PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I
|
---|
720 | PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q
|
---|
721 | PORT user_TxModelStart = radio3_txStart
|
---|
722 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
723 | PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
724 | PORT converter_clock_in = clk_40MHz
|
---|
725 | PORT user_RxHP_external = agc_rxhp_c
|
---|
726 | PORT user_RxBB_gain = agc_g_bb_c
|
---|
727 | PORT user_RxRF_gain = agc_g_rf_c
|
---|
728 | END
|
---|
729 |
|
---|
730 | BEGIN radio_bridge
|
---|
731 | PARAMETER INSTANCE = radio_bridge_slot_4
|
---|
732 | PARAMETER HW_VER = 1.22.a
|
---|
733 | PORT converter_clock_out = fpga_0_radio_bridge_slot_4_converter_clock_out
|
---|
734 | PORT radio_B = fpga_0_radio_bridge_slot_4_radio_B
|
---|
735 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_4_radio_ADC_I
|
---|
736 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_4_radio_ADC_Q
|
---|
737 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_4_radio_DAC_I
|
---|
738 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_4_radio_DAC_Q
|
---|
739 | PORT controller_logic_clk = radio_bridge_slot_1_controller_logic_clk_radio_bridge_slot_2_controller_logic_clk_radio_bridge_slot_3_controller_logic_clk_radio_bridge_slot_4_controller_logic_clk_radio_controller_0_controller_logic_clk
|
---|
740 | PORT controller_spi_clk = radio_bridge_slot_1_controller_spi_clk_radio_bridge_slot_2_controller_spi_clk_radio_bridge_slot_3_controller_spi_clk_radio_bridge_slot_4_controller_spi_clk_radio_controller_0_spi_clk
|
---|
741 | PORT controller_spi_data = radio_bridge_slot_1_controller_spi_data_radio_bridge_slot_2_controller_spi_data_radio_bridge_slot_3_controller_spi_data_radio_bridge_slot_4_controller_spi_data_radio_controller_0_data_out
|
---|
742 | PORT controller_radio_cs = radio_bridge_slot_4_controller_radio_cs_radio_controller_0_radio4_cs
|
---|
743 | PORT controller_dac_cs = radio_bridge_slot_4_controller_dac_cs_radio_controller_0_dac4_cs
|
---|
744 | PORT controller_SHDN = radio_bridge_slot_4_controller_SHDN_radio_controller_0_radio4_SHDN
|
---|
745 | PORT controller_TxEn = radio_bridge_slot_4_controller_TxEn_radio_controller_0_radio4_TxEn
|
---|
746 | PORT controller_RxEn = radio_bridge_slot_4_controller_RxEn_radio_controller_0_radio4_RxEn
|
---|
747 | PORT controller_RxHP = radio_bridge_slot_4_controller_RxHP_radio_controller_0_radio4_RxHP
|
---|
748 | PORT controller_24PA = radio_bridge_slot_4_controller_24PA_radio_controller_0_radio4_24PA
|
---|
749 | PORT controller_5PA = radio_bridge_slot_4_controller_5PA_radio_controller_0_radio4_5PA
|
---|
750 | PORT controller_ANTSW = radio_bridge_slot_4_controller_ANTSW_radio_controller_0_radio4_ANTSW
|
---|
751 | PORT controller_LED = radio_bridge_slot_4_controller_LED_radio_controller_0_radio4_LED
|
---|
752 | PORT controller_RX_ADC_DCS = radio_bridge_slot_4_controller_RX_ADC_DCS_radio_controller_0_radio4_ADC_RX_DCS
|
---|
753 | PORT controller_RX_ADC_DFS = radio_bridge_slot_4_controller_RX_ADC_DFS_radio_controller_0_radio4_ADC_RX_DFS
|
---|
754 | PORT controller_RX_ADC_PWDNA = radio_bridge_slot_4_controller_RX_ADC_PWDNA_radio_controller_0_radio4_ADC_RX_PWDNA
|
---|
755 | PORT controller_RX_ADC_PWDNB = radio_bridge_slot_4_controller_RX_ADC_PWDNB_radio_controller_0_radio4_ADC_RX_PWDNB
|
---|
756 | PORT controller_DIPSW = radio_bridge_slot_4_controller_DIPSW_radio_controller_0_radio4_DIPSW
|
---|
757 | PORT controller_RSSI_ADC_CLAMP = radio_bridge_slot_4_controller_RSSI_ADC_CLAMP_radio_controller_0_radio4_RSSI_ADC_CLAMP
|
---|
758 | PORT controller_RSSI_ADC_HIZ = radio_bridge_slot_4_controller_RSSI_ADC_HIZ_radio_controller_0_radio4_RSSI_ADC_HIZ
|
---|
759 | PORT controller_RSSI_ADC_SLEEP = radio_bridge_slot_4_controller_RSSI_ADC_SLEEP_radio_controller_0_radio4_RSSI_ADC_SLEEP
|
---|
760 | PORT controller_RSSI_ADC_D = radio_bridge_slot_4_controller_RSSI_ADC_D_radio_controller_0_radio4_RSSI_ADC_D
|
---|
761 | PORT controller_LD = radio_bridge_slot_4_controller_LD_radio_controller_0_radio4_LD
|
---|
762 | PORT controller_RX_ADC_OTRA = radio_bridge_slot_4_controller_RX_ADC_OTRA_radio_controller_0_radio4_ADC_RX_OTRA
|
---|
763 | PORT controller_RX_ADC_OTRB = radio_bridge_slot_4_controller_RX_ADC_OTRB_radio_controller_0_radio4_ADC_RX_OTRB
|
---|
764 | PORT controller_RSSI_ADC_OTR = radio_bridge_slot_4_controller_RSSI_ADC_OTR_radio_controller_0_radio4_RSSI_ADC_OTR
|
---|
765 | PORT controller_dac_PLL_LOCK = radio_bridge_slot_4_controller_dac_PLL_LOCK_radio_controller_0_radio4_TX_DAC_PLL_LOCK
|
---|
766 | PORT controller_dac_RESET = radio_bridge_slot_4_controller_dac_RESET_radio_controller_0_radio4_TX_DAC_RESET
|
---|
767 | PORT user_Tx_gain = radio_bridge_slot_4_user_Tx_gain_radio_controller_0_radio4_TxGain
|
---|
768 | PORT controller_TxStart = radio_bridge_slot_4_controller_TxStart_radio_controller_0_radio4_TxStart
|
---|
769 | PORT controller_SHDN_external = radio_bridge_slot_4_controller_SHDN_external_radio_controller_0_radio4_SHDN_external
|
---|
770 | PORT controller_RxEn_external = radio_bridge_slot_4_controller_RxEn_external_radio_controller_0_radio4_RxEn_external
|
---|
771 | PORT controller_TxEn_external = radio_bridge_slot_4_controller_TxEn_external_radio_controller_0_radio4_TxEn_external
|
---|
772 | PORT controller_RxHP_external = radio_bridge_slot_4_controller_RxHP_external_radio_controller_0_radio4_RxHP_external
|
---|
773 | PORT dac_spi_data = fpga_0_radio_bridge_slot_4_dac_spi_data
|
---|
774 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_4_dac_spi_cs
|
---|
775 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_4_dac_spi_clk
|
---|
776 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_4_radio_spi_clk
|
---|
777 | PORT radio_spi_data = fpga_0_radio_bridge_slot_4_radio_spi_data
|
---|
778 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_4_radio_spi_cs
|
---|
779 | PORT radio_SHDN = fpga_0_radio_bridge_slot_4_radio_SHDN
|
---|
780 | PORT radio_TxEn = fpga_0_radio_bridge_slot_4_radio_TxEn
|
---|
781 | PORT radio_RxEn = fpga_0_radio_bridge_slot_4_radio_RxEn
|
---|
782 | PORT radio_RxHP = fpga_0_radio_bridge_slot_4_radio_RxHP
|
---|
783 | PORT radio_24PA = fpga_0_radio_bridge_slot_4_radio_24PA
|
---|
784 | PORT radio_5PA = fpga_0_radio_bridge_slot_4_radio_5PA
|
---|
785 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_4_radio_ANTSW
|
---|
786 | PORT radio_LED = fpga_0_radio_bridge_slot_4_radio_LED
|
---|
787 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS
|
---|
788 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS
|
---|
789 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA
|
---|
790 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB
|
---|
791 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_4_radio_DIPSW
|
---|
792 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk
|
---|
793 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP
|
---|
794 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ
|
---|
795 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP
|
---|
796 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D
|
---|
797 | PORT radio_LD = fpga_0_radio_bridge_slot_4_radio_LD
|
---|
798 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA
|
---|
799 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB
|
---|
800 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR
|
---|
801 | PORT radio_dac_PLL_LOCK = fpga_0_radio_bridge_slot_4_radio_dac_PLL_LOCK
|
---|
802 | PORT radio_dac_RESET = fpga_0_radio_bridge_slot_4_radio_dac_RESET
|
---|
803 | PORT user_EEPROM_IO_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T
|
---|
804 | PORT user_EEPROM_IO_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O
|
---|
805 | PORT user_EEPROM_IO_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I
|
---|
806 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO
|
---|
807 | PORT user_ADC_I = radio_bridge_slot_4_user_ADC_I
|
---|
808 | PORT user_ADC_Q = radio_bridge_slot_4_user_ADC_Q
|
---|
809 | PORT user_DAC_I = radio_bridge_slot_4_user_DAC_I
|
---|
810 | PORT user_DAC_Q = radio_bridge_slot_4_user_DAC_Q
|
---|
811 | PORT user_TxModelStart = radio4_txStart
|
---|
812 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
813 | PORT user_RSSI_ADC_D = radio_bridge_slot_4_user_RSSI_ADC_D
|
---|
814 | PORT converter_clock_in = clk_40MHz
|
---|
815 | PORT user_RxHP_external = agc_rxhp_d
|
---|
816 | PORT user_RxBB_gain = agc_g_bb_d
|
---|
817 | PORT user_RxRF_gain = agc_g_rf_d
|
---|
818 | END
|
---|
819 |
|
---|
820 | BEGIN isocm_v10
|
---|
821 | PARAMETER INSTANCE = ppc405_0_iocm
|
---|
822 | PARAMETER HW_VER = 2.00.b
|
---|
823 | PARAMETER C_ISCNTLVALUE = 0x85
|
---|
824 | PORT ISOCM_Clk = sys_clk_s
|
---|
825 | PORT sys_rst = sys_bus_reset
|
---|
826 | END
|
---|
827 |
|
---|
828 | BEGIN isbram_if_cntlr
|
---|
829 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr
|
---|
830 | PARAMETER HW_VER = 3.00.b
|
---|
831 | PARAMETER C_BASEADDR = 0xffff0000
|
---|
832 | PARAMETER C_HIGHADDR = 0xffffffff
|
---|
833 | BUS_INTERFACE ISOCM = ppc405_0_iocm
|
---|
834 | BUS_INTERFACE DCR_WRITE_PORT = isocm_porta
|
---|
835 | BUS_INTERFACE INSTRN_READ_PORT = isocm_portb
|
---|
836 | END
|
---|
837 |
|
---|
838 | BEGIN bram_block
|
---|
839 | PARAMETER INSTANCE = isocm_bram
|
---|
840 | PARAMETER HW_VER = 1.00.a
|
---|
841 | BUS_INTERFACE PORTA = isocm_porta
|
---|
842 | BUS_INTERFACE PORTB = isocm_portb
|
---|
843 | END
|
---|
844 |
|
---|
845 | BEGIN dsocm_v10
|
---|
846 | PARAMETER INSTANCE = ppc405_0_docm
|
---|
847 | PARAMETER HW_VER = 2.00.b
|
---|
848 | PARAMETER C_DSCNTLVALUE = 0x85
|
---|
849 | PORT DSOCM_Clk = sys_clk_s
|
---|
850 | PORT sys_rst = sys_bus_reset
|
---|
851 | END
|
---|
852 |
|
---|
853 | BEGIN dsbram_if_cntlr
|
---|
854 | PARAMETER INSTANCE = ppc405_0_docm_cntlr
|
---|
855 | PARAMETER HW_VER = 3.00.b
|
---|
856 | PARAMETER C_BASEADDR = 0x40800000
|
---|
857 | PARAMETER C_HIGHADDR = 0x40807fff
|
---|
858 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
859 | BUS_INTERFACE PORTA = dsocm_porta
|
---|
860 | END
|
---|
861 |
|
---|
862 | BEGIN bram_block
|
---|
863 | PARAMETER INSTANCE = dsocm_bram
|
---|
864 | PARAMETER HW_VER = 1.00.a
|
---|
865 | BUS_INTERFACE PORTA = dsocm_porta
|
---|
866 | END
|
---|
867 |
|
---|
868 | BEGIN clock_generator
|
---|
869 | PARAMETER INSTANCE = clock_generator_0
|
---|
870 | PARAMETER HW_VER = 2.01.a
|
---|
871 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
872 | PARAMETER C_CLKIN_FREQ = 40000000
|
---|
873 | PARAMETER C_CLKOUT0_FREQ = 80000000
|
---|
874 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
875 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
876 | PARAMETER C_CLKOUT0_GROUP = DCM0
|
---|
877 | PARAMETER C_CLKOUT1_FREQ = 240000000
|
---|
878 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
879 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
880 | PARAMETER C_CLKOUT1_GROUP = DCM0
|
---|
881 | PARAMETER C_CLKOUT2_FREQ = 40000000
|
---|
882 | PORT CLKOUT0 = sys_clk_s
|
---|
883 | PORT CLKOUT1 = proc_clk_s
|
---|
884 | PORT CLKOUT2 = clk_40MHz
|
---|
885 | PORT CLKIN = dcm_clk_s
|
---|
886 | PORT LOCKED = Dcm_all_locked
|
---|
887 | PORT RST = clk_board_config_config_invalid
|
---|
888 | END
|
---|
889 |
|
---|
890 | BEGIN proc_sys_reset
|
---|
891 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
892 | PARAMETER HW_VER = 2.00.a
|
---|
893 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
894 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus
|
---|
895 | PORT Slowest_sync_clk = clk_40MHz
|
---|
896 | PORT Dcm_locked = Dcm_all_locked
|
---|
897 | PORT Ext_Reset_In = sys_rst_s
|
---|
898 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
899 | PORT Peripheral_Reset = sys_periph_reset
|
---|
900 | END
|
---|
901 |
|
---|
902 | BEGIN plbv46_plbv46_bridge
|
---|
903 | PARAMETER INSTANCE = plbv46_plbv46_bridge_0
|
---|
904 | PARAMETER HW_VER = 1.01.a
|
---|
905 | PARAMETER C_BUS_CLOCK_RATIO = 2
|
---|
906 | PARAMETER C_NUM_ADDR_RNG = 1
|
---|
907 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000
|
---|
908 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
|
---|
909 | PARAMETER C_RNG0_BASEADDR = 0xc0000000
|
---|
910 | PARAMETER C_RNG0_HIGHADDR = 0xcfffffff
|
---|
911 | BUS_INTERFACE SPLB = plb0
|
---|
912 | BUS_INTERFACE MPLB = plb_32b_40MHz
|
---|
913 | END
|
---|
914 |
|
---|
915 | BEGIN plb_v46
|
---|
916 | PARAMETER INSTANCE = plb_32b_40MHz
|
---|
917 | PARAMETER HW_VER = 1.03.a
|
---|
918 | PORT PLB_Clk = clk_40MHz
|
---|
919 | END
|
---|
920 |
|
---|
921 | BEGIN warplab_mimo_4x4_plbw
|
---|
922 | PARAMETER INSTANCE = warplab_mimo_4x4_plbw_0
|
---|
923 | PARAMETER HW_VER = 1.04.a
|
---|
924 | PARAMETER C_BASEADDR = 0x83800000
|
---|
925 | PARAMETER C_HIGHADDR = 0x83bfffff
|
---|
926 | BUS_INTERFACE SPLB = plb0
|
---|
927 | PORT sysgen_clk = clk_40MHz
|
---|
928 | PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I
|
---|
929 | PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q
|
---|
930 | PORT radio2_adc_i_otr = radio_bridge_slot_2_controller_RX_ADC_OTRA_radio_controller_0_radio2_ADC_RX_OTRA
|
---|
931 | PORT radio2_adc_q_otr = radio_bridge_slot_2_controller_RX_ADC_OTRB_radio_controller_0_radio2_ADC_RX_OTRB
|
---|
932 | PORT startcapture = net_gnd
|
---|
933 | PORT StartTx = net_gnd
|
---|
934 | PORT StopTx = net_gnd
|
---|
935 | PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I
|
---|
936 | PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q
|
---|
937 | PORT rssi_adc_clk = rssi_clk_out
|
---|
938 | PORT debug_capturing = rxrun
|
---|
939 | PORT debug_transmitting = txrun
|
---|
940 | PORT debug_agc_done = agcsetdone
|
---|
941 | PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I
|
---|
942 | PORT radio3_adc_i_otr = radio_bridge_slot_3_controller_RX_ADC_OTRA_radio_controller_0_radio3_ADC_RX_OTRA
|
---|
943 | PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q
|
---|
944 | PORT radio3_adc_q_otr = radio_bridge_slot_3_controller_RX_ADC_OTRB_radio_controller_0_radio3_ADC_RX_OTRB
|
---|
945 | PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I
|
---|
946 | PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q
|
---|
947 | PORT radio4_dac_q = radio_bridge_slot_4_user_DAC_Q
|
---|
948 | PORT radio4_dac_i = radio_bridge_slot_4_user_DAC_I
|
---|
949 | PORT radio1_dac_q = radio_bridge_slot_1_user_DAC_Q
|
---|
950 | PORT radio1_dac_i = radio_bridge_slot_1_user_DAC_I
|
---|
951 | PORT radio4_adc_q_otr = radio_bridge_slot_4_controller_RX_ADC_OTRB_radio_controller_0_radio4_ADC_RX_OTRB
|
---|
952 | PORT radio4_adc_q = radio_bridge_slot_4_user_ADC_Q
|
---|
953 | PORT radio4_adc_i_otr = radio_bridge_slot_4_controller_RX_ADC_OTRA_radio_controller_0_radio4_ADC_RX_OTRA
|
---|
954 | PORT radio4_adc_i = radio_bridge_slot_4_user_ADC_I
|
---|
955 | PORT radio1_adc_q_otr = radio_bridge_slot_1_controller_RX_ADC_OTRB_radio_controller_0_radio1_ADC_RX_OTRB
|
---|
956 | PORT radio1_adc_q = radio_bridge_slot_1_user_ADC_Q
|
---|
957 | PORT radio1_adc_i_otr = radio_bridge_slot_1_controller_RX_ADC_OTRA_radio_controller_0_radio1_ADC_RX_OTRA
|
---|
958 | PORT radio1_adc_i = radio_bridge_slot_1_user_ADC_I
|
---|
959 | PORT radio1_rssi = radio_bridge_slot_1_user_RSSI_ADC_D
|
---|
960 | PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
961 | PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
962 | PORT radio4_rssi = radio_bridge_slot_4_user_RSSI_ADC_D
|
---|
963 | PORT agc_done = agc_is_done
|
---|
964 | PORT fromagc_radio1_i = dc_filtered_i_a
|
---|
965 | PORT fromagc_radio1_q = dc_filtered_q_a
|
---|
966 | PORT fromagc_radio2_i = dc_filtered_i_b
|
---|
967 | PORT fromagc_radio2_q = dc_filtered_q_b
|
---|
968 | PORT fromagc_radio3_i = dc_filtered_i_c
|
---|
969 | PORT fromagc_radio3_q = dc_filtered_q_c
|
---|
970 | PORT fromagc_radio4_i = dc_filtered_i_d
|
---|
971 | PORT fromagc_radio4_q = dc_filtered_q_d
|
---|
972 | END
|
---|
973 |
|
---|
974 | BEGIN warplab_mimo_4x4_agc_plbw
|
---|
975 | PARAMETER INSTANCE = warplab_mimo_4x4_agc_plbw_0
|
---|
976 | PARAMETER HW_VER = 2.00.a
|
---|
977 | PARAMETER C_BASEADDR = 0xc4a00000
|
---|
978 | PARAMETER C_HIGHADDR = 0xc4a0ffff
|
---|
979 | BUS_INTERFACE SPLB = plb_32b_40MHz
|
---|
980 | PORT sysgen_clk = clk_40MHz
|
---|
981 | PORT rxhp_d = agc_rxhp_d
|
---|
982 | PORT rxhp_c = agc_rxhp_c
|
---|
983 | PORT rxhp_b = agc_rxhp_b
|
---|
984 | PORT rxhp_a = agc_rxhp_a
|
---|
985 | PORT g_rf_d = agc_g_rf_d
|
---|
986 | PORT g_rf_c = agc_g_rf_c
|
---|
987 | PORT g_rf_b = agc_g_rf_b
|
---|
988 | PORT g_rf_a = agc_g_rf_a
|
---|
989 | PORT g_bb_d = agc_g_bb_d
|
---|
990 | PORT g_bb_c = agc_g_bb_c
|
---|
991 | PORT g_bb_b = agc_g_bb_b
|
---|
992 | PORT g_bb_a = agc_g_bb_a
|
---|
993 | PORT agc_done = agc_is_done
|
---|
994 | PORT rssi_in_d = radio_bridge_slot_4_user_RSSI_ADC_D
|
---|
995 | PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
996 | PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
997 | PORT rssi_in_a = radio_bridge_slot_1_user_RSSI_ADC_D
|
---|
998 | PORT reset_in = net_gnd
|
---|
999 | PORT q_in_d = radio_bridge_slot_4_user_ADC_Q
|
---|
1000 | PORT q_in_c = radio_bridge_slot_3_user_ADC_Q
|
---|
1001 | PORT q_in_b = radio_bridge_slot_2_user_ADC_Q
|
---|
1002 | PORT q_in_a = radio_bridge_slot_1_user_ADC_Q
|
---|
1003 | PORT packet_in = net_gnd
|
---|
1004 | PORT mreset_in = net_gnd
|
---|
1005 | PORT i_in_d = radio_bridge_slot_4_user_ADC_I
|
---|
1006 | PORT i_in_c = radio_bridge_slot_3_user_ADC_I
|
---|
1007 | PORT i_in_b = radio_bridge_slot_2_user_ADC_I
|
---|
1008 | PORT i_in_a = radio_bridge_slot_1_user_ADC_I
|
---|
1009 | PORT i_out_a = dc_filtered_i_a
|
---|
1010 | PORT i_out_b = dc_filtered_i_b
|
---|
1011 | PORT i_out_c = dc_filtered_i_c
|
---|
1012 | PORT i_out_d = dc_filtered_i_d
|
---|
1013 | PORT q_out_a = dc_filtered_q_a
|
---|
1014 | PORT q_out_b = dc_filtered_q_b
|
---|
1015 | PORT q_out_c = dc_filtered_q_c
|
---|
1016 | PORT q_out_d = dc_filtered_q_d
|
---|
1017 | END
|
---|
1018 |
|
---|
1019 | BEGIN xps_gpio
|
---|
1020 | PARAMETER INSTANCE = debug_sw_gpio
|
---|
1021 | PARAMETER HW_VER = 1.00.a
|
---|
1022 | PARAMETER C_GPIO_WIDTH = 8
|
---|
1023 | PARAMETER C_IS_BIDIR = 0
|
---|
1024 | PARAMETER C_BASEADDR = 0x81400000
|
---|
1025 | PARAMETER C_HIGHADDR = 0x8140ffff
|
---|
1026 | BUS_INTERFACE SPLB = plb0
|
---|
1027 | PORT GPIO_d_out = debug_sw_gpio_O
|
---|
1028 | END
|
---|
1029 |
|
---|
1030 | BEGIN util_flipflop
|
---|
1031 | PARAMETER INSTANCE = util_flipflop_0
|
---|
1032 | PARAMETER HW_VER = 1.10.a
|
---|
1033 | PARAMETER C_USE_RST = 0
|
---|
1034 | PARAMETER C_USE_SET = 0
|
---|
1035 | PARAMETER C_SET_RST_HIGH = 0
|
---|
1036 | PARAMETER C_USE_CE = 0
|
---|
1037 | PARAMETER C_USE_ASYNCH = 0
|
---|
1038 | PARAMETER C_SIZE = 2
|
---|
1039 | PORT Clk = sys_clk_s
|
---|
1040 | PORT D = fpga_0_Ethernet_MAC_PHY_dv & fpga_0_Ethernet_MAC_PHY_tx_en
|
---|
1041 | PORT Q = ff_fpga_0_Ethernet_MAC_PHY_ensigs
|
---|
1042 | END
|
---|
1043 |
|
---|
1044 | BEGIN xps_timer
|
---|
1045 | PARAMETER INSTANCE = xps_timer_0
|
---|
1046 | PARAMETER HW_VER = 1.00.a
|
---|
1047 | PARAMETER C_BASEADDR = 0x83c00000
|
---|
1048 | PARAMETER C_HIGHADDR = 0x83c0ffff
|
---|
1049 | BUS_INTERFACE SPLB = plb0
|
---|
1050 | END
|
---|
1051 |
|
---|