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2 | # ##############################################################################
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3 | # Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
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4 | # Thu Jun 28 08:17:23 2012
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5 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1 (XPS 13 version)
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6 | # Family: virtex4
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7 | # Device: XC4VFX100
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8 | # Package: FF1517
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9 | # Speed Grade: -11
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10 | # Processor number: 1
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11 | # Processor 1: ppc405_0
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12 | # Processor clock frequency: 160.0
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13 | # Bus clock frequency: 80.0
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14 | # Debug Interface: FPGA JTAG
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15 | # ##############################################################################
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16 | PARAMETER VERSION = 2.1.0
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17 |
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18 |
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19 | PORT fpga_0_UserIO_LEDs_out_pin = fpga_0_UserIO_LEDs_out_pin, DIR = O, VEC = [0:7]
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20 | PORT fpga_0_UserIO_IOEx_SDA_pin = fpga_0_UserIO_IOEx_SDA_pin, DIR = O
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21 | PORT fpga_0_UserIO_IOEx_SCL_pin = fpga_0_UserIO_IOEx_SCL_pin, DIR = O
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22 | PORT fpga_0_UserIO_PB_in_pin = fpga_0_UserIO_PB_in_pin, DIR = I, VEC = [0:3]
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23 | PORT fpga_0_UserIO_DIPSW_in_pin = fpga_0_UserIO_DIPSW_in_pin, DIR = I, VEC = [0:3]
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24 | PORT fpga_0_rs232_db9_RX_pin = fpga_0_rs232_db9_RX_pin, DIR = I
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25 | PORT fpga_0_rs232_db9_TX_pin = fpga_0_rs232_db9_TX_pin, DIR = O
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26 | PORT fpga_0_rs232_usb_RX_pin = fpga_0_rs232_usb_RX_pin, DIR = I
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27 | PORT fpga_0_rs232_usb_TX_pin = fpga_0_rs232_usb_TX_pin, DIR = O
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28 | PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin, DIR = O
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29 | PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin, DIR = I
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30 | PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
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31 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin, DIR = O
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32 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin, DIR = O
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33 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin, DIR = O
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34 | PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
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35 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin, DIR = I
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36 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin, DIR = I
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37 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin, DIR = I
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38 | PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0_pin, DIR = O
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39 | PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0_pin, DIR = IO
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40 | PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk_pin, DIR = I
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41 | PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out_pin, DIR = O
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42 | PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out_pin, DIR = O
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43 | PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out_pin, DIR = O
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44 | PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out_pin, DIR = O
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45 | PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out_pin, DIR = O
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46 | PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out_pin, DIR = O
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47 | PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out_pin, DIR = O
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48 | PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out_pin, DIR = O
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49 | PORT fpga_0_radio_bridge_slot_1_converter_clock_out_pin = fpga_0_radio_bridge_slot_1_converter_clock_out_pin, DIR = O
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50 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin, DIR = O
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51 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_I_pin = fpga_0_radio_bridge_slot_1_radio_DAC_I_pin, DIR = O, VEC = [15:0]
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52 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
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53 | PORT fpga_0_radio_bridge_slot_1_radio_ADC_I_pin = fpga_0_radio_bridge_slot_1_radio_ADC_I_pin, DIR = I, VEC = [13:0]
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54 | PORT fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
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55 | PORT fpga_0_radio_bridge_slot_1_radio_B_pin = fpga_0_radio_bridge_slot_1_radio_B_pin, DIR = O, VEC = [6:0]
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56 | PORT fpga_0_radio_bridge_slot_1_radio_ANTSW_pin = fpga_0_radio_bridge_slot_1_radio_ANTSW_pin, DIR = O, VEC = [1:0]
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57 | PORT fpga_0_radio_bridge_slot_1_radio_LED_pin = fpga_0_radio_bridge_slot_1_radio_LED_pin, DIR = O, VEC = [2:0]
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58 | PORT fpga_0_radio_bridge_slot_1_radio_DIPSW_pin = fpga_0_radio_bridge_slot_1_radio_DIPSW_pin, DIR = I, VEC = [3:0]
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59 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
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60 | PORT fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin, DIR = IO
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61 | PORT fpga_0_radio_bridge_slot_1_radio_spi_clk_pin = fpga_0_radio_bridge_slot_1_radio_spi_clk_pin, DIR = O
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62 | PORT fpga_0_radio_bridge_slot_1_radio_spi_data_pin = fpga_0_radio_bridge_slot_1_radio_spi_data_pin, DIR = O
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63 | PORT fpga_0_radio_bridge_slot_1_radio_spi_cs_pin = fpga_0_radio_bridge_slot_1_radio_spi_cs_pin, DIR = O
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64 | PORT fpga_0_radio_bridge_slot_1_radio_SHDN_pin = fpga_0_radio_bridge_slot_1_radio_SHDN_pin, DIR = O
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65 | PORT fpga_0_radio_bridge_slot_1_radio_TxEn_pin = fpga_0_radio_bridge_slot_1_radio_TxEn_pin, DIR = O
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66 | PORT fpga_0_radio_bridge_slot_1_radio_RxEn_pin = fpga_0_radio_bridge_slot_1_radio_RxEn_pin, DIR = O
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67 | PORT fpga_0_radio_bridge_slot_1_radio_RxHP_pin = fpga_0_radio_bridge_slot_1_radio_RxHP_pin, DIR = O
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68 | PORT fpga_0_radio_bridge_slot_1_radio_24PA_pin = fpga_0_radio_bridge_slot_1_radio_24PA_pin, DIR = O
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69 | PORT fpga_0_radio_bridge_slot_1_radio_5PA_pin = fpga_0_radio_bridge_slot_1_radio_5PA_pin, DIR = O
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70 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin, DIR = O
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71 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin, DIR = O
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72 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin, DIR = O
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73 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin, DIR = O
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74 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin, DIR = O
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75 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin, DIR = O
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76 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin, DIR = O
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77 | PORT fpga_0_radio_bridge_slot_1_radio_LD_pin = fpga_0_radio_bridge_slot_1_radio_LD_pin, DIR = I
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78 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin, DIR = I
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79 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin, DIR = I
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80 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin, DIR = I
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81 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin, DIR = I
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82 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin, DIR = O
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83 | PORT fpga_0_radio_bridge_slot_1_dac_spi_data_pin = fpga_0_radio_bridge_slot_1_dac_spi_data_pin, DIR = O
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84 | PORT fpga_0_radio_bridge_slot_1_dac_spi_cs_pin = fpga_0_radio_bridge_slot_1_dac_spi_cs_pin, DIR = O
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85 | PORT fpga_0_radio_bridge_slot_1_dac_spi_clk_pin = fpga_0_radio_bridge_slot_1_dac_spi_clk_pin, DIR = O
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86 | PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out_pin, DIR = O
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87 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin, DIR = O
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88 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin, DIR = O, VEC = [15:0]
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89 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
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90 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin, DIR = I, VEC = [13:0]
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91 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
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92 | PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B_pin, DIR = O, VEC = [6:0]
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93 | PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin, DIR = O, VEC = [1:0]
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94 | PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED_pin, DIR = O, VEC = [2:0]
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95 | PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin, DIR = I, VEC = [3:0]
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96 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
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97 | PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin, DIR = IO
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98 | PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin, DIR = O
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99 | PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data_pin, DIR = O
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100 | PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin, DIR = O
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101 | PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN_pin, DIR = O
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102 | PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn_pin, DIR = O
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103 | PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn_pin, DIR = O
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104 | PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP_pin, DIR = O
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105 | PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA_pin, DIR = O
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106 | PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA_pin, DIR = O
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107 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin, DIR = O
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108 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin, DIR = O
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109 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin, DIR = O
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110 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin, DIR = O
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111 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin, DIR = O
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112 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin, DIR = O
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113 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin, DIR = O
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114 | PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD_pin, DIR = I
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115 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin, DIR = I
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116 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin, DIR = I
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117 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin, DIR = I
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118 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin, DIR = I
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119 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin, DIR = O
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120 | PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data_pin, DIR = O
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121 | PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin, DIR = O
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122 | PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin, DIR = O
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123 | PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out_pin, DIR = O
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124 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin, DIR = O
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125 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin, DIR = O, VEC = [15:0]
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126 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
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127 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin, DIR = I, VEC = [13:0]
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128 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
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129 | PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B_pin, DIR = O, VEC = [6:0]
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130 | PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin, DIR = O, VEC = [1:0]
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131 | PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED_pin, DIR = O, VEC = [2:0]
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132 | PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin, DIR = I, VEC = [3:0]
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133 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
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134 | PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin, DIR = IO
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135 | PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin, DIR = O
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136 | PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data_pin, DIR = O
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137 | PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin, DIR = O
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138 | PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN_pin, DIR = O
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139 | PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn_pin, DIR = O
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140 | PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn_pin, DIR = O
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141 | PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP_pin, DIR = O
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142 | PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA_pin, DIR = O
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143 | PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA_pin, DIR = O
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144 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin, DIR = O
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145 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin, DIR = O
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146 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin, DIR = O
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147 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin, DIR = O
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148 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin, DIR = O
|
---|
149 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin, DIR = O
|
---|
150 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin, DIR = O
|
---|
151 | PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD_pin, DIR = I
|
---|
152 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin, DIR = I
|
---|
153 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin, DIR = I
|
---|
154 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin, DIR = I
|
---|
155 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin, DIR = I
|
---|
156 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin, DIR = O
|
---|
157 | PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data_pin, DIR = O
|
---|
158 | PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin, DIR = O
|
---|
159 | PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin, DIR = O
|
---|
160 | PORT fpga_0_radio_bridge_slot_4_converter_clock_out_pin = fpga_0_radio_bridge_slot_4_converter_clock_out_pin, DIR = O
|
---|
161 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin, DIR = O
|
---|
162 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_I_pin = fpga_0_radio_bridge_slot_4_radio_DAC_I_pin, DIR = O, VEC = [15:0]
|
---|
163 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
|
---|
164 | PORT fpga_0_radio_bridge_slot_4_radio_ADC_I_pin = fpga_0_radio_bridge_slot_4_radio_ADC_I_pin, DIR = I, VEC = [13:0]
|
---|
165 | PORT fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
|
---|
166 | PORT fpga_0_radio_bridge_slot_4_radio_B_pin = fpga_0_radio_bridge_slot_4_radio_B_pin, DIR = O, VEC = [6:0]
|
---|
167 | PORT fpga_0_radio_bridge_slot_4_radio_ANTSW_pin = fpga_0_radio_bridge_slot_4_radio_ANTSW_pin, DIR = O, VEC = [1:0]
|
---|
168 | PORT fpga_0_radio_bridge_slot_4_radio_LED_pin = fpga_0_radio_bridge_slot_4_radio_LED_pin, DIR = O, VEC = [2:0]
|
---|
169 | PORT fpga_0_radio_bridge_slot_4_radio_DIPSW_pin = fpga_0_radio_bridge_slot_4_radio_DIPSW_pin, DIR = I, VEC = [3:0]
|
---|
170 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
|
---|
171 | PORT fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin, DIR = IO
|
---|
172 | PORT fpga_0_radio_bridge_slot_4_radio_spi_clk_pin = fpga_0_radio_bridge_slot_4_radio_spi_clk_pin, DIR = O
|
---|
173 | PORT fpga_0_radio_bridge_slot_4_radio_spi_data_pin = fpga_0_radio_bridge_slot_4_radio_spi_data_pin, DIR = O
|
---|
174 | PORT fpga_0_radio_bridge_slot_4_radio_spi_cs_pin = fpga_0_radio_bridge_slot_4_radio_spi_cs_pin, DIR = O
|
---|
175 | PORT fpga_0_radio_bridge_slot_4_radio_SHDN_pin = fpga_0_radio_bridge_slot_4_radio_SHDN_pin, DIR = O
|
---|
176 | PORT fpga_0_radio_bridge_slot_4_radio_TxEn_pin = fpga_0_radio_bridge_slot_4_radio_TxEn_pin, DIR = O
|
---|
177 | PORT fpga_0_radio_bridge_slot_4_radio_RxEn_pin = fpga_0_radio_bridge_slot_4_radio_RxEn_pin, DIR = O
|
---|
178 | PORT fpga_0_radio_bridge_slot_4_radio_RxHP_pin = fpga_0_radio_bridge_slot_4_radio_RxHP_pin, DIR = O
|
---|
179 | PORT fpga_0_radio_bridge_slot_4_radio_24PA_pin = fpga_0_radio_bridge_slot_4_radio_24PA_pin, DIR = O
|
---|
180 | PORT fpga_0_radio_bridge_slot_4_radio_5PA_pin = fpga_0_radio_bridge_slot_4_radio_5PA_pin, DIR = O
|
---|
181 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin, DIR = O
|
---|
182 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin, DIR = O
|
---|
183 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin, DIR = O
|
---|
184 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin, DIR = O
|
---|
185 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin, DIR = O
|
---|
186 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin, DIR = O
|
---|
187 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin, DIR = O
|
---|
188 | PORT fpga_0_radio_bridge_slot_4_radio_LD_pin = fpga_0_radio_bridge_slot_4_radio_LD_pin, DIR = I
|
---|
189 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin, DIR = I
|
---|
190 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin, DIR = I
|
---|
191 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin, DIR = I
|
---|
192 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin, DIR = I
|
---|
193 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin, DIR = O
|
---|
194 | PORT fpga_0_radio_bridge_slot_4_dac_spi_data_pin = fpga_0_radio_bridge_slot_4_dac_spi_data_pin, DIR = O
|
---|
195 | PORT fpga_0_radio_bridge_slot_4_dac_spi_cs_pin = fpga_0_radio_bridge_slot_4_dac_spi_cs_pin, DIR = O
|
---|
196 | PORT fpga_0_radio_bridge_slot_4_dac_spi_clk_pin = fpga_0_radio_bridge_slot_4_dac_spi_clk_pin, DIR = O
|
---|
197 | PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0_pin, DIR = IO
|
---|
198 | PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
|
---|
199 | PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
|
---|
200 |
|
---|
201 |
|
---|
202 | BEGIN ppc405_virtex4
|
---|
203 | PARAMETER INSTANCE = ppc405_0
|
---|
204 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
|
---|
205 | PARAMETER C_IDCR_BASEADDR = 0b0100000000
|
---|
206 | PARAMETER C_IDCR_HIGHADDR = 0b0111111111
|
---|
207 | PARAMETER HW_VER = 2.01.b
|
---|
208 | BUS_INTERFACE DPLB0 = plb
|
---|
209 | BUS_INTERFACE IPLB0 = plb
|
---|
210 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
211 | BUS_INTERFACE ISOCM = ppc405_0_iocm
|
---|
212 | BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
|
---|
213 | BUS_INTERFACE RESETPPC = ppc_reset_bus
|
---|
214 | PORT CPMC405CLOCK = clk_160_0000MHzDCM0
|
---|
215 | END
|
---|
216 |
|
---|
217 | BEGIN isocm_v10
|
---|
218 | PARAMETER INSTANCE = ppc405_0_iocm
|
---|
219 | PARAMETER C_ISCNTLVALUE = 0xa3
|
---|
220 | PARAMETER HW_VER = 2.00.b
|
---|
221 | PORT ISOCM_Clk = clk_80_0000MHzDCM0
|
---|
222 | PORT SYS_Rst = sys_bus_reset
|
---|
223 | END
|
---|
224 |
|
---|
225 | BEGIN isbram_if_cntlr
|
---|
226 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr
|
---|
227 | PARAMETER HW_VER = 3.00.c
|
---|
228 | PARAMETER C_BASEADDR = 0xffff0000
|
---|
229 | PARAMETER C_HIGHADDR = 0xffffffff
|
---|
230 | BUS_INTERFACE ISOCM = ppc405_0_iocm
|
---|
231 | BUS_INTERFACE DCR_WRITE_PORT = ppc405_0_iocm_cntlr_porta
|
---|
232 | BUS_INTERFACE INSTRN_READ_PORT = ppc405_0_iocm_cntlr_portb
|
---|
233 | END
|
---|
234 |
|
---|
235 | BEGIN bram_block
|
---|
236 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr_bram
|
---|
237 | PARAMETER HW_VER = 1.00.a
|
---|
238 | BUS_INTERFACE PORTA = ppc405_0_iocm_cntlr_porta
|
---|
239 | BUS_INTERFACE PORTB = ppc405_0_iocm_cntlr_portb
|
---|
240 | END
|
---|
241 |
|
---|
242 | BEGIN dsocm_v10
|
---|
243 | PARAMETER INSTANCE = ppc405_0_docm
|
---|
244 | PARAMETER C_DSCNTLVALUE = 0xa3
|
---|
245 | PARAMETER HW_VER = 2.00.b
|
---|
246 | PORT DSOCM_Clk = clk_80_0000MHzDCM0
|
---|
247 | PORT SYS_Rst = sys_bus_reset
|
---|
248 | END
|
---|
249 |
|
---|
250 | BEGIN dsbram_if_cntlr
|
---|
251 | PARAMETER INSTANCE = ppc405_0_docm_cntlr
|
---|
252 | PARAMETER HW_VER = 3.00.c
|
---|
253 | PARAMETER C_BASEADDR = 0x40110000
|
---|
254 | PARAMETER C_HIGHADDR = 0x4011ffff
|
---|
255 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
256 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
257 | END
|
---|
258 |
|
---|
259 | BEGIN bram_block
|
---|
260 | PARAMETER INSTANCE = ppc405_0_docm_cntlr_bram
|
---|
261 | PARAMETER HW_VER = 1.00.a
|
---|
262 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
263 | END
|
---|
264 |
|
---|
265 | BEGIN plb_v46
|
---|
266 | PARAMETER INSTANCE = plb
|
---|
267 | PARAMETER C_DCR_INTFCE = 0
|
---|
268 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
269 | PARAMETER HW_VER = 1.05.a
|
---|
270 | PORT PLB_Clk = clk_80_0000MHzDCM0
|
---|
271 | PORT SYS_Rst = sys_bus_reset
|
---|
272 | END
|
---|
273 |
|
---|
274 | BEGIN xps_bram_if_cntlr
|
---|
275 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
---|
276 | PARAMETER C_SPLB_NATIVE_DWIDTH = 64
|
---|
277 | PARAMETER HW_VER = 1.00.b
|
---|
278 | PARAMETER C_BASEADDR = 0x00000000
|
---|
279 | PARAMETER C_HIGHADDR = 0x0000ffff
|
---|
280 | BUS_INTERFACE SPLB = plb
|
---|
281 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
282 | END
|
---|
283 |
|
---|
284 | BEGIN bram_block
|
---|
285 | PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
|
---|
286 | PARAMETER HW_VER = 1.00.a
|
---|
287 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
288 | END
|
---|
289 |
|
---|
290 | BEGIN warp_v4_userio
|
---|
291 | PARAMETER INSTANCE = UserIO
|
---|
292 | PARAMETER C_ADDRESS_0 = 0x40
|
---|
293 | PARAMETER C_ADDRESS_1 = 0x42
|
---|
294 | PARAMETER C_I2C_DIVIDER = 0x40
|
---|
295 | PARAMETER HW_VER = 1.00.a
|
---|
296 | PARAMETER C_BASEADDR = 0xc9600000
|
---|
297 | PARAMETER C_HIGHADDR = 0xc960ffff
|
---|
298 | BUS_INTERFACE SPLB = plb
|
---|
299 | PORT LEDs_out = fpga_0_UserIO_LEDs_out_pin
|
---|
300 | PORT IOEx_SDA = fpga_0_UserIO_IOEx_SDA_pin
|
---|
301 | PORT IOEx_SCL = fpga_0_UserIO_IOEx_SCL_pin
|
---|
302 | PORT PB_in = fpga_0_UserIO_PB_in_pin
|
---|
303 | PORT DIPSW_in = fpga_0_UserIO_DIPSW_in_pin
|
---|
304 | END
|
---|
305 |
|
---|
306 | BEGIN xps_uartlite
|
---|
307 | PARAMETER INSTANCE = rs232_db9
|
---|
308 | PARAMETER C_BAUDRATE = 57600
|
---|
309 | PARAMETER C_DATA_BITS = 8
|
---|
310 | PARAMETER C_USE_PARITY = 0
|
---|
311 | PARAMETER C_ODD_PARITY = 0
|
---|
312 | PARAMETER HW_VER = 1.02.a
|
---|
313 | PARAMETER C_BASEADDR = 0x84020000
|
---|
314 | PARAMETER C_HIGHADDR = 0x8402ffff
|
---|
315 | BUS_INTERFACE SPLB = plb
|
---|
316 | PORT RX = fpga_0_rs232_db9_RX_pin
|
---|
317 | PORT TX = fpga_0_rs232_db9_TX_pin
|
---|
318 | END
|
---|
319 |
|
---|
320 | BEGIN xps_uartlite
|
---|
321 | PARAMETER INSTANCE = rs232_usb
|
---|
322 | PARAMETER C_BAUDRATE = 57600
|
---|
323 | PARAMETER C_DATA_BITS = 8
|
---|
324 | PARAMETER C_USE_PARITY = 0
|
---|
325 | PARAMETER C_ODD_PARITY = 0
|
---|
326 | PARAMETER HW_VER = 1.02.a
|
---|
327 | PARAMETER C_BASEADDR = 0x84000000
|
---|
328 | PARAMETER C_HIGHADDR = 0x8400ffff
|
---|
329 | BUS_INTERFACE SPLB = plb
|
---|
330 | PORT RX = fpga_0_rs232_usb_RX_pin
|
---|
331 | PORT TX = fpga_0_rs232_usb_TX_pin
|
---|
332 | END
|
---|
333 |
|
---|
334 | BEGIN xps_ll_temac
|
---|
335 | PARAMETER INSTANCE = TriMode_MAC_GMII
|
---|
336 | PARAMETER C_NUM_IDELAYCTRL = 2
|
---|
337 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
|
---|
338 | PARAMETER C_PHY_TYPE = 1
|
---|
339 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
340 | PARAMETER C_TEMAC_TYPE = 1
|
---|
341 | PARAMETER HW_VER = 2.03.a
|
---|
342 | PARAMETER C_BASEADDR = 0x87000000
|
---|
343 | PARAMETER C_HIGHADDR = 0x8707ffff
|
---|
344 | BUS_INTERFACE SPLB = plb
|
---|
345 | BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_llink0
|
---|
346 | PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
|
---|
347 | PORT GTX_CLK_0 = clk_125_0000MHz
|
---|
348 | PORT REFCLK = clk_200_0000MHz
|
---|
349 | PORT LlinkTemac0_CLK = clk_80_0000MHzDCM0
|
---|
350 | PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
|
---|
351 | PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
|
---|
352 | PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
|
---|
353 | PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
|
---|
354 | PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
|
---|
355 | PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
|
---|
356 | PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
|
---|
357 | PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
|
---|
358 | PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
|
---|
359 | PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0_pin
|
---|
360 | PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0_pin
|
---|
361 | END
|
---|
362 |
|
---|
363 | BEGIN clock_board_config
|
---|
364 | PARAMETER INSTANCE = clk_board_config
|
---|
365 | PARAMETER HW_VER = 1.05.a
|
---|
366 | PORT sys_clk = fpga_0_clk_board_config_sys_clk_pin
|
---|
367 | PORT sys_rst = net_gnd
|
---|
368 | PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out_pin
|
---|
369 | PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out_pin
|
---|
370 | PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out_pin
|
---|
371 | PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out_pin
|
---|
372 | PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out_pin
|
---|
373 | PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out_pin
|
---|
374 | PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out_pin
|
---|
375 | PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out_pin
|
---|
376 | PORT radio_clk_src_sel = net_gnd
|
---|
377 | PORT logic_clk_src_sel = net_gnd
|
---|
378 | PORT config_invalid = clk_board_config_config_invalid
|
---|
379 | END
|
---|
380 |
|
---|
381 | BEGIN radio_controller
|
---|
382 | PARAMETER INSTANCE = radio_controller_0
|
---|
383 | PARAMETER HW_VER = 1.30.a
|
---|
384 | PARAMETER C_BASEADDR = 0xcac00000
|
---|
385 | PARAMETER C_HIGHADDR = 0xcac0ffff
|
---|
386 | BUS_INTERFACE SPLB = plb_v46_40MHz
|
---|
387 | BUS_INTERFACE RC2RB_RAD1 = radio_controller_0_RC2RB_RAD1
|
---|
388 | BUS_INTERFACE RC2RB_RAD2 = radio_controller_0_RC2RB_RAD2
|
---|
389 | BUS_INTERFACE RC2RB_RAD3 = radio_controller_0_RC2RB_RAD3
|
---|
390 | BUS_INTERFACE RC2RB_RAD4 = radio_controller_0_RC2RB_RAD4
|
---|
391 | END
|
---|
392 |
|
---|
393 | BEGIN radio_bridge
|
---|
394 | PARAMETER INSTANCE = radio_bridge_slot_1
|
---|
395 | PARAMETER HW_VER = 1.30.a
|
---|
396 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD1
|
---|
397 | PORT converter_clock_in = clk_40_0000MHz
|
---|
398 | PORT converter_clock_out = fpga_0_radio_bridge_slot_1_converter_clock_out_pin
|
---|
399 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin
|
---|
400 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_1_radio_DAC_I_pin
|
---|
401 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin
|
---|
402 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_1_radio_ADC_I_pin
|
---|
403 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin
|
---|
404 | PORT radio_B = fpga_0_radio_bridge_slot_1_radio_B_pin
|
---|
405 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_1_radio_ANTSW_pin
|
---|
406 | PORT radio_LED = fpga_0_radio_bridge_slot_1_radio_LED_pin
|
---|
407 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_1_radio_DIPSW_pin
|
---|
408 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin
|
---|
409 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin
|
---|
410 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_1_radio_spi_clk_pin
|
---|
411 | PORT radio_spi_data = fpga_0_radio_bridge_slot_1_radio_spi_data_pin
|
---|
412 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_1_radio_spi_cs_pin
|
---|
413 | PORT radio_SHDN = fpga_0_radio_bridge_slot_1_radio_SHDN_pin
|
---|
414 | PORT radio_TxEn = fpga_0_radio_bridge_slot_1_radio_TxEn_pin
|
---|
415 | PORT radio_RxEn = fpga_0_radio_bridge_slot_1_radio_RxEn_pin
|
---|
416 | PORT radio_RxHP = fpga_0_radio_bridge_slot_1_radio_RxHP_pin
|
---|
417 | PORT radio_24PA = fpga_0_radio_bridge_slot_1_radio_24PA_pin
|
---|
418 | PORT radio_5PA = fpga_0_radio_bridge_slot_1_radio_5PA_pin
|
---|
419 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin
|
---|
420 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin
|
---|
421 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin
|
---|
422 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin
|
---|
423 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin
|
---|
424 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin
|
---|
425 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin
|
---|
426 | PORT radio_LD = fpga_0_radio_bridge_slot_1_radio_LD_pin
|
---|
427 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin
|
---|
428 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin
|
---|
429 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin
|
---|
430 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin
|
---|
431 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin
|
---|
432 | PORT dac_spi_data = fpga_0_radio_bridge_slot_1_dac_spi_data_pin
|
---|
433 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_1_dac_spi_cs_pin
|
---|
434 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_1_dac_spi_clk_pin
|
---|
435 | PORT user_EEPROM_IO_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T
|
---|
436 | PORT user_EEPROM_IO_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O
|
---|
437 | PORT user_EEPROM_IO_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I
|
---|
438 | PORT user_ADC_I = radio_bridge_slot_1_user_ADC_I
|
---|
439 | PORT user_ADC_Q = radio_bridge_slot_1_user_ADC_Q
|
---|
440 | PORT user_DAC_I = radio_bridge_slot_1_user_DAC_I
|
---|
441 | PORT user_DAC_Q = radio_bridge_slot_1_user_DAC_Q
|
---|
442 | PORT user_TxModelStart = radio1_txStart
|
---|
443 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
444 | PORT user_RSSI_ADC_D = radio_bridge_slot_1_user_RSSI_ADC_D
|
---|
445 | PORT user_RxHP_external = agc_rxhp_a
|
---|
446 | PORT user_RxBB_gain = agc_g_bb_a
|
---|
447 | PORT user_RxRF_gain = agc_g_rf_a
|
---|
448 | END
|
---|
449 |
|
---|
450 | BEGIN radio_bridge
|
---|
451 | PARAMETER INSTANCE = radio_bridge_slot_2
|
---|
452 | PARAMETER HW_VER = 1.30.a
|
---|
453 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD2
|
---|
454 | PORT converter_clock_in = clk_40_0000MHz
|
---|
455 | PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out_pin
|
---|
456 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
|
---|
457 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
|
---|
458 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
|
---|
459 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
|
---|
460 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
|
---|
461 | PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B_pin
|
---|
462 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
|
---|
463 | PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED_pin
|
---|
464 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
|
---|
465 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
|
---|
466 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
|
---|
467 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
|
---|
468 | PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data_pin
|
---|
469 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
|
---|
470 | PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN_pin
|
---|
471 | PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn_pin
|
---|
472 | PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn_pin
|
---|
473 | PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP_pin
|
---|
474 | PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA_pin
|
---|
475 | PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA_pin
|
---|
476 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
|
---|
477 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
|
---|
478 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
|
---|
479 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
|
---|
480 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
|
---|
481 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
|
---|
482 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
|
---|
483 | PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD_pin
|
---|
484 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
|
---|
485 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
|
---|
486 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
|
---|
487 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
|
---|
488 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
|
---|
489 | PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data_pin
|
---|
490 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
|
---|
491 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
|
---|
492 | PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
|
---|
493 | PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
|
---|
494 | PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
|
---|
495 | PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I
|
---|
496 | PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q
|
---|
497 | PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I
|
---|
498 | PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q
|
---|
499 | PORT user_TxModelStart = radio2_txStart
|
---|
500 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
501 | PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
502 | PORT user_RxHP_external = agc_rxhp_b
|
---|
503 | PORT user_RxBB_gain = agc_g_bb_b
|
---|
504 | PORT user_RxRF_gain = agc_g_rf_b
|
---|
505 | END
|
---|
506 |
|
---|
507 | BEGIN radio_bridge
|
---|
508 | PARAMETER INSTANCE = radio_bridge_slot_3
|
---|
509 | PARAMETER HW_VER = 1.30.a
|
---|
510 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD3
|
---|
511 | PORT converter_clock_in = clk_40_0000MHz
|
---|
512 | PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out_pin
|
---|
513 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
|
---|
514 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
|
---|
515 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
|
---|
516 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
|
---|
517 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
|
---|
518 | PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B_pin
|
---|
519 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
|
---|
520 | PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED_pin
|
---|
521 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
|
---|
522 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
|
---|
523 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
|
---|
524 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
|
---|
525 | PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data_pin
|
---|
526 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
|
---|
527 | PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN_pin
|
---|
528 | PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn_pin
|
---|
529 | PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn_pin
|
---|
530 | PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP_pin
|
---|
531 | PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA_pin
|
---|
532 | PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA_pin
|
---|
533 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
|
---|
534 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
|
---|
535 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
|
---|
536 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
|
---|
537 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
|
---|
538 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
|
---|
539 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
|
---|
540 | PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD_pin
|
---|
541 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
|
---|
542 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
|
---|
543 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
|
---|
544 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
|
---|
545 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
|
---|
546 | PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data_pin
|
---|
547 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
|
---|
548 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
|
---|
549 | PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
|
---|
550 | PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
|
---|
551 | PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
|
---|
552 | PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I
|
---|
553 | PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q
|
---|
554 | PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I
|
---|
555 | PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q
|
---|
556 | PORT user_TxModelStart = radio3_txStart
|
---|
557 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
558 | PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
559 | PORT user_RxHP_external = agc_rxhp_c
|
---|
560 | PORT user_RxBB_gain = agc_g_bb_c
|
---|
561 | PORT user_RxRF_gain = agc_g_rf_c
|
---|
562 | END
|
---|
563 |
|
---|
564 | BEGIN radio_bridge
|
---|
565 | PARAMETER INSTANCE = radio_bridge_slot_4
|
---|
566 | PARAMETER HW_VER = 1.30.a
|
---|
567 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD4
|
---|
568 | PORT converter_clock_in = clk_40_0000MHz
|
---|
569 | PORT converter_clock_out = fpga_0_radio_bridge_slot_4_converter_clock_out_pin
|
---|
570 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin
|
---|
571 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_4_radio_DAC_I_pin
|
---|
572 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin
|
---|
573 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_4_radio_ADC_I_pin
|
---|
574 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin
|
---|
575 | PORT radio_B = fpga_0_radio_bridge_slot_4_radio_B_pin
|
---|
576 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_4_radio_ANTSW_pin
|
---|
577 | PORT radio_LED = fpga_0_radio_bridge_slot_4_radio_LED_pin
|
---|
578 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_4_radio_DIPSW_pin
|
---|
579 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin
|
---|
580 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin
|
---|
581 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_4_radio_spi_clk_pin
|
---|
582 | PORT radio_spi_data = fpga_0_radio_bridge_slot_4_radio_spi_data_pin
|
---|
583 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_4_radio_spi_cs_pin
|
---|
584 | PORT radio_SHDN = fpga_0_radio_bridge_slot_4_radio_SHDN_pin
|
---|
585 | PORT radio_TxEn = fpga_0_radio_bridge_slot_4_radio_TxEn_pin
|
---|
586 | PORT radio_RxEn = fpga_0_radio_bridge_slot_4_radio_RxEn_pin
|
---|
587 | PORT radio_RxHP = fpga_0_radio_bridge_slot_4_radio_RxHP_pin
|
---|
588 | PORT radio_24PA = fpga_0_radio_bridge_slot_4_radio_24PA_pin
|
---|
589 | PORT radio_5PA = fpga_0_radio_bridge_slot_4_radio_5PA_pin
|
---|
590 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin
|
---|
591 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin
|
---|
592 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin
|
---|
593 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin
|
---|
594 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin
|
---|
595 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin
|
---|
596 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin
|
---|
597 | PORT radio_LD = fpga_0_radio_bridge_slot_4_radio_LD_pin
|
---|
598 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin
|
---|
599 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin
|
---|
600 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin
|
---|
601 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin
|
---|
602 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin
|
---|
603 | PORT dac_spi_data = fpga_0_radio_bridge_slot_4_dac_spi_data_pin
|
---|
604 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_4_dac_spi_cs_pin
|
---|
605 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_4_dac_spi_clk_pin
|
---|
606 | PORT user_EEPROM_IO_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T
|
---|
607 | PORT user_EEPROM_IO_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O
|
---|
608 | PORT user_EEPROM_IO_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I
|
---|
609 | PORT user_ADC_I = radio_bridge_slot_4_user_ADC_I
|
---|
610 | PORT user_ADC_Q = radio_bridge_slot_4_user_ADC_Q
|
---|
611 | PORT user_DAC_I = radio_bridge_slot_4_user_DAC_I
|
---|
612 | PORT user_DAC_Q = radio_bridge_slot_4_user_DAC_Q
|
---|
613 | PORT user_TxModelStart = radio4_txStart
|
---|
614 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
615 | PORT user_RSSI_ADC_D = radio_bridge_slot_4_user_RSSI_ADC_D
|
---|
616 | PORT user_RxHP_external = agc_rxhp_d
|
---|
617 | PORT user_RxBB_gain = agc_g_bb_d
|
---|
618 | PORT user_RxRF_gain = agc_g_rf_d
|
---|
619 | END
|
---|
620 |
|
---|
621 | BEGIN eeprom_onewire
|
---|
622 | PARAMETER INSTANCE = eeprom_controller
|
---|
623 | PARAMETER HW_VER = 1.10.a
|
---|
624 | PARAMETER C_MEM0_BASEADDR = 0xc5400000
|
---|
625 | PARAMETER C_MEM0_HIGHADDR = 0xc540ffff
|
---|
626 | BUS_INTERFACE SPLB = plb
|
---|
627 | PORT DQ0 = fpga_0_eeprom_controller_DQ0_pin
|
---|
628 | PORT DQ1_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T
|
---|
629 | PORT DQ1_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O
|
---|
630 | PORT DQ1_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I
|
---|
631 | PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
|
---|
632 | PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
|
---|
633 | PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
|
---|
634 | PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
|
---|
635 | PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
|
---|
636 | PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
|
---|
637 | PORT DQ4_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T
|
---|
638 | PORT DQ4_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O
|
---|
639 | PORT DQ4_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I
|
---|
640 | PORT DQ5_I = net_vcc
|
---|
641 | PORT DQ6_I = net_vcc
|
---|
642 | PORT DQ7_I = net_vcc
|
---|
643 | END
|
---|
644 |
|
---|
645 | BEGIN xps_ll_fifo
|
---|
646 | PARAMETER INSTANCE = TriMode_MAC_GMII_fifo
|
---|
647 | PARAMETER HW_VER = 1.02.a
|
---|
648 | PARAMETER C_BASEADDR = 0x81a00000
|
---|
649 | PARAMETER C_HIGHADDR = 0x81a0ffff
|
---|
650 | BUS_INTERFACE SPLB = plb
|
---|
651 | BUS_INTERFACE LLINK = TriMode_MAC_GMII_llink0
|
---|
652 | END
|
---|
653 |
|
---|
654 | BEGIN clock_generator
|
---|
655 | PARAMETER INSTANCE = clock_generator_0
|
---|
656 | PARAMETER C_CLKIN_FREQ = 40000000
|
---|
657 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
658 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
659 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
660 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
661 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
662 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
663 | PARAMETER C_CLKOUT1_GROUP = DCM0
|
---|
664 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
665 | PARAMETER C_CLKOUT2_FREQ = 200000000
|
---|
666 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
667 | PARAMETER C_CLKOUT2_GROUP = NONE
|
---|
668 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
669 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
670 | PARAMETER C_CLKOUT3_PHASE = 0
|
---|
671 | PARAMETER C_CLKOUT3_GROUP = NONE
|
---|
672 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
673 | PARAMETER C_CLKOUT4_FREQ = 80000000
|
---|
674 | PARAMETER C_CLKOUT4_PHASE = 0
|
---|
675 | PARAMETER C_CLKOUT4_GROUP = DCM0
|
---|
676 | PARAMETER C_CLKOUT4_BUF = TRUE
|
---|
677 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
678 | PARAMETER HW_VER = 4.03.a
|
---|
679 | PORT CLKIN = CLK_S
|
---|
680 | PORT CLKOUT0 = clk_125_0000MHz
|
---|
681 | PORT CLKOUT1 = clk_160_0000MHzDCM0
|
---|
682 | PORT CLKOUT2 = clk_200_0000MHz
|
---|
683 | PORT CLKOUT3 = clk_40_0000MHz
|
---|
684 | PORT CLKOUT4 = clk_80_0000MHzDCM0
|
---|
685 | PORT RST = clk_board_config_config_invalid
|
---|
686 | PORT LOCKED = Dcm_all_locked
|
---|
687 | END
|
---|
688 |
|
---|
689 | BEGIN jtagppc_cntlr
|
---|
690 | PARAMETER INSTANCE = jtagppc_cntlr_inst
|
---|
691 | PARAMETER HW_VER = 2.01.c
|
---|
692 | BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
|
---|
693 | END
|
---|
694 |
|
---|
695 | BEGIN proc_sys_reset
|
---|
696 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
697 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
698 | PARAMETER HW_VER = 3.00.a
|
---|
699 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus
|
---|
700 | PORT Slowest_sync_clk = clk_40_0000MHz
|
---|
701 | PORT Ext_Reset_In = sys_rst_s
|
---|
702 | PORT Dcm_locked = Dcm_all_locked
|
---|
703 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
704 | PORT Peripheral_Reset = sys_periph_reset
|
---|
705 | END
|
---|
706 |
|
---|
707 | BEGIN plb_v46
|
---|
708 | PARAMETER INSTANCE = plb_v46_40MHz
|
---|
709 | PARAMETER C_DCR_INTFCE = 0
|
---|
710 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
711 | PARAMETER HW_VER = 1.05.a
|
---|
712 | PORT PLB_Clk = clk_40_0000MHz
|
---|
713 | PORT SYS_Rst = sys_bus_reset
|
---|
714 | END
|
---|
715 |
|
---|
716 | BEGIN plbv46_plbv46_bridge
|
---|
717 | PARAMETER INSTANCE = plbv46_plbv46_bridge_0
|
---|
718 | PARAMETER HW_VER = 1.04.a
|
---|
719 | PARAMETER C_BUS_CLOCK_RATIO = 2
|
---|
720 | PARAMETER C_NUM_ADDR_RNG = 2
|
---|
721 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000
|
---|
722 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
|
---|
723 | PARAMETER C_RNG0_BASEADDR = 0xc4a00000
|
---|
724 | PARAMETER C_RNG0_HIGHADDR = 0xc4a0ffff
|
---|
725 | PARAMETER C_RNG1_BASEADDR = 0xcac00000
|
---|
726 | PARAMETER C_RNG1_HIGHADDR = 0xcac0ffff
|
---|
727 | BUS_INTERFACE MPLB = plb_v46_40MHz
|
---|
728 | BUS_INTERFACE SPLB = plb
|
---|
729 | END
|
---|
730 |
|
---|
731 | BEGIN warplab_mimo_4x4_plbw
|
---|
732 | PARAMETER INSTANCE = warplab_mimo_4x4_plbw_0
|
---|
733 | PARAMETER HW_VER = 1.04.a
|
---|
734 | PARAMETER C_BASEADDR = 0x83800000
|
---|
735 | PARAMETER C_HIGHADDR = 0x83bfffff
|
---|
736 | BUS_INTERFACE SPLB = plb
|
---|
737 | PORT sysgen_clk = clk_40_0000MHz
|
---|
738 | PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I
|
---|
739 | PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q
|
---|
740 | PORT radio2_adc_i_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
|
---|
741 | PORT radio2_adc_q_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
|
---|
742 | PORT startcapture = net_gnd
|
---|
743 | PORT StartTx = net_gnd
|
---|
744 | PORT StopTx = net_gnd
|
---|
745 | PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I
|
---|
746 | PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q
|
---|
747 | PORT rssi_adc_clk = rssi_clk_out
|
---|
748 | PORT debug_capturing = rxrun
|
---|
749 | PORT debug_transmitting = txrun
|
---|
750 | PORT debug_agc_done = agcsetdone
|
---|
751 | PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I
|
---|
752 | PORT radio3_adc_i_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
|
---|
753 | PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q
|
---|
754 | PORT radio3_adc_q_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
|
---|
755 | PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I
|
---|
756 | PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q
|
---|
757 | PORT radio4_dac_q = radio_bridge_slot_4_user_DAC_Q
|
---|
758 | PORT radio4_dac_i = radio_bridge_slot_4_user_DAC_I
|
---|
759 | PORT radio1_dac_q = radio_bridge_slot_1_user_DAC_Q
|
---|
760 | PORT radio1_dac_i = radio_bridge_slot_1_user_DAC_I
|
---|
761 | PORT radio4_adc_q_otr = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin
|
---|
762 | PORT radio4_adc_q = radio_bridge_slot_4_user_ADC_Q
|
---|
763 | PORT radio4_adc_i_otr = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin
|
---|
764 | PORT radio4_adc_i = radio_bridge_slot_4_user_ADC_I
|
---|
765 | PORT radio1_adc_q_otr = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin
|
---|
766 | PORT radio1_adc_q = radio_bridge_slot_1_user_ADC_Q
|
---|
767 | PORT radio1_adc_i_otr = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin
|
---|
768 | PORT radio1_adc_i = radio_bridge_slot_1_user_ADC_I
|
---|
769 | PORT radio1_rssi = radio_bridge_slot_1_user_RSSI_ADC_D
|
---|
770 | PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
771 | PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
772 | PORT radio4_rssi = radio_bridge_slot_4_user_RSSI_ADC_D
|
---|
773 | PORT agc_done = agc_is_done
|
---|
774 | PORT fromagc_radio1_i = dc_filtered_i_a
|
---|
775 | PORT fromagc_radio1_q = dc_filtered_q_a
|
---|
776 | PORT fromagc_radio2_i = dc_filtered_i_b
|
---|
777 | PORT fromagc_radio2_q = dc_filtered_q_b
|
---|
778 | PORT fromagc_radio3_i = dc_filtered_i_c
|
---|
779 | PORT fromagc_radio3_q = dc_filtered_q_c
|
---|
780 | PORT fromagc_radio4_i = dc_filtered_i_d
|
---|
781 | PORT fromagc_radio4_q = dc_filtered_q_d
|
---|
782 | END
|
---|
783 |
|
---|
784 | BEGIN warplab_mimo_4x4_agc_plbw
|
---|
785 | PARAMETER INSTANCE = warplab_mimo_4x4_agc_plbw_0
|
---|
786 | PARAMETER HW_VER = 2.00.a
|
---|
787 | PARAMETER C_BASEADDR = 0xc4a00000
|
---|
788 | PARAMETER C_HIGHADDR = 0xc4a0ffff
|
---|
789 | BUS_INTERFACE SPLB = plb_v46_40MHz
|
---|
790 | PORT sysgen_clk = clk_40_0000MHz
|
---|
791 | PORT rxhp_d = agc_rxhp_d
|
---|
792 | PORT rxhp_c = agc_rxhp_c
|
---|
793 | PORT rxhp_b = agc_rxhp_b
|
---|
794 | PORT rxhp_a = agc_rxhp_a
|
---|
795 | PORT g_rf_d = agc_g_rf_d
|
---|
796 | PORT g_rf_c = agc_g_rf_c
|
---|
797 | PORT g_rf_b = agc_g_rf_b
|
---|
798 | PORT g_rf_a = agc_g_rf_a
|
---|
799 | PORT g_bb_d = agc_g_bb_d
|
---|
800 | PORT g_bb_c = agc_g_bb_c
|
---|
801 | PORT g_bb_b = agc_g_bb_b
|
---|
802 | PORT g_bb_a = agc_g_bb_a
|
---|
803 | PORT agc_done = agc_is_done
|
---|
804 | PORT rssi_in_d = radio_bridge_slot_4_user_RSSI_ADC_D
|
---|
805 | PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
806 | PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
807 | PORT rssi_in_a = radio_bridge_slot_1_user_RSSI_ADC_D
|
---|
808 | PORT reset_in = net_gnd
|
---|
809 | PORT q_in_d = radio_bridge_slot_4_user_ADC_Q
|
---|
810 | PORT q_in_c = radio_bridge_slot_3_user_ADC_Q
|
---|
811 | PORT q_in_b = radio_bridge_slot_2_user_ADC_Q
|
---|
812 | PORT q_in_a = radio_bridge_slot_1_user_ADC_Q
|
---|
813 | PORT packet_in = net_gnd
|
---|
814 | PORT mreset_in = net_gnd
|
---|
815 | PORT i_in_d = radio_bridge_slot_4_user_ADC_I
|
---|
816 | PORT i_in_c = radio_bridge_slot_3_user_ADC_I
|
---|
817 | PORT i_in_b = radio_bridge_slot_2_user_ADC_I
|
---|
818 | PORT i_in_a = radio_bridge_slot_1_user_ADC_I
|
---|
819 | PORT i_out_a = dc_filtered_i_a
|
---|
820 | PORT i_out_b = dc_filtered_i_b
|
---|
821 | PORT i_out_c = dc_filtered_i_c
|
---|
822 | PORT i_out_d = dc_filtered_i_d
|
---|
823 | PORT q_out_a = dc_filtered_q_a
|
---|
824 | PORT q_out_b = dc_filtered_q_b
|
---|
825 | PORT q_out_c = dc_filtered_q_c
|
---|
826 | PORT q_out_d = dc_filtered_q_d
|
---|
827 | END
|
---|
828 |
|
---|
829 | BEGIN xps_central_dma
|
---|
830 | PARAMETER INSTANCE = xps_central_dma_0
|
---|
831 | PARAMETER HW_VER = 2.03.a
|
---|
832 | PARAMETER C_BASEADDR = 0x80200000
|
---|
833 | PARAMETER C_HIGHADDR = 0x8020ffff
|
---|
834 | BUS_INTERFACE MPLB = plb
|
---|
835 | BUS_INTERFACE SPLB = plb
|
---|
836 | END
|
---|
837 |
|
---|
838 | BEGIN xps_timer
|
---|
839 | PARAMETER INSTANCE = xps_timer_0
|
---|
840 | PARAMETER HW_VER = 1.02.a
|
---|
841 | PARAMETER C_BASEADDR = 0x83c00000
|
---|
842 | PARAMETER C_HIGHADDR = 0x83c0ffff
|
---|
843 | BUS_INTERFACE SPLB = plb
|
---|
844 | END
|
---|
845 |
|
---|