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warplab.c

Last change on this file was 1818, checked in by chunter, 12 years ago
WARP v3 EDK Files
File size: 52.1 KB

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1	////////////////////////////////////////////////////////////////////////////////
2	//
3	// File : warplab.c
4	// Date : 2012, August 29
5	// Author : P. Murphy, S. Gupta, M. Duarte, C. Hunter
6	//
7	// Changelog:
8	// - This warplab.c is tailored to WARP v3. It will not compile on other hardware.
9	// - Added support for WARPxilnet_v3_00 that adds support for the hard TEMACs
10	// inside the Virtex4
11	// - v2 WARP hardware will use gigabit speeds by default. The Ethernet PHY
12	// advertises its speed as gigabit, so there is no longer a need to
13	// explicitly tell your computer to send at 100Mbit.
14	// - Uses an XPS_Timer core to inact a timeout of WAITDURATION_SEC seconds
15	// to wait for a sync packet. Previously, this timeout was handled by
16	// waiting a set number of packets (e.g. 10 received packets).
17	// - Moved the sync IP address up to a proper broadcast address of X.X.X.255.
18	// This should obviate the need for explicit ARP table entries to handle
19	// sync packets. The v06 WARPLAB M-Code Reference has correspondingly been
20	// updated.
21	// - This source file will compile for either v1 or v2 WARP hardware, assuming
22	// the WARPxilnet and WARP_FPGA_BOARD software libraries are configured
23	//
24	////////////////////////////////////////////////////////////////////////////////
25
26	#include "xparameters.h"
27	#include <xilnet_config.h>
28	#include <xilnet_xilsock.h>
29	#include <xilnet_mac.h>
30	#include "xstatus.h"
31	#include <stdlib.h>
32	#include <string.h>
33	#include "math.h"
34	#include "radio_controller.h"
35	#include "warplab_defines.h"
36	#include "warplab_regmacros.h"
37	#include "stdio.h"
38	#include "xtmrctr.h"
39	#include "w3_userio.h"
40	#include "w3_ad_controller.h"
41	#include "w3_clock_controller.h"
42	#include "w3_iic_eeprom.h"
43	#include "Xio.h"
44	#include "xlltemac.h"
45	#include "xllfifo.h"
46	#include "xdmacentral.h"
47	#include "xdmacentral_l.h"
48	#include "warp_hw_ver.h"
49
50	#define WARPLAB_MAJOR_VER 6
51	#define WARPLAB_MINOR_VER 2
52
53	#define RC_BASEADDR XPAR_RADIO_CONTROLLER_0_BASEADDR
54	#define AD_BASEADDR XPAR_W3_AD_CONTROLLER_0_BASEADDR
55	#define CLK_BASEADDR XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR
56	#define EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_0_BASEADDR
57	#define USERIO_BASEADDR XPAR_W3_USERIO_0_BASEADDR
58	#define TIMER_FREQ XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ
59	#define WARPLAB_TXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO1
60	#define WARPLAB_TXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO2
61	#define WARPLAB_TXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO3
62	#define WARPLAB_TXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO4
63	#define WARPLAB_RXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO1
64	#define WARPLAB_RXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO2
65	#define WARPLAB_RXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO3
66	#define WARPLAB_RXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO4
67	#define WARPLAB_RSSIBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO1
68	#define WARPLAB_RSSIBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO2
69	#define WARPLAB_RSSIBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO3
70	#define WARPLAB_RSSIBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO4
71	#define TEMAC_DEVICE_ID XPAR_LLTEMAC_0_DEVICE_ID
72	#define FIFO_DEVICE_ID XPAR_LLFIFO_0_DEVICE_ID
73	#define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID
74	#define TIMER_COUNTER_0 0
75
76
77	#define WARPLAB_CONFIG_2RF 1 // Comment in if board in 2x2 configuration
78	//#define WARPLAB_CONFIG_4RF 1 // Comment in if board in 4x4 configuration
79	// Currently not applicable to WARP v3
80
81	static XDmaCentral DmaCentralInst;
82	static XDmaCentral_Config *DMAConfigPtr;
83	XLlTemac TemacInstance;
84	XLlTemac_Config *MacCfgPtr;
85	XLlFifo FifoInstance;
86	XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */
87
88	u8 numSync;
89	u8 hw_generation;
90	u8 numRadios;
91
92	#define ENET_LINK_SPEED 1000
93	#define BUFSIZE 2000
94	#define DEBUG_LVL 0
95
96
97	#define WAITDURATION_SEC 2
98
99	unsigned int sendPtr32[(BUFSIZE+3)/4];
100	unsigned char * const sendBuffer = (unsigned char *) sendPtr32;
101	unsigned int receivePtr32[(BUFSIZE+3)/4];
102	unsigned char * const receiveBuffer = (unsigned char *) receivePtr32;
103	unsigned int myPort;
104
105	int sock; // UDP socket
106	struct sockaddr_in addr;
107	unsigned int alen = 0;
108	char node;
109
110	unsigned int ReadWrite;
111	unsigned char Radios_WirelessChan;
112	unsigned char Radios_Tx_LPF_Corn_Freq;
113	unsigned char Radios_Rx_LPF_Corn_Freq;
114	unsigned char Radio1_TxGain_BB, Radio1_TxGain_RF, Radio1_RxGain_BB, Radio1_RxGain_RF;
115	unsigned char Radio2_TxGain_BB, Radio2_TxGain_RF, Radio2_RxGain_BB, Radio2_RxGain_RF;
116	unsigned char Radio3_TxGain_BB, Radio3_TxGain_RF, Radio3_RxGain_BB, Radio3_RxGain_RF;
117	unsigned char Radio4_TxGain_BB, Radio4_TxGain_RF, Radio4_RxGain_BB, Radio4_RxGain_RF;
118
119	unsigned int AgcIsDoneAddr;
120	unsigned int MGC_AGC_Sel_Variable = 0; // By default MGC is selected
121
122	//----------------------------------
123	// Functions
124	void sendACK(unsigned int packetNo, unsigned int commandToACK);
125	unsigned char sevenSegmentMap(unsigned char x);
126	int warpphy_applyTxDCOCorrection(unsigned int radioSelection);
127	void warplab_AGC_Reset();
128	void warplab_AGC_MasterReset();
129	void warplab_AGC_Start();
130	void warplab_AGC_Initialize(int noise_estimate);
131	void warplab_AGC_setNoiseEstimate(int noise_estimate);
132	unsigned int warplab_AGC_GetGains(void);
133	void warplab_AGC_SetTarget(unsigned int target);
134	void warplab_AGC_SetDCO(unsigned int AGCstate);
135	int warpphy_applyTxDCOCalibration(unsigned int radioSelection);
136	// In WARPLab there is no decimation filter in the AGC, there is a downsampling only, so in WARPLab a function equivalent to
137	// ofdm_AGC_FiltSel is not needed
138
139	int w3_node_init() {
140
141	int status;
142	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
143	int ret = XST_SUCCESS;
144
145	microblaze_enable_exceptions();
146
147	//Initialize the AD9512 clock buffers (RF reference and sampling clocks)
148	status = clk_init(CLK_BASEADDR, 2);
149	if(status != XST_SUCCESS) {
150	xil_printf("w3_node_init: Error in clk_init (%d)\n", status);
151	ret = XST_FAILURE;
152	}
153	//Update the sampling clock buffer config to divide the AD clocks by 2 for 40MHz sampling
154	clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4B, 0x00); //OUT0 divider on
155	clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4A, 0x00); //OUT0 divide by 2
156	clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4F, 0x00); //OUT2 divider on
157	clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x4E, 0x00); //OUT2 divide by 2
158	clk_spi_write(CLK_BASEADDR, CLKCTRL_REG_SPITX_SAMP_CS, 0x5A, 0x01); //Self-clearing register update flag
159
160	//Initialize the AD9963 ADCs/DACs
161	status = ad_init(AD_BASEADDR, 2);
162	if(status != XST_SUCCESS) {
163	xil_printf("w3_node_init: Error in ad_init (%d)\n", status);
164	ret = XST_FAILURE;
165	}
166
167	//Initialize the radio_controller core and MAX2829 transceivers
168	status = radio_controller_init(RC_BASEADDR, (RC_RFA \| RC_RFB), 1, 1);
169	if(status != XST_SUCCESS) {
170	xil_printf("w3_node_init: Error in radio_controller_initialize (%d)\n", status);
171	ret = XST_FAILURE;
172	}
173
174	//Initialize the EEPROM read/write core
175	iic_eeprom_init(EEPROM_BASEADDR, 0x64);
176	if(status != XST_SUCCESS) {
177	xil_printf("w3_node_init: Error in IIC_EEPROM_init (%d)\n", status);
178	ret = XST_FAILURE;
179	}
180
181	/*
182	* Initialize the timer counter so that it's ready to use,
183	* specify the device ID that is generated in xparameters.h
184	*/
185	status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID);
186	if (status != XST_SUCCESS) {
187	xil_printf("w3_node_init: Error in XtmrCtr_Initialize (%d)\n", status);
188	ret = XST_FAILURE;
189	}
190
191	/*
192	* Perform a self-test to ensure that the hardware was built
193	* correctly, use the 1st timer in the device (0)
194	*/
195	status = XTmrCtr_SelfTest(TmrCtrInstancePtr, 0);
196	if (status != XST_SUCCESS) {
197	ret = XST_FAILURE;
198	}
199
200	// Set timer 0 to into a "count down" mode
201	XTmrCtr_SetOptions(TmrCtrInstancePtr, 0, (XTC_DOWN_COUNT_OPTION));
202
203	///// Project-Specific Initializations /////
204	node = userio_read_inputs(USERIO_BASEADDR)&W3_USERIO_DIPSW;
205	userio_write_hexdisp_left(USERIO_BASEADDR, (node+1)%10);
206
207	radio_controller_setTxGainSource(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_GAINSRC_SPI);
208	radio_controller_setRxGainSource(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_GAINSRC_SPI);
209
210	radio_controller_apply_TxDCO_calibration(AD_BASEADDR, EEPROM_BASEADDR, (RC_RFA \| RC_RFB));
211
212	//Set Tx bandwidth to nominal mode
213	Radios_Tx_LPF_Corn_Freq = 1;
214	radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_PARAMID_TXLPF_BW, Radios_Tx_LPF_Corn_Freq);
215
216	//Set Rx bandwidth to nominal mode
217	Radios_Rx_LPF_Corn_Freq = 1;
218	radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_PARAMID_RXLPF_BW, Radios_Rx_LPF_Corn_Freq);
219
220	//Set Radios to use 30KHz cutoff on HPF
221	radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 1);
222
223	radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_PARAMID_TXLINEARITY_VGA, 2);
224
225
226
227	///Timer Setup///
228	XTmrCtr_SetResetValue(TmrCtrInstancePtr,1,0); //Sets it so issuing a "start" command begins at counter=0
229	/////////////////
230
231	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA \| RC_RFB));
232
233
234	#ifdef WARP_HW_VER_v3
235	hw_generation = 3;
236	#elif defined WARP_HW_VER_v2
237	hw_generation = 2;
238	#elif defined WARP_HW_VER_v1
239	hw_generation = 1;
240	#endif
241
242	#ifdef WARPLAB_CONFIG_2RF
243	numRadios = 2;
244	#elif defined WARPLAB_CONFIG_4RF
245	numRadios = 4;
246	#endif
247
248
249
250	return ret;
251	}
252
253	void usleep(u32 duration){
254	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
255	XTmrCtr_SetResetValue(TmrCtrInstancePtr,0,duration*(TIMER_FREQ/1000000));
256
257	XTmrCtr_Start(TmrCtrInstancePtr,0);
258
259	volatile u8 isExpired = 0;
260	while(isExpired!=1){
261	isExpired = XTmrCtr_IsExpired(TmrCtrInstancePtr,0);
262	}
263	XTmrCtr_Reset(TmrCtrInstancePtr,0);
264	return;
265	}
266
267
268	void init_net() {
269	int Status;
270	xil_printf("Configuring network\n");
271
272	mb_hw_addr[0] = 0x00;
273	mb_hw_addr[1] = 0x50;
274	mb_hw_addr[2] = 0xc2;
275	mb_hw_addr[3] = 0x63;
276	mb_hw_addr[4] = 0x36;
277	mb_hw_addr[5] = node+0x63;
278
279	mb_ip_addr[0] = 10;
280	mb_ip_addr[1] = 0;
281	mb_ip_addr[2] = 0;
282	mb_ip_addr[3] = node+1;
283
284	//Define the last octet of the IP address used for SYNC packets. The first three will be the mb_ip_addr.
285	sync_IP_octet = 255;
286
287	myPort = 9000 + node;
288
289	xilnet_eth_init_hw_addr_tbl();
290
291	if(DEBUG_LVL > 1) xil_printf("... initializing DMA\n");
292	/************************DMA*****************************/
293	//Lookup the DMA configuration information
294	DMAConfigPtr = XDmaCentral_LookupConfig(XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID);
295
296	//Initialize the config struct
297	Status = XDmaCentral_CfgInitialize(&DmaCentralInst, DMAConfigPtr, DMAConfigPtr->BaseAddress);
298	if (Status != XST_SUCCESS){
299	xil_printf("... ... DMA CfgInitialize failed!\n");
300	return;
301	}
302
303	//Disable Interrupts
304	XDmaCentral_InterruptEnableSet(&DmaCentralInst, 0);
305	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
306	/************************************************************/
307
308	/*****************Ethernet********************************/
309	if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet\n");
310	MacCfgPtr = XLlTemac_LookupConfig(TEMAC_DEVICE_ID);
311	Status = XLlTemac_CfgInitialize(&TemacInstance, MacCfgPtr, MacCfgPtr->BaseAddress);
312	XLlFifo_Initialize(&FifoInstance, XLlTemac_LlDevBaseAddress(&TemacInstance));
313	if (Status != XST_SUCCESS)
314	xil_printf("... ... EMAC init error\n");
315
316	if (!XLlTemac_IsFifo(&TemacInstance))
317	xil_printf("... ... EMAC hw config incorrect\n");
318
319
320
321	Status = XLlTemac_ClearOptions(&TemacInstance, XTE_LENTYPE_ERR_OPTION \| XTE_FLOW_CONTROL_OPTION \| XTE_FCS_STRIP_OPTION);// \| XTE_MULTICAST_OPTION);
322	Status \|= XLlTemac_SetOptions(&TemacInstance, XTE_PROMISC_OPTION \| XTE_MULTICAST_OPTION \| XTE_BROADCAST_OPTION \| XTE_RECEIVER_ENABLE_OPTION \| XTE_TRANSMITTER_ENABLE_OPTION); //\| XTE_JUMBO_OPTION
323	if (Status != XST_SUCCESS)
324	xil_printf("... ... Error setting EMAC options\n, code %d", Status);
325
326	// Make sure the TEMAC is ready
327	Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET);
328	while ((Status & XTE_RDY_HARD_ACS_RDY_MASK) == 0)
329	{
330	Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET);
331	}
332
333	XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED);
334	usleep(1 * 10000);
335
336	XLlTemac_Start(&TemacInstance);
337	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
338	/************************************************************/
339
340	// Initialize the MAC OPB base address (MAC driver in net/mac.c)
341	xilnet_mac_init((void )&FifoInstance,(void )&DmaCentralInst);
342
343
344	if(DEBUG_LVL > 1) xil_printf("... complete!\n");
345	// Print IP address
346	if(DEBUG_LVL > 0) xil_printf("IP Address: %d.%d.%d.%d \n", mb_ip_addr[0], mb_ip_addr[1],mb_ip_addr[2],mb_ip_addr[3]);
347	}
348
349
350	void init_socket() {
351
352	sock = xilsock_socket(AF_INET, SOCK_DGRAM, 0); // Create UDP socket with domain Internet and UDP connection.
353	if (sock == -1) {
354	if(DEBUG_LVL > 0) xil_printf("Error in creating socket\n");
355	exit(-1);
356	}
357
358	addr.sin_family = AF_INET;
359	addr.sin_port = myPort;
360	addr.sin_addr.s_addr = INADDR_ANY; // Create the input socket with any incoming address. (0x00000000)
361
362	XStatus bind = xilsock_bind(sock, (struct sockaddr *)&addr, sizeof(struct sockaddr));
363	if (bind == -1) {
364	if(DEBUG_LVL > 0) xil_printf("Unable to bind socket\n");
365	exit(-1);
366	}
367	alen = sizeof(struct sockaddr);
368	if(DEBUG_LVL > 0) xil_printf("Listening on UDP port %d.\n", myPort);
369	}
370
371	void shut_socket() {
372	xilsock_close(sock);
373	}
374
375	int waitForSync()
376	{
377	unsigned int n;
378	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
379	XTmrCtr_Start(TmrCtrInstancePtr, 1);
380
381	while(XTmrCtr_GetValue(TmrCtrInstancePtr, 1) < (WAITDURATION_SEC*XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ)){
382	n = xilnet_eth_recv_frame(receiveBuffer, BUFSIZE);
383	if(n==9999)
384	{
385	//xil_printf("Got Sync\n");
386	numSync++;
387	return 0;
388	}
389	}
390
391	XTmrCtr_Stop(TmrCtrInstancePtr, 1);
392
393	int numblinks;
394	for(numblinks=0;numblinks<10;numblinks++){
395	userio_write_leds_red(USERIO_BASEADDR,0xF);
396	usleep(100000);
397	userio_write_leds_red(USERIO_BASEADDR,0x0);
398	usleep(100000);
399	userio_write_leds_red(USERIO_BASEADDR,0xF);
400	}
401	userio_write_leds_red(USERIO_BASEADDR,0x0);
402	userio_write_leds_green(USERIO_BASEADDR,0x0);
403
404	xil_printf("NoSync\n");
405	return 1;
406	}
407
408	int main() {
409
410	int bytesReceived;
411	int bytesSend;
412	int command;
413	int packetNo;
414	int status;
415	unsigned int rxArg0;
416	char done = 0;
417	unsigned char sevenSeg1 = 0x1;
418	int agctarget = -14;
419	int agcnoiseEst = -95;
420	unsigned int agc_dco_state;
421
422	status = w3_node_init();
423	if(status != 0) {
424	xil_printf("Error in w3_node_init()! Exiting\n");
425	return -1;
426	}
427
428	//Initialize the xilnet stack & default sockets
429	init_net();
430	init_socket();
431
432	#ifdef WARPLAB_CONFIG_2RF
433	xil_printf("WARPLab 2x2 Started - Waiting for connection from MATLAB\n");
434	#elif defined WARPLAB_CONFIG_4RF
435	xil_printf("WARPLab 4x4 Started - Waiting for connection from MATLAB\n");
436	#endif
437
438
439	userio_write_leds_red(USERIO_BASEADDR,0x5);
440	int numblinks;
441	for(numblinks=0;numblinks<10;numblinks++){
442	userio_toggle_leds_red(USERIO_BASEADDR,0xF);
443	usleep(100000);
444	}
445	userio_write_leds_red(USERIO_BASEADDR,0x0);
446	userio_write_leds_green(USERIO_BASEADDR,0x0);
447
448	XLlFifo_Reset(&FifoInstance);
449
450
451
452	while(done == 0) {
453
454	if(DEBUG_LVL > 3) xil_printf("\|");
455
456	bytesReceived = xilsock_recvfrom(sock, receiveBuffer, BUFSIZE, (struct sockaddr *)&addr, &alen); // Wait to receive data
457
458	if (bytesReceived > 0) { // Check for valid packet
459
460	packetNo = receivePtr32[0];
461	command = receivePtr32[1];
462	rxArg0 = receivePtr32[2];
463
464	//Rotate the single active bit
465	sevenSeg1 = ( ((sevenSeg1<<1)&0x7E) \| ((sevenSeg1>>5)&0x7E) );
466
467	userio_write_hexdisp_right(USERIO_BASEADDR, sevenSeg1<<1);
468
469	if(DEBUG_LVL > 2) xil_printf("=============\nPacket Received\n Length: %d\n Packet No.: %d\n Command No: %d\n", bytesReceived, packetNo, command);
470
471	switch(command) { // Decode on incoming command
472
473	case INITIALIZE:
474	//if(DEBUG_LVL > 1) xil_printf("Initializing Node...");
475	warplab_buffers_WriteReg_TxDelay(0);
476	warplab_buffers_WriteReg_StartCapture(0);
477	warplab_buffers_WriteReg_TxLength((unsigned int)16383);
478	warplab_buffers_WriteReg_TransMode(0);
479	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0);
480	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0);
481	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0);
482	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0);
483	warplab_AGC_WriteReg_RADIO1_AGC_EN(0); // No radio on slot 1
484	warplab_AGC_WriteReg_RADIO2_AGC_EN(0);
485	warplab_AGC_WriteReg_RADIO3_AGC_EN(0);
486	warplab_AGC_WriteReg_RADIO4_AGC_EN(0); // No radio on slot 4
487	warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)50);
488	warplab_buffers_WriteReg_MGC_AGC_SEL(0);// Select MGC by default
489	warplab_AGC_WriteReg_AGC_EN(0);
490	MGC_AGC_Sel_Variable = 0;
491	#ifdef WARPLAB_CONFIG_4RF
492	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0);
493	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0);
494	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0);
495	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0);
496	#endif
497	sendACK(packetNo, command);
498	break;
499
500	case NETWORKCHECK:
501	sendPtr32[0] = packetNo + 1;
502	sendPtr32[1] = ACK;
503	sendPtr32[2] = command;
504	sendPtr32[3] = numSync;
505	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
506	numSync = 0;
507	waitForSync();
508	break;
509
510	case BOARDINFO:
511	sendPtr32[0] = packetNo + 1;
512	sendPtr32[1] = ACK;
513	sendPtr32[2] = command;
514	sendPtr32[3] = w3_eeprom_readSerialNum(EEPROM_BASEADDR);
515	sendPtr32[4] = userio_read_fpga_dna_msb(USERIO_BASEADDR);
516	sendPtr32[5] = userio_read_fpga_dna_lsb(USERIO_BASEADDR);
517	sendPtr32[6] = (hw_generation<<24)\|(numRadios<<16)\|(WARPLAB_MAJOR_VER<<8)\|(WARPLAB_MINOR_VER);
518	xilsock_sendto(sock, sendBuffer, 28, (struct sockaddr *)&addr, alen);
519	break;
520
521	case TX_DELAY:
522
523	ReadWrite = (unsigned int)receivePtr32[2];
524	if(0 == ReadWrite)
525	{
526	sendPtr32[0] = packetNo + 1;
527	sendPtr32[1] = ACK;
528	sendPtr32[2] = command;
529
530	sendPtr32[3] = warplab_mimo_ReadReg_TxDelay(WARPLAB_BASEADDR);
531
532	if(DEBUG_LVL > 2) xil_printf("Read capt offset of %d\n", (unsigned int)receivePtr32[3]);
533	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
534	}
535	if(1 == ReadWrite)
536	{
537	//If the user requests a TX_DELAY that's too big, write the maximum instead
538	warplab_buffers_WriteReg_TxDelay((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]);
539	if(DEBUG_LVL > 2) xil_printf("Set capt offset to %d\n", (unsigned int)receivePtr32[3]);
540	sendACK(packetNo, command);
541	}
542
543	break;
544
545	case TX_LENGTH:
546	ReadWrite = (unsigned int)receivePtr32[2];
547	if(0 == ReadWrite)
548	{
549	sendPtr32[0] = packetNo + 1;
550	sendPtr32[1] = ACK;
551	sendPtr32[2] = command;
552
553	sendPtr32[3] = warplab_mimo_ReadReg_TxLength(WARPLAB_BASEADDR);
554
555	if(DEBUG_LVL > 2) xil_printf("Read TxLength of %d\n", (unsigned int)receivePtr32[3]);
556	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
557	}
558	if(1 == ReadWrite)
559	{
560	//If the user requests a TX_LENGTH that's too big, write the maximum instead
561	warplab_buffers_WriteReg_TxLength((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]);
562	if(DEBUG_LVL > 2) xil_printf("Set TxLength to %d\n", (unsigned int)receivePtr32[3]);
563	sendACK(packetNo, command);
564	}
565	break;
566
567	case TX_MODE:
568	ReadWrite = (unsigned int)receivePtr32[2];
569	if(0 == ReadWrite)
570	{
571	sendPtr32[0] = packetNo + 1;
572	sendPtr32[1] = ACK;
573	sendPtr32[2] = command;
574
575	sendPtr32[3] = warplab_mimo_ReadReg_TransMode(WARPLAB_BASEADDR);
576
577	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
578	}
579	if(1 == ReadWrite)
580	{
581	warplab_buffers_WriteReg_TransMode((unsigned int)receivePtr32[3]);
582	sendACK(packetNo, command);
583	}
584	break;
585
586
587	case RX1BUFFERS_DEBUG:
588
589	break;
590
591	case RX2BUFFERS_DEBUG:
592
593	break;
594
595	#ifdef WARPLAB_CONFIG_4RF
596	case RX3BUFFERS_DEBUG:
597
598	break;
599
600	case RX4BUFFERS_DEBUG:
601
602	break;
603	#endif
604
605	case MGC_AGC_SEL:
606	//ReadWrite = (unsigned int)receivePtr32[2];
607	MGC_AGC_Sel_Variable = (unsigned int)receivePtr32[2];
608	//if(0 == ReadWrite)
609	//{
610	// sendPtr32[0] = packetNo + 1;
611	// sendPtr32[1] = ACK;
612	// sendPtr32[2] = command;
613
614	// sendPtr32[3] = warplab_mimo_4x4_ReadReg_MGC_AGC_SEL(XPAR_WARPLAB_MIMO_4X4_OPBW_0_BASEADDR);
615
616	// xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
617	//}
618	//if(1 == ReadWrite)
619	//{
620	warplab_buffers_WriteReg_MGC_AGC_SEL(MGC_AGC_Sel_Variable);
621
622	if(0 == MGC_AGC_Sel_Variable)
623	{
624	warplab_AGC_WriteReg_AGC_EN(0);
625	radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_REG);
626	radio_controller_setRxGainSource(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_GAINSRC_SPI);
627	}
628	if(1 == MGC_AGC_Sel_Variable)
629	{
630	radio_controller_setCtrlSource(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_HW);
631	radio_controller_setRxGainSource(RC_BASEADDR, (RC_RFA \| RC_RFB), RC_GAINSRC_HW);
632
633	// Initialize the AGC
634	warplab_AGC_Initialize(agcnoiseEst);
635	warplab_AGC_setNoiseEstimate(agcnoiseEst);
636	// ofdm_AGC_FiltSel(0); No decimation option in WARPLab AGC
637	warplab_AGC_SetDCO(0);
638	warplab_AGC_SetTarget(agctarget);
639	warplab_AGC_Reset();
640	}
641
642	sendACK(packetNo, command);
643	//}
644	break;
645
646	case CARRIER_CHANNEL:
647	Radios_WirelessChan = ((unsigned int)receivePtr32[2]);
648
649	//Channels in [1...37] are valid
650	// Values in [1...14] select 2.4GHz channels [1...14]
651	// Values in [15...37] select a 5GHz channels [1...23]
652	if(Radios_WirelessChan <= (14+23))
653	{
654	if(Radios_WirelessChan <= 14) {
655	radio_controller_setCenterFrequency(RC_BASEADDR, (RC_RFA\|RC_RFB), RC_24GHZ, Radios_WirelessChan);
656	} else {
657	radio_controller_setCenterFrequency(RC_BASEADDR, (RC_RFA\|RC_RFB), RC_5GHZ, (Radios_WirelessChan-14));
658	}
659	}
660
661	sendACK(packetNo, command);
662	break;
663
664	case TX_LPF_CORN_FREQ:
665	Radios_Tx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]);
666	radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA\|RC_RFB), RC_PARAMID_TXLPF_BW, Radios_Tx_LPF_Corn_Freq&0x3);
667	sendACK(packetNo, command);
668	break;
669
670	case RX_LPF_CORN_FREQ:
671	Radios_Rx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]);
672	radio_controller_setRadioParam(RC_BASEADDR, (RC_RFA\|RC_RFB), RC_PARAMID_RXLPF_BW, Radios_Rx_LPF_Corn_Freq&0x3);
673	sendACK(packetNo, command);
674	break;
675
676
677	case RADIO1_TXGAINS:
678	//Extract the radio gain config options from the received Ethernet packet
679	Radio1_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
680	Radio1_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
681	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_BB, Radio1_TxGain_BB);
682	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_RF, Radio1_TxGain_RF);
683	//radio_controller_setTxGainTarget(RC_BASEADDR, RC_RFA, Radio1_TxGain_RF);
684	sendACK(packetNo, command);
685	break;
686
687	case RADIO1_RXGAINS:
688	//Extract the radio gain config options from the received Ethernet packet
689	Radio1_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
690	Radio1_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
691	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_BB, Radio1_RxGain_BB);
692	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_RF, Radio1_RxGain_RF);
693	sendACK(packetNo, command);
694	break;
695
696	case RADIO2_TXGAINS:
697	//Extract the radio gain config options from the received Ethernet packet
698	Radio2_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
699	Radio2_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
700	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_TXGAIN_BB, Radio2_TxGain_BB);
701	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_TXGAIN_RF, Radio2_TxGain_RF);
702	sendACK(packetNo, command);
703	break;
704
705	case RADIO2_RXGAINS:
706	//Extract the radio gain config options from the received Ethernet packet
707	Radio2_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
708	Radio2_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
709	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_RXGAIN_BB, Radio2_RxGain_BB);
710	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_RXGAIN_RF, Radio2_RxGain_RF);
711	sendACK(packetNo, command);
712	break;
713
714	#ifdef WARPLAB_CONFIG_4RF
715	case RADIO3_TXGAINS:
716	sendACK(packetNo, command);
717	break;
718
719	case RADIO3_RXGAINS:
720	sendACK(packetNo, command);
721	break;
722
723	case RADIO4_TXGAINS:
724	sendACK(packetNo, command);
725	break;
726
727	case RADIO4_RXGAINS:
728	sendACK(packetNo, command);
729	break;
730	#endif
731
732
733	case RADIO1_TXEN:
734	radio_controller_TxEnable(RC_BASEADDR, (RC_RFA));
735
736	if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Enabled\n");
737	sendACK(packetNo, command);
738	break;
739
740	case RADIO2_TXEN:
741	radio_controller_TxEnable(RC_BASEADDR, (RC_RFB));
742
743	if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Enabled\n");
744	sendACK(packetNo, command);
745	break;
746
747	#ifdef WARPLAB_CONFIG_4RF
748	case RADIO3_TXEN:
749	sendACK(packetNo, command);
750	break;
751
752
753	case RADIO4_TXEN:
754	sendACK(packetNo, command);
755	break;
756	#endif
757
758	case RADIO1_TXDIS:
759	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA));
760	if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\n");
761	sendACK(packetNo, command);
762	break;
763
764	case RADIO2_TXDIS:
765	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFB));
766	if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\n");
767	sendACK(packetNo, command);
768	break;
769
770	#ifdef WARPLAB_CONFIG_4RF
771	case RADIO3_TXDIS:
772	sendACK(packetNo, command);
773	break;
774
775	case RADIO4_TXDIS:
776	sendACK(packetNo, command);
777	break;
778	#endif
779
780	case RADIO1_RXEN:
781	/*************** Setup the radio board **********/
782	if(0 == MGC_AGC_Sel_Variable)
783	{
784	// Disable the Rx HP filter
785	// Only needed in Manual Gain Control (MGC) Mode
786	// In Automatic Gain Control (AGC) Mode, the RxHp
787	// is controlled by the AGC core
788	radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_OFF);
789	}
790
791	// usleep(10);
792
793	//Enable the receiver
794	radio_controller_RxEnable(RC_BASEADDR, (RC_RFA));
795
796	if(1 == MGC_AGC_Sel_Variable)
797	{
798	//Enable this radio's AGC if user has set AGC Mode
799	warplab_AGC_WriteReg_RADIO1_AGC_EN(1);
800	}
801
802	/*************** END Setup the radio board **********/
803
804	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n");
805	if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n");
806	sendACK(packetNo, command);
807	break;
808
809	case RADIO2_RXEN:
810
811	/*************** Setup the radio board **********/
812	if(0 == MGC_AGC_Sel_Variable)
813	{
814	// Disable the Rx HP filter
815	// Only needed in Manual Gain Control (MGC) Mode
816	// In Automatic Gain Control (AGC) Mode, the RxHp
817	// is controlled by the AGC core
818	//WarpRadio_v1_RxHpDisable(radio2);
819	radio_controller_setRxHP(RC_BASEADDR, (RC_RFB), RC_RXHP_OFF);
820	}
821
822	// usleep(10);
823
824	//Enable the receiver
825	radio_controller_RxEnable(RC_BASEADDR, (RC_RFB));
826
827	if(1 == MGC_AGC_Sel_Variable)
828	{
829	//Enable this radio's AGC if user has set AGC Mode
830	warplab_AGC_WriteReg_RADIO2_AGC_EN(1);
831	}
832
833	/*************** END Setup the radio board **********/
834
835	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n");
836	if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n");
837	sendACK(packetNo, command);
838	break;
839
840	#ifdef WARPLAB_CONFIG_4RF
841	case RADIO3_RXEN:
842	sendACK(packetNo, command);
843	break;
844
845	case RADIO4_RXEN:
846	sendACK(packetNo, command);
847	break;
848	#endif
849
850	case RADIO1_RXDIS:
851	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA));
852
853	if(0 == MGC_AGC_Sel_Variable)
854	{
855	//Enable the Rx HP filter
856	// Only needed in Manual Gain Control (MGC) Mode
857	// In Automatic Gain Control (AGC) Mode, the RxHp
858	// is controlled by the AGC core
859	radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_ON);
860	}
861
862	if(1 == MGC_AGC_Sel_Variable)
863	{
864	//Disable this radio's AGC if user has set AGC Mode
865	warplab_AGC_WriteReg_RADIO1_AGC_EN(0);
866	}
867
868	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n");
869	if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n");
870	sendACK(packetNo, command);
871	break;
872
873	case RADIO2_RXDIS:
874	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFB));
875
876	if(0 == MGC_AGC_Sel_Variable)
877	{
878	//Enable the Rx HP filter
879	// Only needed in Manual Gain Control (MGC) Mode
880	// In Automatic Gain Control (AGC) Mode, the RxHp
881	// is controlled by the AGC core
882	radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_ON);
883	}
884
885	if(1 == MGC_AGC_Sel_Variable)
886	{
887	//Disable this radio's AGC if user has set AGC Mode
888	warplab_AGC_WriteReg_RADIO2_AGC_EN(0);
889	}
890
891	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n");
892	if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n");
893	sendACK(packetNo, command);
894	break;
895
896	#ifdef WARPLAB_CONFIG_4RF
897	case RADIO3_RXDIS:
898	WarpRadio_v1_TxRxDisable(radio3);
899
900	if(0 == MGC_AGC_Sel_Variable)
901	{
902	//Enable the Rx HP filter
903	// Only needed in Manual Gain Control (MGC) Mode
904	// In Automatic Gain Control (AGC) Mode, the RxHp
905	// is controlled by the AGC core
906	WarpRadio_v1_RxHpEnable(radio3);
907	}
908
909	if(1 == MGC_AGC_Sel_Variable)
910	{
911	//Disable this radio's AGC if user has set AGC Mode
912	warplab_AGC_WriteReg_RADIO3_AGC_EN(0);
913	}
914
915	//if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n");
916	if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n");
917	sendACK(packetNo, command);
918	break;
919
920	case RADIO4_RXDIS:
921	WarpRadio_v1_TxRxDisable(radio4);
922
923	if(0 == MGC_AGC_Sel_Variable)
924	{
925	//Enable the Rx HP filter
926	// Only needed in Manual Gain Control (MGC) Mode
927	// In Automatic Gain Control (AGC) Mode, the RxHp
928	// is controlled by the AGC core
929	WarpRadio_v1_RxHpEnable(radio4);
930	}
931
932	if(1 == MGC_AGC_Sel_Variable)
933	{
934	//Disable this radio's AGC if user has set AGC Mode
935	warplab_AGC_WriteReg_RADIO4_AGC_EN(0);
936	}
937
938	//if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n");
939	if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n");
940	sendACK(packetNo, command);
941	break;
942	#endif
943
944	case RADIO1_TXDATA:
945	memcpy
946	(
947	(unsigned int )(WARPLAB_TXBUFF_RADIO1 + 4rxArg0),\
948	(unsigned int *)(receivePtr32 + 3),\
949	(bytesReceived-12)
950	);
951	sendACK(packetNo, command);
952	break;
953
954	case RADIO2_TXDATA:
955	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
956	//if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", (unsigned int )(receivePtr32 + 3), (unsigned int )(receivePtr32 + 4), (unsigned int )(receivePtr32 + 5), (unsigned int )(receivePtr32 + 6));
957
958	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
959
960	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
961
962	memcpy
963	(
964	(unsigned int )(WARPLAB_TXBUFF_RADIO2 + 4rxArg0),\
965	(unsigned int *)(receivePtr32 + 3),\
966	(bytesReceived-12)
967	);
968
969	sendACK(packetNo, command);
970	break;
971
972
973	#ifdef WARPLAB_CONFIG_4RF
974	case RADIO3_TXDATA:
975	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0);
976	//if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", (unsigned int )(receivePtr32 + 3), (unsigned int )(receivePtr32 + 4), (unsigned int )(receivePtr32 + 5), (unsigned int )(receivePtr32 + 6));
977
978	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0);
979
980	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0);
981	/*
982	memcpy
983	(
984	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMWO_TxBuff_Radio3_OFFSET + 4rxArg0),\
985	(unsigned int *)(receivePtr32 + 3),\
986	(bytesReceived-12)
987	);
988	*/
989	memcpy
990	(
991	(unsigned int )(WARPLAB_TXBUFF_RADIO3 + 4rxArg0),\
992	(unsigned int *)(receivePtr32 + 3),\
993	(bytesReceived-12)
994	);
995	sendACK(packetNo, command);
996	break;
997
998	case RADIO4_TXDATA:
999	memcpy
1000	(
1001	(unsigned int )(WARPLAB_TXBUFF_RADIO4 + 4rxArg0),\
1002	(unsigned int *)(receivePtr32 + 3),\
1003	(bytesReceived-12)
1004	);
1005	sendACK(packetNo, command);
1006	break;
1007	#endif
1008
1009
1010	case RADIO1_RXDATA:
1011	memcpy
1012	(
1013	(unsigned int *)(sendPtr32 + 4), \
1014	(unsigned int )(WARPLAB_RXBUFF_RADIO1 + 4rxArg0),\
1015	1024
1016	);
1017
1018	sendPtr32[0] = packetNo + 1;
1019	sendPtr32[1] = ACK;
1020	sendPtr32[2] = command;
1021	sendPtr32[3] = rxArg0;
1022	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1023	break;
1024
1025	case RADIO2_RXDATA:
1026	//while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {}
1027
1028	/*
1029	memcpy
1030	(
1031	(unsigned int *)(sendPtr32 + 4), \
1032	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + 4rxArg0),\
1033	1024
1034	);
1035	*/
1036	memcpy
1037	(
1038	(unsigned int *)(sendPtr32 + 4), \
1039	(unsigned int )(WARPLAB_RXBUFF_RADIO2 + 4rxArg0),\
1040	1024
1041	);
1042
1043	//if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0);
1044	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + rxArg0));
1045
1046	sendPtr32[0] = packetNo + 1;
1047	sendPtr32[1] = ACK;
1048	sendPtr32[2] = command;
1049	sendPtr32[3] = rxArg0;
1050	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1051	break;
1052	#ifdef WARPLAB_CONFIG_4RF
1053	case RADIO3_RXDATA:
1054	//while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {}
1055
1056	/*
1057	memcpy
1058	(
1059	(unsigned int *)(sendPtr32 + 4), \
1060	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET + 4rxArg0),\
1061	1024
1062	);
1063	*/
1064	memcpy
1065	(
1066	(unsigned int *)(sendPtr32 + 4), \
1067	(unsigned int )(WARPLAB_RXBUFF_RADIO3 + 4rxArg0),\
1068	1024
1069	);
1070
1071
1072	//if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0);
1073	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio3_OFFSET + rxArg0));
1074
1075	sendPtr32[0] = packetNo + 1;
1076	sendPtr32[1] = ACK;
1077	sendPtr32[2] = command;
1078	sendPtr32[3] = rxArg0;
1079	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1080	break;
1081
1082	case RADIO4_RXDATA:
1083	memcpy
1084	(
1085	(unsigned int *)(sendPtr32 + 4), \
1086	(unsigned int )(WARPLAB_RXBUFF_RADIO4 + 4rxArg0),\
1087	1024
1088	);
1089
1090	sendPtr32[0] = packetNo + 1;
1091	sendPtr32[1] = ACK;
1092	sendPtr32[2] = command;
1093	sendPtr32[3] = rxArg0;
1094	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1095	break;
1096	#endif
1097
1098
1099	case RADIO1_RSSIDATA:
1100	memcpy
1101	(
1102	(unsigned int *)(sendPtr32 + 4), \
1103	(unsigned int )(WARPLAB_RSSIBUFF_RADIO1 + 4rxArg0),\
1104	1024
1105	);
1106	sendPtr32[0] = packetNo + 1;
1107	sendPtr32[1] = ACK;
1108	sendPtr32[2] = command;
1109	sendPtr32[3] = rxArg0;
1110	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1111	break;
1112
1113	case RADIO2_RSSIDATA:
1114	//while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {}
1115
1116	/*
1117	memcpy
1118	(
1119	(unsigned int *)(sendPtr32 + 4), \
1120	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4rxArg0),\
1121	1024
1122	);
1123	*/
1124	memcpy
1125	(
1126	(unsigned int *)(sendPtr32 + 4), \
1127	(unsigned int )(WARPLAB_RSSIBUFF_RADIO2 + 4rxArg0),\
1128	1024
1129	);
1130
1131
1132	//if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0);
1133	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0));
1134
1135	sendPtr32[0] = packetNo + 1;
1136	sendPtr32[1] = ACK;
1137	sendPtr32[2] = command;
1138	sendPtr32[3] = rxArg0;
1139	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1140	break;
1141
1142	#ifdef WARPLAB_CONFIG_4RF
1143	case RADIO3_RSSIDATA:
1144	//while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {}
1145
1146	/*
1147	memcpy
1148	(
1149	(unsigned int *)(sendPtr32 + 4), \
1150	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4rxArg0),\
1151	1024
1152	);
1153	*/
1154	memcpy
1155	(
1156	(unsigned int *)(sendPtr32 + 4), \
1157	(unsigned int )(WARPLAB_RSSIBUFF_RADIO3 + 4rxArg0),\
1158	1024
1159	);
1160
1161
1162	//if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0);
1163	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4*rxArg0));
1164
1165	sendPtr32[0] = packetNo + 1;
1166	sendPtr32[1] = ACK;
1167	sendPtr32[2] = command;
1168	sendPtr32[3] = rxArg0;
1169	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1170	break;
1171
1172	case RADIO4_RSSIDATA:
1173	memcpy
1174	(
1175	(unsigned int *)(sendPtr32 + 4), \
1176	(unsigned int )(WARPLAB_RSSIBUFF_RADIO4 + 4rxArg0),\
1177	1024
1178	);
1179	sendPtr32[0] = packetNo + 1;
1180	sendPtr32[1] = ACK;
1181	sendPtr32[2] = command;
1182	sendPtr32[3] = rxArg0;
1183	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1184	break;
1185	#endif
1186
1187
1188	case RADIO1TXBUFF_TXEN:
1189	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(1);
1190
1191	sendACK(packetNo, command);
1192	break;
1193
1194	case RADIO2TXBUFF_TXEN:
1195	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(1);
1196
1197	sendACK(packetNo, command);
1198	break;
1199
1200	#ifdef WARPLAB_CONFIG_4RF
1201	case RADIO3TXBUFF_TXEN:
1202	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(1);
1203
1204	sendACK(packetNo, command);
1205	break;
1206
1207	case RADIO4TXBUFF_TXEN:
1208	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(1);
1209
1210	sendACK(packetNo, command);
1211	break;
1212	#endif
1213
1214	case RADIO1TXBUFF_TXDIS:
1215	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0);
1216
1217	sendACK(packetNo, command);
1218	break;
1219
1220	case RADIO2TXBUFF_TXDIS:
1221	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0);
1222
1223	sendACK(packetNo, command);
1224	break;
1225
1226	#ifdef WARPLAB_CONFIG_4RF
1227	case RADIO3TXBUFF_TXDIS:
1228	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0);
1229
1230	sendACK(packetNo, command);
1231	break;
1232
1233	case RADIO4TXBUFF_TXDIS:
1234	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0);
1235
1236	sendACK(packetNo, command);
1237	break;
1238	#endif
1239
1240	case RADIO1RXBUFF_RXEN:
1241	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(1);
1242
1243	sendACK(packetNo, command);
1244	break;
1245
1246	case RADIO2RXBUFF_RXEN:
1247	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(1);
1248
1249	sendACK(packetNo, command);
1250	break;
1251
1252	#ifdef WARPLAB_CONFIG_4RF
1253	case RADIO3RXBUFF_RXEN:
1254	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(1);
1255
1256	sendACK(packetNo, command);
1257	break;
1258
1259	case RADIO4RXBUFF_RXEN:
1260	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(1);
1261
1262	sendACK(packetNo, command);
1263	break;
1264	#endif
1265
1266	case RADIO1RXBUFF_RXDIS:
1267	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0);
1268
1269	sendACK(packetNo, command);
1270	break;
1271
1272	case RADIO2RXBUFF_RXDIS:
1273	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0);
1274
1275	sendACK(packetNo, command);
1276	break;
1277
1278	#ifdef WARPLAB_CONFIG_4RF
1279	case RADIO3RXBUFF_RXDIS:
1280	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0);
1281
1282	sendACK(packetNo, command);
1283	break;
1284
1285	case RADIO4RXBUFF_RXDIS:
1286	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0);
1287
1288	sendACK(packetNo, command);
1289	break;
1290	#endif
1291
1292	case RX_DONECHECK:
1293
1294	sendPtr32[0] = packetNo + 1;
1295	sendPtr32[1] = ACK;
1296	sendPtr32[2] = command;
1297
1298	if(warplab_mimo_ReadReg_CaptureDone(WARPLAB_BASEADDR) == 0)
1299	sendPtr32[3] = 0;
1300	else
1301	sendPtr32[3] = 1;
1302
1303	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1304	break;
1305
1306	case RX_DONEREADING:
1307	//warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 1);
1308	//warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 0);
1309
1310	sendACK(packetNo, command);
1311	break;
1312
1313	case RX_START:
1314	//if(DEBUG_LVL > 1) xil_printf("Starting Rx\n");
1315	//if(DEBUG_LVL > 1) xil_printf("Starting Rx\n");
1316	sendACK(packetNo, command);
1317
1318	if(waitForSync() == 0)
1319	{
1320	warplab_buffers_WriteReg_StartCapture(1);
1321	warplab_AGC_Start();
1322	warplab_buffers_WriteReg_StartCapture(0);
1323
1324	//if(DEBUG_LVL > 1) xil_printf("Capture started\n");
1325	}
1326	else
1327	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Rx Capture\n");
1328	break;
1329
1330	case TX_START:
1331	//if(DEBUG_LVL > 1) xil_printf("Starting Tx\n");
1332	if(DEBUG_LVL > 1) xil_printf("Starting Tx\n");
1333	sendACK(packetNo, command);
1334
1335	if(waitForSync() == 0)
1336	{
1337	warplab_buffers_WriteReg_StartTx(1);
1338	warplab_buffers_WriteReg_StartTx(0);
1339	//if(DEBUG_LVL > 1) xil_printf("Transmit started\n");
1340	}
1341	else
1342	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Tx\n");
1343	break;
1344
1345	case TX_STOP:
1346	sendACK(packetNo, command);
1347
1348	warplab_buffers_WriteReg_StopTx(1);
1349	warplab_buffers_WriteReg_StopTx(0);
1350
1351	break;
1352
1353	case TXRX_START:
1354	if(DEBUG_LVL > 1) xil_printf("Starting TxRX\n");
1355	sendACK(packetNo, command);
1356
1357	if(waitForSync() == 0)
1358	{
1359	warplab_buffers_WriteReg_StartTxRx(1);
1360	warplab_buffers_WriteReg_StartTxRx(0);
1361	}
1362	else
1363	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling TxRx\n");
1364	break;
1365
1366	case READ_AGC_DONE_ADDR:
1367	sendPtr32[0] = packetNo + 1;
1368	sendPtr32[1] = ACK;
1369	sendPtr32[2] = command;
1370
1371	sendPtr32[3] = warplab_mimo_ReadReg_AGCDoneAddr(WARPLAB_BASEADDR);
1372
1373	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1374	break;
1375
1376	case READ_RADIO1AGCDONERSSI:
1377	sendPtr32[0] = packetNo + 1;
1378	sendPtr32[1] = ACK;
1379	sendPtr32[2] = command;
1380
1381	sendPtr32[3] = warplab_mimo_ReadReg_Radio1AGCDoneRSSI(WARPLAB_BASEADDR);
1382
1383	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1384	break;
1385
1386	case READ_RADIO2AGCDONERSSI:
1387	sendPtr32[0] = packetNo + 1;
1388	sendPtr32[1] = ACK;
1389	sendPtr32[2] = command;
1390
1391	sendPtr32[3] = warplab_mimo_ReadReg_Radio2AGCDoneRSSI(WARPLAB_BASEADDR);
1392
1393	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1394	break;
1395
1396	#ifdef WARPLAB_CONFIG_4RF
1397	case READ_RADIO3AGCDONERSSI:
1398	sendPtr32[0] = packetNo + 1;
1399	sendPtr32[1] = ACK;
1400	sendPtr32[2] = command;
1401
1402	sendPtr32[3] = warplab_mimo_ReadReg_Radio3AGCDoneRSSI(WARPLAB_BASEADDR);
1403
1404	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1405	break;
1406
1407	case READ_RADIO4AGCDONERSSI:
1408	sendPtr32[0] = packetNo + 1;
1409	sendPtr32[1] = ACK;
1410	sendPtr32[2] = command;
1411
1412	sendPtr32[3] = warplab_mimo_ReadReg_Radio4AGCDoneRSSI(WARPLAB_BASEADDR);
1413	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1414	break;
1415	#endif
1416
1417	case AGC_RESET:
1418	warplab_AGC_Reset();
1419	sendACK(packetNo, command);
1420	break;
1421
1422	case READ_AGC_GAINS:
1423	sendPtr32[0] = packetNo + 1;
1424	sendPtr32[1] = ACK;
1425	sendPtr32[2] = command;
1426
1427	sendPtr32[3] = warplab_AGC_GetGains();
1428
1429	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1430	break;
1431
1432	case SET_AGC_TARGET_dBm:
1433	agctarget = (int)receivePtr32[2];
1434	warplab_AGC_SetTarget(agctarget);
1435	//xil_printf("agctarget = %d\n",agctarget);
1436	sendACK(packetNo, command);
1437	break;
1438
1439	case SET_AGC_DCO_EN_DIS:
1440	agc_dco_state = (unsigned int)receivePtr32[2];
1441	warplab_AGC_SetDCO(agc_dco_state);
1442	warplab_buffers_WriteReg_DCO_EN_SEL(agc_dco_state);
1443	//xil_printf("agc_dco_state = %d\n",agc_dco_state);
1444	sendACK(packetNo, command);
1445	break;
1446
1447	case SET_AGC_NOISEEST_dBm:
1448	agcnoiseEst = (int)receivePtr32[2];
1449	warplab_AGC_setNoiseEstimate(agcnoiseEst);
1450	//xil_printf("agctarget = %d\n",agctarget);
1451	sendACK(packetNo, command);
1452	break;
1453
1454	case SET_AGC_THRESHOLDS:
1455	warplab_AGC_WriteReg_Thresholds((unsigned int)receivePtr32[2]);
1456	sendACK(packetNo, command);
1457	break;
1458
1459	case SET_AGC_TRIG_DELAY:
1460	warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)receivePtr32[2]);
1461	sendACK(packetNo, command);
1462	break;
1463
1464	case READ_AGC_THRESHOLDS:
1465	sendPtr32[0] = packetNo + 1;
1466	sendPtr32[1] = ACK;
1467	sendPtr32[2] = command;
1468
1469	sendPtr32[3] = warplab_AGC_ReadReg_Thresholds(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1470
1471	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1472	break;
1473
1474	case CLOSE:
1475	if(DEBUG_LVL > 1) xil_printf("Closing sockets.\n");
1476	sendACK(packetNo, command);
1477	done = 1;
1478
1479	break;
1480
1481	case TX_TEST:
1482	if(DEBUG_LVL > 1) xil_printf("Starting Tx Test\n");
1483	sendACK(packetNo, command);
1484
1485	break;
1486
1487	default:
1488	if(DEBUG_LVL > 1) xil_printf("Received command (%d) is not recognized. Please retry transmission.\n", command);
1489
1490	sendPtr32[0] = packetNo + 1;
1491	sendPtr32[1] = NOACK;
1492	bytesSend = 8;
1493	xilsock_sendto(sock, sendBuffer, bytesSend, (struct sockaddr *)&addr, alen);
1494	}
1495	}
1496	}
1497
1498	shut_socket();
1499
1500	return 0;
1501	}
1502
1503	void sendACK(unsigned int packetNo, unsigned int commandToACK)
1504	{
1505	sendPtr32[0] = packetNo + 1;
1506	sendPtr32[1] = ACK;
1507	sendPtr32[2] = commandToACK;
1508	xilsock_sendto(sock, sendBuffer, 12, (struct sockaddr *)&addr, alen);
1509	return;
1510	}
1511
1512	unsigned char sevenSegmentMap(unsigned char x)
1513	{
1514	switch(x)
1515	{
1516	case(0x0) : return 0x007E;
1517	case(0x1) : return 0x0030;
1518	case(0x2) : return 0x006D;
1519	case(0x3) : return 0x0079;
1520	case(0x4) : return 0x0033;
1521	case(0x5) : return 0x005B;
1522	case(0x6) : return 0x005F;
1523	case(0x7) : return 0x0070;
1524	case(0x8) : return 0x007F;
1525	case(0x9) : return 0x007B;
1526
1527	case(0xA) : return 0x0077;
1528	case(0xB) : return 0x007F;
1529	case(0xC) : return 0x004E;
1530	case(0xD) : return 0x007E;
1531	case(0xE) : return 0x004F;
1532	case(0xF) : return 0x0047;
1533	default : return 0x0000;
1534	}
1535	}
1536
1537	#define XPAR_EEPROM_CONTROLLER_BASEADDR XPAR_EEPROM_CONTROLLER_MEM0_BASEADDR
1538	//New TxDCO calibration code
1539	int warpphy_applyTxDCOCalibration(unsigned int radioSelection)
1540	{
1541	#if 0
1542	int eepromStatus = 0;
1543	short calReadback = 0;
1544	signed short best_I, best_Q;
1545	unsigned char radioNum;
1546	Xuint8 memory[8], version, revision, valid, i;
1547	Xuint16 serial;
1548
1549	//Radio selection will be 0x11111111, 0x22222222, 0x44444444 or 0x88888888
1550	// corresponding to radios in slots 1, 2, 3 or 4
1551	// We need the slot number to initialize the EEPROM
1552	radioNum = (radioSelection & 0xF) == 1 ? 1 : ( (radioSelection & 0xF) == 2 ? 2 : ( (radioSelection & 0xF) == 4 ? 3 : 4 ) );
1553	if(DEBUG_LVL>2) xil_printf("Applying TxDCO correction for radio %d\n", radioNum);
1554
1555	//Mimic the radio test code, in hopes of a more stable EEPROM read...
1556	//Choose the EEPROM on the selected radio board; second arg is [0,1,2,3,4] for [FPGA, radio1, radio2, radio3, radio4]
1557	eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR, 0);
1558	if(eepromStatus != 0)
1559	{
1560	if(DEBUG_LVL>2) xil_printf("EEPROM Select Failed!\n");
1561	return -1;
1562	}
1563
1564	//Initialize the EEPROM controller
1565	eepromStatus = WarpEEPROM_Initialize((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR);
1566	if(eepromStatus != 0)
1567	{
1568	if(DEBUG_LVL>2) xil_printf("EEPROM Init Returned %x\n", eepromStatus);
1569	if(DEBUG_LVL>2) xil_printf("EEPROM Init Failed!\n");
1570	return -1;
1571	}
1572
1573	//Select the EEPROM on the current radio board
1574	eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, radioNum);
1575
1576	if(eepromStatus != 0)
1577	{
1578	if(DEBUG_LVL>2) xil_printf("TxDCO: EEPROM error\n");
1579	return -1;
1580	}
1581
1582	//Read the first page from the EERPOM
1583	WarpEEPROM_ReadMem((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 0, 0, memory);
1584	version = (memory[0] & 0xE0) >> 5;
1585	revision = (memory[1] & 0xE0) >> 5;
1586	valid = memory[1] & 0x1F;
1587
1588	if(DEBUG_LVL>2) xil_printf("\n\nEEPROM Values for Radio Board in Slot %d\n", radioNum);
1589
1590	if(DEBUG_LVL>2) xil_printf(" WARP Radio Board Version %d.%d\n", version, revision);
1591
1592	serial = WarpEEPROM_ReadWARPSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR);
1593
1594	if(DEBUG_LVL>2) xil_printf(" Serial Number (WARP): WR-a-%05d\n", serial);
1595
1596	WarpEEPROM_ReadDSSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, memory);
1597	if(DEBUG_LVL>2) print(" EEPROM Hard-wired Serial Number: ");
1598	if(DEBUG_LVL>2){
1599	for(i=1;i<7;i++)
1600	xil_printf(" %x",memory[7-i]);
1601	xil_printf("\n\n");
1602	}
1603	//Read the Tx DCO values
1604	calReadback = WarpEEPROM_ReadRadioCal((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 2, 1);
1605
1606	//Scale the stored values
1607	best_I = (signed short)(((signed char)(calReadback & 0xFF))<<1);
1608	best_Q = (signed short)(((signed char)((calReadback>>8) & 0xFF))<<1);
1609
1610	if(DEBUG_LVL>2) xil_printf("TxDCO: Applied values to radio %d - I: %d\tQ: %d\n", radioNum, best_I, best_Q);
1611
1612	//Finally, write the Tx DCO values to the DAC
1613	WarpRadio_v1_DACOffsetAdj(ICHAN, best_I, radioSelection);
1614	WarpRadio_v1_DACOffsetAdj(QCHAN, best_Q, radioSelection);
1615	#endif
1616	return 0;
1617	}
1618
1619
1620	void warplab_AGC_Reset()
1621	{
1622	// Cycle the agc's software reset port
1623
1624	warplab_AGC_WriteReg_SRESET_IN(1);
1625	usleep(10);
1626	warplab_AGC_WriteReg_SRESET_IN(0);
1627	usleep(100);
1628
1629	return;
1630	}
1631
1632	void warplab_AGC_MasterReset()
1633	{
1634	// Cycle the master reset register in the AGC and enable it
1635
1636	warplab_AGC_WriteReg_AGC_EN(0);
1637	usleep(10);
1638	warplab_AGC_WriteReg_MRESET_IN(0);
1639	usleep(10);
1640	warplab_AGC_WriteReg_MRESET_IN(1);
1641	usleep(10);
1642	warplab_AGC_WriteReg_MRESET_IN(0);
1643	usleep(10);
1644	warplab_AGC_WriteReg_AGC_EN(1);
1645
1646	return;
1647	}
1648
1649	void warplab_AGC_Start()
1650	{
1651	// Cycle the agc's packet in port
1652	warplab_AGC_WriteReg_PACKET_IN(1);
1653	usleep(10);
1654	warplab_AGC_WriteReg_PACKET_IN(0);
1655	usleep(100);
1656
1657	return;
1658	}
1659
1660	void warplab_AGC_Initialize(int noise_estimate)
1661	{
1662	int g_bbset = 0;
1663
1664	// First set all standard parameters
1665
1666	// Turn off both resets and the master enable
1667	warplab_AGC_WriteReg_AGC_EN(0);
1668	warplab_AGC_WriteReg_SRESET_IN(0);
1669	warplab_AGC_WriteReg_MRESET_IN(0);
1670
1671	// An adjustment parameter
1672	warplab_AGC_WriteReg_ADJ(8);
1673
1674	// Timing for the DC-offset correction
1675	warplab_AGC_WriteReg_DCO_Timing(0x12001000);
1676
1677	// Initial baseband gain setting
1678	warplab_AGC_WriteReg_GBB_init(52);
1679
1680	// RF gain AGCstate thresholds
1681	warplab_AGC_WriteReg_Thresholds(0xD5CBA6);
1682
1683	// Overall AGC timing
1684	warplab_AGC_WriteReg_Timing(0x9A962A28);//0x826E3C0A;
1685
1686	// vIQ and RSSI average lengths
1687	warplab_AGC_WriteReg_AVG_LEN(0x10F); //103
1688
1689	// Disable DCO, disable DCO subtraction
1690	warplab_AGC_WriteReg_Bits(0x0);
1691
1692	// Compute and set the initial g_BB gain value from the noise estimate
1693	// The initial g_bb sets noise to -19 db, assuming 32 db RF gain
1694
1695	g_bbset = -19 - 32 - noise_estimate;
1696	warplab_AGC_WriteReg_GBB_init(g_bbset);
1697
1698	// Perform a master reset
1699	warplab_AGC_MasterReset();
1700
1701	// Agc is now reset and enabled, ready to go!
1702	return;
1703	}
1704
1705	void warplab_AGC_setNoiseEstimate(int noise_estimate)
1706	{
1707	int g_bbset;
1708
1709	g_bbset = -19 - 32 - noise_estimate;
1710
1711	warplab_AGC_WriteReg_GBB_init(g_bbset);
1712
1713	return;
1714	}
1715
1716	unsigned int warplab_AGC_GetGains(void)
1717	{
1718	unsigned int gBB_A, gRF_A, gBB_B, gRF_B, gBB_C, gRF_C, gBB_D, gRF_D, gains;
1719
1720	// Get the gains from the registers
1721	gBB_A = warplab_AGC_ReadReg_GBB_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1722	gRF_A = warplab_AGC_ReadReg_GRF_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1723
1724	gBB_B = warplab_AGC_ReadReg_GBB_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1725	gRF_B = warplab_AGC_ReadReg_GRF_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1726
1727	gBB_C = warplab_AGC_ReadReg_GBB_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1728	gRF_C = warplab_AGC_ReadReg_GRF_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1729
1730	gBB_D = warplab_AGC_ReadReg_GBB_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1731	gRF_D = warplab_AGC_ReadReg_GRF_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1732
1733	// First concatenate the two radios together, into the gRF register
1734	// 2 lowest bits are RF, 5 higher bits are BB, last bit is unused
1735	// Multiply by 2^2, shift gBB right by 2 bits
1736
1737	gRF_A = gRF_A + (gBB_A * 4);
1738	gRF_B = gRF_B + (gBB_B * 4);
1739	gRF_C = gRF_C + (gBB_C * 4);
1740	gRF_D = gRF_D + (gBB_D * 4);
1741
1742	// Multiply by 2^8 shift gRF right by 8 bits
1743
1744	gains = gRF_A + (gRF_B * 256) + (gRF_C * 65536) + (gRF_D * 16777216);
1745
1746	return gains;
1747	}
1748
1749	void warplab_AGC_SetTarget(unsigned int target)
1750	{
1751	warplab_AGC_WriteReg_T_dB(target);
1752	return;
1753	}
1754
1755	void warplab_AGC_SetDCO(unsigned int AGCstate)
1756	{
1757	// Enables DCO and DCO subtraction (correction scheme and butterworth hipass are active)
1758
1759	unsigned int bits;
1760
1761	bits = warplab_AGC_ReadReg_Bits(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1762
1763	if(AGCstate)
1764	bits = bits \| 0x6;
1765	else
1766	bits = bits & 0x1;
1767
1768	warplab_AGC_WriteReg_Bits(bits);
1769
1770	return;
1771	}

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source: ResearchApps/PHY/WARPLAB/WARPLab_v6p2/C_Code_Reference/warp_v3/warplab.c

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