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warplab.c

Last change on this file was 1832, checked in by chunter, 12 years ago
adding software
File size: 56.8 KB

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1	////////////////////////////////////////////////////////////////////////////////
2	//
3	// File : warplab.c v6.2
4	// Date : 2012, August 30
5	// Author : P. Murphy, S. Gupta, M. Duarte, C. Hunter
6	//
7	// Changelog:
8	// - Fixed bug in handling of sync packets that causes jitter
9	// - Added diagnosis commands
10	// - Added support for WARPxilnet_v3_00 that adds support for the hard TEMACs
11	// inside the Virtex4
12	// - v2 WARP hardware will use gigabit speeds by default. The Ethernet PHY
13	// advertises its speed as gigabit, so there is no longer a need to
14	// explicitly tell your computer to send at 100Mbit.
15	// - Uses an XPS_Timer core to inact a timeout of WAITDURATION_SEC seconds
16	// to wait for a sync packet. Previously, this timeout was handled by
17	// waiting a set number of packets (e.g. 10 received packets).
18	// - Moved the sync IP address up to a proper broadcast address of X.X.X.255.
19	// This should obviate the need for explicit ARP table entries to handle
20	// sync packets. The v06 WARPLAB M-Code Reference has correspondingly been
21	// updated.
22	// - This source file will compile for either v1 or v2 WARP hardware
23	//
24	////////////////////////////////////////////////////////////////////////////////
25
26	#include "xparameters.h"
27	#include <xilnet_config.h>
28	#include <xilnet_xilsock.h>
29	#include <xilnet_mac.h>
30	#include "xstatus.h"
31	#include <stdlib.h>
32	#include <string.h>
33	#include "math.h"
34	#include "radio_controller_basic.h"
35	#include "radio_controller_ext.h"
36	#include "radio_controller_adv.h"
37	#include "radio_controller_5ghz.h"
38	#include "warplab_defines.h"
39	#include "EEPROM.h"
40	#include "warplab_regmacros.h"
41	#include "stdio.h"
42	#include "xtmrctr.h"
43	#include "warp_hw_ver.h"
44
45	#define WARPLAB_MAJOR_VER 6
46	#define WARPLAB_MINOR_VER 2
47
48	//#define WARPLAB_CONFIG_2RF 1 // Comment in if board in 2x2 configuration
49	#define WARPLAB_CONFIG_4RF 1 // Comment in if board in 4x4 configuration
50
51	//Includes for specific FPGA board versions
52	#ifdef WARP_HW_VER_v1
53	#include "warp_userio.h"
54	#include "xemaclite.h"
55	#include "xemaclite_l.h"
56	#include "xgpio.h"
57	static XGpio GPIO_UserIO; //Instantiates the general-purpose input-output peripheral driver
58	static XEmacLite EmacLiteInstance; /* Instance of the EmacLite */
59	static XEmacLite_Config *EmacLiteConfigPtr;
60	#define XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ 80000000 //The 10.1 tools don't automatically generate this
61	#endif
62
63	#ifdef WARP_HW_VER_v2
64	#define USERIO_BASEADDR XPAR_USERIO_BASEADDR
65	#include "warp_v4_userio.h"
66	#include "xlltemac.h"
67	#include "xllfifo.h"
68	#include "xdmacentral.h"
69	#include "xdmacentral_l.h"
70	static XDmaCentral DmaCentralInst;
71	static XDmaCentral_Config *DMAConfigPtr;
72	XLlTemac TemacInstance;
73	XLlTemac_Config *MacCfgPtr;
74	XLlFifo FifoInstance;
75	#endif
76
77	#define WARPLAB_TXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO1
78	#define WARPLAB_TXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO2
79	#define WARPLAB_TXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO3
80	#define WARPLAB_TXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO4
81	#define WARPLAB_RXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO1
82	#define WARPLAB_RXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO2
83	#define WARPLAB_RXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO3
84	#define WARPLAB_RXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO4
85	#define WARPLAB_RSSIBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO1
86	#define WARPLAB_RSSIBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO2
87	#define WARPLAB_RSSIBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO3
88	#define WARPLAB_RSSIBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO4
89
90	#define TEMAC_DEVICE_ID XPAR_LLTEMAC_0_DEVICE_ID
91	#define FIFO_DEVICE_ID XPAR_LLFIFO_0_DEVICE_ID
92
93	#define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID
94	#define TIMER_COUNTER_0 0
95
96
97	#ifdef WARP_HW_VER_v1
98
99	#define ENET_LINK_SPEED 100
100	#endif
101
102	#ifdef WARP_HW_VER_v2
103
104	#include "warp_v4_userio.h"
105	static XDmaCentral DmaCentralInst;
106	static XDmaCentral_Config *DMAConfigPtr;
107	XLlTemac TemacInstance;
108	XLlTemac_Config *MacCfgPtr;
109	XLlFifo FifoInstance;
110	#define USERIO_BASEADDR XPAR_USERIO_BASEADDR
111	#define ENET_LINK_SPEED 1000
112
113	#endif
114
115
116	#define BUFSIZE 2000
117	#define DEBUG_LVL 2
118
119	#define WAITDURATION_SEC 2
120
121	unsigned int sendPtr32[(BUFSIZE+3)/4];
122	unsigned char * const sendBuffer = (unsigned char *) sendPtr32;
123	unsigned int receivePtr32[(BUFSIZE+3)/4];
124	unsigned char * const receiveBuffer = (unsigned char *) receivePtr32;
125	unsigned int myPort;
126
127	u8 numSync;
128	u8 hw_generation;
129	u8 numRadios;
130
131	XTmrCtr TmrCtrInstance;
132
133	int sock; // UDP socket
134	struct sockaddr_in addr;
135	unsigned int alen = 0;
136	char node;
137
138	unsigned int ReadWrite;
139	unsigned char Radios_WirelessChan;
140	unsigned char Radios_Tx_LPF_Corn_Freq;
141	unsigned char Radios_Rx_LPF_Corn_Freq;
142	unsigned char Radio1_TxGain_BB, Radio1_TxGain_RF, Radio1_RxGain_BB, Radio1_RxGain_RF;
143	unsigned char Radio2_TxGain_BB, Radio2_TxGain_RF, Radio2_RxGain_BB, Radio2_RxGain_RF;
144	unsigned char Radio3_TxGain_BB, Radio3_TxGain_RF, Radio3_RxGain_BB, Radio3_RxGain_RF;
145	unsigned char Radio4_TxGain_BB, Radio4_TxGain_RF, Radio4_RxGain_BB, Radio4_RxGain_RF;
146
147	#ifdef WARPLAB_CONFIG_2RF
148	unsigned int radios = RADIO2_ADDR \| RADIO3_ADDR;
149	#elif defined WARPLAB_CONFIG_4RF
150	unsigned int radios = RADIO1_ADDR \| RADIO2_ADDR \| RADIO3_ADDR \| RADIO4_ADDR;
151	#endif
152	unsigned int radio1 = RADIO1_ADDR;
153	unsigned int radio2 = RADIO2_ADDR;
154	unsigned int radio3 = RADIO3_ADDR;
155	unsigned int radio4 = RADIO4_ADDR;
156
157	unsigned int AgcIsDoneAddr;
158	unsigned int MGC_AGC_Sel_Variable = 0; // By default MGC is selected
159
160	//----------------------------------
161	// Functions
162	void sendACK(unsigned int packetNo, unsigned int commandToACK);
163	unsigned char sevenSegmentMap(unsigned char x);
164	int warpphy_applyTxDCOCorrection(unsigned int radioSelection);
165	void warplab_AGC_Reset();
166	void warplab_AGC_MasterReset();
167	void warplab_AGC_Start();
168	void warplab_AGC_Initialize(int noise_estimate);
169	void warplab_AGC_setNoiseEstimate(int noise_estimate);
170	unsigned int warplab_AGC_GetGains(void);
171	void warplab_AGC_SetTarget(unsigned int target);
172	void warplab_AGC_SetDCO(unsigned int AGCstate);
173	int warpphy_applyTxDCOCalibration(unsigned int radioSelection);
174	// In WARPLab there is no decimation filter in the AGC, there is a downsampling only, so in WARPLab a function equivalent to
175	// ofdm_AGC_FiltSel is not needed
176
177	void init_net() {
178	XStatus Status;
179	xil_printf("Configuring network\n\r");
180
181	mb_hw_addr[0] = 0x00;
182	mb_hw_addr[1] = 0x50;
183	mb_hw_addr[2] = 0xc2;
184	mb_hw_addr[3] = 0x63;
185	mb_hw_addr[4] = 0x36;
186	mb_hw_addr[5] = node+0x63;
187
188	mb_ip_addr[0] = 10;
189	mb_ip_addr[1] = 0;
190	mb_ip_addr[2] = 0;
191	mb_ip_addr[3] = node+1;
192
193	//Define the last octet of the IP address used for SYNC packets. The first three will be the mb_ip_addr.
194	sync_IP_octet = 255;
195
196	myPort = 9000 + node;
197
198	xilnet_eth_init_hw_addr_tbl();
199
200	#ifdef WARP_HW_VER_v1
201	// Initialize the MAC OPB base address (MAC driver in net/mac.c)
202	xilnet_mac_init(XPAR_ETHERNET_MAC_BASEADDR);
203	// xemac_l.h
204
205	/***********************Ethernet*************************/
206	if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet");
207	//Initialize the EMAC config struct
208	EmacLiteConfigPtr = XEmacLite_LookupConfig(XPAR_EMACLITE_0_DEVICE_ID);
209	if (EmacLiteConfigPtr == NULL){
210	xil_printf("... ... EMAClite LookupConfig failed!\n");
211	return;
212	}
213
214	Status = XEmacLite_CfgInitialize(&EmacLiteInstance, EmacLiteConfigPtr, EmacLiteConfigPtr->BaseAddress);
215	if (Status != XST_SUCCESS){
216	xil_printf("... ... EMAClite CfgInitialize failed!\n");
217	return;
218	}
219
220	XEmacLite_SetMacAddress(&EmacLiteInstance, mb_hw_addr);
221
222	XEmacLite_FlushReceive(&EmacLiteInstance);
223	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
224	/************************************************************/
225	#endif
226	#ifdef WARP_HW_VER_v2
227	if(DEBUG_LVL > 1) xil_printf("... initializing DMA\n");
228	/************************DMA*****************************/
229	//Lookup the DMA configuration information
230	DMAConfigPtr = XDmaCentral_LookupConfig(XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID);
231
232	//Initialize the config struct
233	Status = XDmaCentral_CfgInitialize(&DmaCentralInst, DMAConfigPtr, DMAConfigPtr->BaseAddress);
234	if (Status != XST_SUCCESS){
235	xil_printf("... ... DMA CfgInitialize failed!\n");
236	return;
237	}
238
239	//Disable Interrupts
240	XDmaCentral_InterruptEnableSet(&DmaCentralInst, 0);
241	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
242	/************************************************************/
243
244	/*****************Ethernet********************************/
245	if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet\n");
246	MacCfgPtr = XLlTemac_LookupConfig(TEMAC_DEVICE_ID);
247	Status = XLlTemac_CfgInitialize(&TemacInstance, MacCfgPtr, MacCfgPtr->BaseAddress);
248	XLlFifo_Initialize(&FifoInstance, XLlTemac_LlDevBaseAddress(&TemacInstance));
249	if (Status != XST_SUCCESS)
250	xil_printf("... ... EMAC init error\n");
251
252	if (!XLlTemac_IsFifo(&TemacInstance))
253	xil_printf("... ... EMAC hw config incorrect\n");
254
255
256
257	Status = XLlTemac_ClearOptions(&TemacInstance, XTE_LENTYPE_ERR_OPTION \| XTE_FLOW_CONTROL_OPTION \| XTE_FCS_STRIP_OPTION);// \| XTE_MULTICAST_OPTION);
258	Status \|= XLlTemac_SetOptions(&TemacInstance, XTE_PROMISC_OPTION \| XTE_MULTICAST_OPTION \| XTE_BROADCAST_OPTION \| XTE_RECEIVER_ENABLE_OPTION \| XTE_TRANSMITTER_ENABLE_OPTION); //\| XTE_JUMBO_OPTION
259	if (Status != XST_SUCCESS)
260	xil_printf("... ... Error setting EMAC options\n, code %d", Status);
261
262	// Make sure the TEMAC is ready
263	Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET);
264	while ((Status & XTE_RDY_HARD_ACS_RDY_MASK) == 0)
265	{
266	Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET);
267	}
268
269	XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED);
270	usleep(1 * 10000);
271
272	XLlTemac_Start(&TemacInstance);
273	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
274	/************************************************************/
275
276	// Initialize the MAC OPB base address (MAC driver in net/mac.c)
277	xilnet_mac_init((void )&FifoInstance,(void )&DmaCentralInst);
278	#endif
279
280	if(DEBUG_LVL > 1) xil_printf("... complete!\n");
281	// Print IP address
282	if(DEBUG_LVL > 0) xil_printf("IP Address: %d.%d.%d.%d \n\r", mb_ip_addr[0], mb_ip_addr[1],mb_ip_addr[2],mb_ip_addr[3]);
283	}
284
285
286	void init_socket() {
287
288	sock = xilsock_socket(AF_INET, SOCK_DGRAM, 0); // Create UDP socket with domain Internet and UDP connection.
289	if (sock == -1) {
290	if(DEBUG_LVL > 0) xil_printf("Error in creating socket\n");
291	exit(-1);
292	}
293
294	addr.sin_family = AF_INET;
295	addr.sin_port = myPort;
296	addr.sin_addr.s_addr = INADDR_ANY; // Create the input socket with any incoming address. (0x00000000)
297
298	XStatus bind = xilsock_bind(sock, (struct sockaddr *)&addr, sizeof(struct sockaddr));
299	if (bind == -1) {
300	if(DEBUG_LVL > 0) xil_printf("Unable to bind socket\n");
301	exit(-1);
302	}
303	alen = sizeof(struct sockaddr);
304	if(DEBUG_LVL > 0) xil_printf("Listening on UDP port %d.\n", myPort);
305	}
306
307	void shut_socket() {
308	xilsock_close(sock);
309	}
310
311	int waitForSync()
312	{
313	unsigned int n;
314
315	XTmrCtr_Start(&TmrCtrInstance, TMRCTR_DEVICE_ID);
316
317	while(XTmrCtr_GetValue(&TmrCtrInstance, TMRCTR_DEVICE_ID) < (WAITDURATION_SEC*XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ)){
318	n = xilnet_eth_recv_frame(receiveBuffer, BUFSIZE);
319	if(n==9999)
320	{
321	numSync++;
322	return 0;
323	}
324	}
325
326	XTmrCtr_Stop(&TmrCtrInstance, TMRCTR_DEVICE_ID);
327
328	xil_printf("NoSync\n");
329	return 1;
330	}
331
332	int main() {
333
334	int bytesReceived;
335	int bytesSend;
336	int command;
337	int packetNo;
338	unsigned int rxArg0;
339	char done = 0;
340	unsigned char sevenSeg1 = 0x1;
341	int agctarget = -14;
342	int agcnoiseEst = -95;
343	unsigned int agc_dco_state;
344
345
346	#ifdef WARP_HW_VER_v1
347	unsigned int LEDHEX_Outputs = 0;
348	//Initialize the driver instance for the GPIO core attached to the FPGA board's user I/O (switches, LEDs, etc)
349	XGpio_Initialize(&GPIO_UserIO, XPAR_USER_IO_DEVICE_ID);
350
351	//We use both channels in the GPIO core- one for inputs, one for outputs
352	//A '1' in a bit position in the third argument marks the bit as an input
353	XGpio_SetDataDirection(&GPIO_UserIO, USERIO_CHAN_INPUTS, USERIO_MASK_INPUTS);
354	XGpio_SetDataDirection(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, 0);
355
356	//Make sure the LEDs are all off by default
357	XGpio_DiscreteClear(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, USERIO_MASK_OUTPUTS);
358
359	//Read the 4-bit DIP switch, and use its value as this node's ID
360	node = USERIO_MAP_DIPSW(XGpio_DiscreteRead(&GPIO_UserIO, USERIO_CHAN_INPUTS) & USERIO_MASK_INPUTS);
361
362	//Display the node's ID + 1 (to match the IP address) on the right hex display
363	LEDHEX_Outputs = (
364	USERIO_MAP_LEDS(0) \|
365	USERIO_MAP_DISPR(sevenSegmentMap(node+1)) \|
366	USERIO_MAP_DISPL(sevenSeg1)
367	);
368	XGpio_DiscreteSet(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, LEDHEX_Outputs);
369
370	#endif
371	#ifdef WARP_HW_VER_v2
372	//Set the modes for the three hex displays
373	WarpV4_UserIO_NumberMode_LeftHex(USERIO_BASEADDR);
374	WarpV4_UserIO_NumberMode_MiddleHex(USERIO_BASEADDR);
375	WarpV4_UserIO_RawMode_RightHex(USERIO_BASEADDR);
376
377	//Read the 4-bit DIP switch and use its value as this node's ID
378	node = WarpV4_UserIO_DipSw(USERIO_BASEADDR);
379
380	//Write the 2-digit node ID to the left and middle hex displays
381	WarpV4_UserIO_WriteNumber_LeftHex(USERIO_BASEADDR, (node+1)/10, 0);
382	WarpV4_UserIO_WriteNumber_MiddleHex(USERIO_BASEADDR, (node+1)%10, 0);
383	#endif
384
385	//Initialize the xilnet stack & default sockets
386	init_net();
387	init_socket();
388
389	#ifdef WARP_HW_VER_v3
390	hw_generation = 3;
391	#elif defined WARP_HW_VER_v2
392	hw_generation = 2;
393	#elif defined WARP_HW_VER_v1
394	hw_generation = 1;
395	#endif
396
397	#ifdef WARPLAB_CONFIG_2RF
398	numRadios = 2;
399	#elif defined WARPLAB_CONFIG_4RF
400	numRadios = 4;
401	#endif
402
403	//Initialize the radio transceivers
404	WarpRadio_v1_Reset((unsigned int*)XPAR_RADIO_CONTROLLER_0_BASEADDR, 2);
405	WarpRadio_v1_SetCenterFreq2GHz(11, radios);
406	WarpRadio_v1_SoftwareTxGainControl(1, radios);
407	//By default, MGC (Manual Gain Control) is enabled. AGC is not enabled by default
408	WarpRadio_v1_SoftwareRxGainControl(1, radios);
409	WarpRadio_v1_RxHpSoftControlEnable(radios);
410	//Set Rx bandwidth to nominal mode
411	Radios_Tx_LPF_Corn_Freq = 1;
412	WarpRadio_v1_RxLpfCornFreqCoarseAdj(Radios_Tx_LPF_Corn_Freq, radios);
413	//Set Tx bandwidth to nominal mode
414	Radios_Rx_LPF_Corn_Freq = 1;
415	WarpRadio_v1_TxLpfCornFreqCoarseAdj(Radios_Rx_LPF_Corn_Freq, radios);
416
417	//Apply the stored TX DC offset correction values for each radio
418	warpphy_applyTxDCOCalibration(RADIO2_ADDR);
419	warpphy_applyTxDCOCalibration(RADIO3_ADDR);
420	#ifdef WARPLAB_CONFIG_4RF
421	warpphy_applyTxDCOCalibration(RADIO1_ADDR);
422	warpphy_applyTxDCOCalibration(RADIO4_ADDR);
423	#endif
424
425	///Timer Setup///
426	XTmrCtr_Initialize(&TmrCtrInstance, TMRCTR_DEVICE_ID);
427	XTmrCtr_SetResetValue(&TmrCtrInstance,TMRCTR_DEVICE_ID,0); //Sets it so issuing a "start" command begins at counter=0
428	/////////////////
429
430
431	#ifdef WARPLAB_CONFIG_2RF
432	xil_printf("WARPLabv06_2 2RF Started - Waiting for connection from MATLAB\n");
433	#elif defined WARPLAB_CONFIG_4RF
434	xil_printf("WARPLabv06_2 4RF Started - Waiting for connection from MATLAB\n");
435	#endif
436
437	#ifdef WARP_HW_VER_v2
438	XLlFifo_Reset(&FifoInstance);
439	#endif
440
441	while(done == 0) {
442
443	if(DEBUG_LVL > 3) xil_printf("\|");
444
445	bytesReceived = xilsock_recvfrom(sock, receiveBuffer, BUFSIZE, (struct sockaddr *)&addr, &alen); // Wait to receive data
446
447	if (bytesReceived > 0) { // Check for valid packet
448
449	packetNo = receivePtr32[0];
450	command = receivePtr32[1];
451	rxArg0 = receivePtr32[2];
452
453	//Rotate the single active bit
454	sevenSeg1 = ( ((sevenSeg1<<1)&0x7E) \| ((sevenSeg1>>5)&0x7E) );
455
456	#ifdef WARP_HW_VER_v1
457	//Update the hex displays to show the new values
458	LEDHEX_Outputs = (
459	USERIO_MAP_LEDS(0) \|
460	USERIO_MAP_DISPR(sevenSegmentMap(node+1)) \|
461	USERIO_MAP_DISPL(sevenSeg1)
462	);
463	XGpio_DiscreteSet(&GPIO_UserIO, USERIO_CHAN_OUTPUTS, LEDHEX_Outputs);
464	#endif
465	#ifdef WARP_HW_VER_v2
466	WarpV4_UserIO_WriteRaw_RightHex(USERIO_BASEADDR, sevenSeg1<<1);
467	#endif
468	if(DEBUG_LVL > 2) xil_printf("=============\nPacket Received\n Length: %d\n Packet No.: %d\n Command No: %d\n", bytesReceived, packetNo, command);
469
470	switch(command) { // Decode on incoming command
471
472	case INITIALIZE:
473	//if(DEBUG_LVL > 1) xil_printf("Initializing Node...");
474	warplab_buffers_WriteReg_TxDelay(0);
475	warplab_buffers_WriteReg_StartCapture(0);
476	warplab_buffers_WriteReg_TxLength((unsigned int)16383);
477	warplab_buffers_WriteReg_TransMode(0);
478	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0);
479	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0);
480	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0);
481	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0);
482	warplab_AGC_WriteReg_RADIO1_AGC_EN(0); // No radio on slot 1
483	warplab_AGC_WriteReg_RADIO2_AGC_EN(0);
484	warplab_AGC_WriteReg_RADIO3_AGC_EN(0);
485	warplab_AGC_WriteReg_RADIO4_AGC_EN(0); // No radio on slot 4
486	warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)50);
487	warplab_buffers_WriteReg_MGC_AGC_SEL(0);// Select MGC by default
488	warplab_AGC_WriteReg_AGC_EN(0);
489	MGC_AGC_Sel_Variable = 0;
490	#ifdef WARPLAB_CONFIG_4RF
491	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0);
492	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0);
493	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0);
494	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0);
495	#endif
496
497	sendACK(packetNo, command);
498	break;
499
500	case NETWORKCHECK:
501	sendPtr32[0] = packetNo + 1;
502	sendPtr32[1] = ACK;
503	sendPtr32[2] = command;
504	sendPtr32[3] = numSync;
505	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
506	numSync = 0;
507	waitForSync();
508	break;
509
510	case BOARDINFO:
511	sendPtr32[0] = packetNo + 1;
512	sendPtr32[1] = ACK;
513	sendPtr32[2] = command;
514	sendPtr32[3] = 99999;
515	sendPtr32[4] = 99999;
516	sendPtr32[5] = 99999;
517	sendPtr32[6] = (hw_generation<<24)\|(numRadios<<16)\|(WARPLAB_MAJOR_VER<<8)\|(WARPLAB_MINOR_VER);
518	xilsock_sendto(sock, sendBuffer, 28, (struct sockaddr *)&addr, alen);
519	break;
520
521	case TX_DELAY:
522
523	ReadWrite = (unsigned int)receivePtr32[2];
524	if(0 == ReadWrite)
525	{
526	sendPtr32[0] = packetNo + 1;
527	sendPtr32[1] = ACK;
528	sendPtr32[2] = command;
529
530	sendPtr32[3] = warplab_buffers_ReadReg_TxDelay(WARPLAB_BASEADDR);
531
532	if(DEBUG_LVL > 2) xil_printf("Read capt offset of %d\n", (unsigned int)receivePtr32[3]);
533	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
534	}
535	if(1 == ReadWrite)
536	{
537	//If the user requests a TX_DELAY that's too big, write the maximum instead
538	warplab_buffers_WriteReg_TxDelay((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]);
539	if(DEBUG_LVL > 2) xil_printf("Set capt offset to %d\n", (unsigned int)receivePtr32[3]);
540	sendACK(packetNo, command);
541	}
542
543	break;
544
545	case TX_LENGTH:
546	ReadWrite = (unsigned int)receivePtr32[2];
547	if(0 == ReadWrite)
548	{
549	sendPtr32[0] = packetNo + 1;
550	sendPtr32[1] = ACK;
551	sendPtr32[2] = command;
552
553	sendPtr32[3] = warplab_buffers_ReadReg_TxLength(WARPLAB_BASEADDR);
554
555	if(DEBUG_LVL > 2) xil_printf("Read TxLength of %d\n", (unsigned int)receivePtr32[3]);
556	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
557	}
558	if(1 == ReadWrite)
559	{
560	//If the user requests a TX_LENGTH that's too big, write the maximum instead
561	warplab_buffers_WriteReg_TxLength((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]);
562	if(DEBUG_LVL > 2) xil_printf("Set TxLength to %d\n", (unsigned int)receivePtr32[3]);
563	sendACK(packetNo, command);
564	}
565	break;
566
567	case TX_MODE:
568	ReadWrite = (unsigned int)receivePtr32[2];
569	if(0 == ReadWrite)
570	{
571	sendPtr32[0] = packetNo + 1;
572	sendPtr32[1] = ACK;
573	sendPtr32[2] = command;
574
575	sendPtr32[3] = warplab_buffers_ReadReg_TransMode(WARPLAB_BASEADDR);
576
577	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
578	}
579	if(1 == ReadWrite)
580	{
581	warplab_buffers_WriteReg_TransMode((unsigned int)receivePtr32[3]);
582	sendACK(packetNo, command);
583	}
584	break;
585
586	case MGC_AGC_SEL:
587	//ReadWrite = (unsigned int)receivePtr32[2];
588	MGC_AGC_Sel_Variable = (unsigned int)receivePtr32[2];
589	//if(0 == ReadWrite)
590	//{
591	// sendPtr32[0] = packetNo + 1;
592	// sendPtr32[1] = ACK;
593	// sendPtr32[2] = command;
594
595	// sendPtr32[3] = warplab_buffers_4x4_ReadReg_MGC_AGC_SEL(XPAR_WARPLAB_BUFFERS_PLBW_OPBW_0_BASEADDR);
596
597	// xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
598	//}
599	//if(1 == ReadWrite)
600	//{
601	warplab_buffers_WriteReg_MGC_AGC_SEL(MGC_AGC_Sel_Variable);
602
603	if(0 == MGC_AGC_Sel_Variable)
604	{
605	warplab_AGC_WriteReg_AGC_EN(0);
606	//Set Radios for Manual Gain Control (MGC)
607	WarpRadio_v1_SoftwareRxGainControl(1, radios);
608	WarpRadio_v1_RxHpSoftControlEnable(radios);
609	}
610	if(1 == MGC_AGC_Sel_Variable)
611	{
612	//Set Radios for Automatic Gain Control (AGC)
613	WarpRadio_v1_SoftwareRxGainControl(0, radios); // RxGains will be controlled by the AGC (AGC Change)
614	WarpRadio_v1_RxHpSoftControlDisable(radios); // RxHp will be controlled by the AGC (AGC Change)
615	WarpRadio_v1_RxHighPassCornerFreq(0, radios); // Will set the corner frequency when RxHp is 0? (AGC Change)
616	//xil_printf("agctargetINIT = %d\n",agctarget);
617	//Set Rx bandwidth; 19MHz
618	WarpRadio_v1_RxLpfCornFreqCoarseAdj(1, radios); // (AGC Change)
619
620	// Initialize the AGC
621	warplab_AGC_Initialize(agcnoiseEst);
622	warplab_AGC_setNoiseEstimate(agcnoiseEst);
623	// ofdm_AGC_FiltSel(0); No decimation option in WARPLab AGC
624	warplab_AGC_SetDCO(0);
625	warplab_AGC_SetTarget(agctarget);
626	warplab_AGC_Reset();
627	}
628
629	sendACK(packetNo, command);
630	//}
631	break;
632
633	case CARRIER_CHANNEL:
634	Radios_WirelessChan = ((unsigned int)receivePtr32[2]);
635
636	//Channels in [1...37] are valid
637	// Values in [1...14] select 2.4GHz channels [1...14]
638	// Values in [15...37] select a 5GHz channels [1...23]
639	if(Radios_WirelessChan <= (14+23))
640	{
641	if(Radios_WirelessChan <= 14)
642	WarpRadio_v1_SetCenterFreq2GHz(Radios_WirelessChan, radios);
643	else
644	WarpRadio_v1_SetCenterFreq5GHz((Radios_WirelessChan-14), radios);
645	}
646
647	sendACK(packetNo, command);
648	break;
649
650	case TX_LPF_CORN_FREQ:
651	Radios_Tx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]);
652	//xil_printf("Radios_Tx_LPF_Corn_Freq = %d\n",Radios_Tx_LPF_Corn_Freq);
653	WarpRadio_v1_TxLpfCornFreqCoarseAdj(Radios_Tx_LPF_Corn_Freq, radios);
654	sendACK(packetNo, command);
655	break;
656
657	case RX_LPF_CORN_FREQ:
658	Radios_Rx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]);
659	//xil_printf("Radios_Rx_LPF_Corn_Freq = %d\n",Radios_Rx_LPF_Corn_Freq);
660	WarpRadio_v1_RxLpfCornFreqCoarseAdj(Radios_Rx_LPF_Corn_Freq, radios);
661	sendACK(packetNo, command);
662	break;
663
664	#ifdef WARPLAB_CONFIG_4RF
665	case RADIO1_TXGAINS:
666	//Extract the radio gain config options from the received Ethernet packet
667	Radio1_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
668	Radio1_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
669	WarpRadio_v1_BaseBandTxGain(Radio1_TxGain_BB, radio1);
670	WarpRadio_v1_TxVGAGainControl(Radio1_TxGain_RF, radio1);
671	sendACK(packetNo, command);
672	break;
673
674	case RADIO1_RXGAINS:
675	//Extract the radio gain config options from the received Ethernet packet
676	Radio1_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
677	Radio1_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
678	WarpRadio_v1_RxLNAGainControl(Radio1_RxGain_RF, radio1);
679	WarpRadio_v1_RxVGAGainControl(Radio1_RxGain_BB, radio1);
680	sendACK(packetNo, command);
681	break;
682	#endif
683
684	case RADIO2_TXGAINS:
685	//Extract the radio gain config options from the received Ethernet packet
686	Radio2_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
687	Radio2_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
688	WarpRadio_v1_BaseBandTxGain(Radio2_TxGain_BB, radio2);
689	WarpRadio_v1_TxVGAGainControl(Radio2_TxGain_RF, radio2);
690	sendACK(packetNo, command);
691	break;
692
693	case RADIO2_RXGAINS:
694	//Extract the radio gain config options from the received Ethernet packet
695	Radio2_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
696	Radio2_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
697	WarpRadio_v1_RxLNAGainControl(Radio2_RxGain_RF, radio2);
698	WarpRadio_v1_RxVGAGainControl(Radio2_RxGain_BB, radio2);
699	sendACK(packetNo, command);
700	break;
701
702	case RADIO3_TXGAINS:
703	//Extract the radio gain config options from the received Ethernet packet
704	Radio3_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
705	Radio3_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
706	WarpRadio_v1_BaseBandTxGain(Radio3_TxGain_BB, radio3);
707	WarpRadio_v1_TxVGAGainControl(Radio3_TxGain_RF, radio3);
708	sendACK(packetNo, command);
709	break;
710
711	case RADIO3_RXGAINS:
712	//Extract the radio gain config options from the received Ethernet packet
713	Radio3_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
714	Radio3_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
715	WarpRadio_v1_RxLNAGainControl(Radio3_RxGain_RF, radio3);
716	WarpRadio_v1_RxVGAGainControl(Radio3_RxGain_BB, radio3);
717	sendACK(packetNo, command);
718	break;
719
720	#ifdef WARPLAB_CONFIG_4RF
721	case RADIO4_TXGAINS:
722	//Extract the radio gain config options from the received Ethernet packet
723	Radio4_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
724	Radio4_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
725	WarpRadio_v1_BaseBandTxGain(Radio4_TxGain_BB, radio4);
726	WarpRadio_v1_TxVGAGainControl(Radio4_TxGain_RF, radio4);
727	sendACK(packetNo, command);
728	break;
729
730	case RADIO4_RXGAINS:
731	//Extract the radio gain config options from the received Ethernet packet
732	Radio4_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
733	Radio4_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
734	WarpRadio_v1_RxLNAGainControl(Radio4_RxGain_RF, radio4);
735	WarpRadio_v1_RxVGAGainControl(Radio4_RxGain_BB, radio4);
736	sendACK(packetNo, command);
737	break;
738	#endif
739
740	#ifdef WARPLAB_CONFIG_4RF
741	case RADIO1_TXEN:
742	/*************** Setup the radio board **********/
743
744	WarpRadio_v1_BaseBandTxGain(Radio1_TxGain_BB, radio1);
745	WarpRadio_v1_TxVGAGainControl(Radio1_TxGain_RF, radio1);
746
747	//Enable the transmitter
748	WarpRadio_v1_TxEnable(radio1);
749	/*************** END Setup the radio board **********/
750
751	if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Enabled\n");
752	sendACK(packetNo, command);
753	break;
754	#endif
755
756	case RADIO2_TXEN:
757	/*************** Setup the radio board **********/
758
759	WarpRadio_v1_BaseBandTxGain(Radio2_TxGain_BB, radio2);
760	WarpRadio_v1_TxVGAGainControl(Radio2_TxGain_RF, radio2);
761
762	//Enable the transmitter
763	WarpRadio_v1_TxEnable(radio2);
764	/*************** END Setup the radio board **********/
765
766	if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Enabled\n");
767	sendACK(packetNo, command);
768	break;
769
770	case RADIO3_TXEN:
771	/*************** Setup the radio board **********/
772
773	WarpRadio_v1_BaseBandTxGain(Radio3_TxGain_BB, radio3);
774	WarpRadio_v1_TxVGAGainControl(Radio3_TxGain_RF, radio3);
775
776	//Enable the transmitter
777	WarpRadio_v1_TxEnable(radio3);
778	/*************** END Setup the radio board **********/
779
780	if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Enabled\n");
781	sendACK(packetNo, command);
782	break;
783
784	#ifdef WARPLAB_CONFIG_4RF
785	case RADIO4_TXEN:
786	/*************** Setup the radio board **********/
787
788	WarpRadio_v1_BaseBandTxGain(Radio4_TxGain_BB, radio4);
789	WarpRadio_v1_TxVGAGainControl(Radio4_TxGain_RF, radio4);
790
791	//Enable the transmitter
792	WarpRadio_v1_TxEnable(radio4);
793	/*************** END Setup the radio board **********/
794
795	if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Enabled\n");
796	sendACK(packetNo, command);
797	break;
798	#endif
799
800	#ifdef WARPLAB_CONFIG_4RF
801	case RADIO1_TXDIS:
802	WarpRadio_v1_TxRxDisable(radio1);
803	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\n");
804	if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\n");
805	sendACK(packetNo, command);
806	break;
807	#endif
808
809	case RADIO2_TXDIS:
810	WarpRadio_v1_TxRxDisable(radio2);
811	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\n");
812	if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\n");
813	sendACK(packetNo, command);
814	break;
815
816	case RADIO3_TXDIS:
817	WarpRadio_v1_TxRxDisable(radio3);
818	//if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Disabled\n");
819	if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Disabled\n");
820	sendACK(packetNo, command);
821	break;
822
823	#ifdef WARPLAB_CONFIG_4RF
824	case RADIO4_TXDIS:
825	WarpRadio_v1_TxRxDisable(radio4);
826	//if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Disabled\n");
827	if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Disabled\n");
828	sendACK(packetNo, command);
829	break;
830	#endif
831
832	#ifdef WARPLAB_CONFIG_4RF
833	case RADIO1_RXEN:
834	/*************** Setup the radio board **********/
835	if(0 == MGC_AGC_Sel_Variable)
836	{
837	// Disable the Rx HP filter
838	// Only needed in Manual Gain Control (MGC) Mode
839	// In Automatic Gain Control (AGC) Mode, the RxHp
840	// is controlled by the AGC core
841	WarpRadio_v1_RxHpDisable(radio1);
842	}
843
844	usleep(10);
845
846	//Enable the receiver
847	WarpRadio_v1_RxEnable(radio1);
848
849	if(1 == MGC_AGC_Sel_Variable)
850	{
851	//Enable this radio's AGC if user has set AGC Mode
852	warplab_AGC_WriteReg_RADIO1_AGC_EN(1);
853	}
854
855	/*************** END Setup the radio board **********/
856
857	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n");
858	if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n");
859	sendACK(packetNo, command);
860	break;
861	#endif
862
863	case RADIO2_RXEN:
864
865	/*************** Setup the radio board **********/
866	if(0 == MGC_AGC_Sel_Variable)
867	{
868	// Disable the Rx HP filter
869	// Only needed in Manual Gain Control (MGC) Mode
870	// In Automatic Gain Control (AGC) Mode, the RxHp
871	// is controlled by the AGC core
872	WarpRadio_v1_RxHpDisable(radio2);
873	}
874
875	usleep(10);
876
877	//Enable the receiver
878	WarpRadio_v1_RxEnable(radio2);
879
880	if(1 == MGC_AGC_Sel_Variable)
881	{
882	//Enable this radio's AGC if user has set AGC Mode
883	warplab_AGC_WriteReg_RADIO2_AGC_EN(1);
884	}
885
886	/*************** END Setup the radio board **********/
887
888	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n");
889	if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n");
890	sendACK(packetNo, command);
891	break;
892
893	case RADIO3_RXEN:
894
895	/*************** Setup the radio board **********/
896	if(0 == MGC_AGC_Sel_Variable)
897	{
898	// Disable the Rx HP filter
899	// Only needed in Manual Gain Control (MGC) Mode
900	// In Automatic Gain Control (AGC) Mode, the RxHp
901	// is controlled by the AGC core
902	WarpRadio_v1_RxHpDisable(radio3);
903	}
904
905	usleep(10);
906
907	//Enable the receiver
908	WarpRadio_v1_RxEnable(radio3);
909
910	if(1 == MGC_AGC_Sel_Variable)
911	{
912	//Enable this radio's AGC if user has set AGC Mode
913	warplab_AGC_WriteReg_RADIO3_AGC_EN(1);
914	}
915
916	/*************** END Setup the radio board **********/
917
918	//if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Enabled\n");
919	if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Enabled\n");
920	sendACK(packetNo, command);
921	break;
922
923	#ifdef WARPLAB_CONFIG_4RF
924	case RADIO4_RXEN:
925	/*************** Setup the radio board **********/
926	if(0 == MGC_AGC_Sel_Variable)
927	{
928	// Disable the Rx HP filter
929	// Only needed in Manual Gain Control (MGC) Mode
930	// In Automatic Gain Control (AGC) Mode, the RxHp
931	// is controlled by the AGC core
932	WarpRadio_v1_RxHpDisable(radio4);
933	}
934
935	usleep(10);
936
937	//Enable the receiver
938	WarpRadio_v1_RxEnable(radio4);
939
940	if(1 == MGC_AGC_Sel_Variable)
941	{
942	//Enable this radio's AGC if user has set AGC Mode
943	warplab_AGC_WriteReg_RADIO4_AGC_EN(1);
944	}
945
946	/*************** END Setup the radio board **********/
947
948	//if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Enabled\n");
949	if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Enabled\n");
950	sendACK(packetNo, command);
951	break;
952	#endif
953
954	#ifdef WARPLAB_CONFIG_4RF
955	case RADIO1_RXDIS:
956	WarpRadio_v1_TxRxDisable(radio1);
957
958	if(0 == MGC_AGC_Sel_Variable)
959	{
960	//Enable the Rx HP filter
961	// Only needed in Manual Gain Control (MGC) Mode
962	// In Automatic Gain Control (AGC) Mode, the RxHp
963	// is controlled by the AGC core
964	WarpRadio_v1_RxHpEnable(radio1);
965	}
966
967	if(1 == MGC_AGC_Sel_Variable)
968	{
969	//Disable this radio's AGC if user has set AGC Mode
970	warplab_AGC_WriteReg_RADIO1_AGC_EN(0);
971	}
972
973	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n");
974	if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n");
975	sendACK(packetNo, command);
976	break;
977	#endif
978
979	case RADIO2_RXDIS:
980	WarpRadio_v1_TxRxDisable(radio2);
981
982	if(0 == MGC_AGC_Sel_Variable)
983	{
984	//Enable the Rx HP filter
985	// Only needed in Manual Gain Control (MGC) Mode
986	// In Automatic Gain Control (AGC) Mode, the RxHp
987	// is controlled by the AGC core
988	WarpRadio_v1_RxHpEnable(radio2);
989	}
990
991	if(1 == MGC_AGC_Sel_Variable)
992	{
993	//Disable this radio's AGC if user has set AGC Mode
994	warplab_AGC_WriteReg_RADIO2_AGC_EN(0);
995	}
996
997	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n");
998	if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n");
999	sendACK(packetNo, command);
1000	break;
1001
1002	case RADIO3_RXDIS:
1003	WarpRadio_v1_TxRxDisable(radio3);
1004
1005	if(0 == MGC_AGC_Sel_Variable)
1006	{
1007	//Enable the Rx HP filter
1008	// Only needed in Manual Gain Control (MGC) Mode
1009	// In Automatic Gain Control (AGC) Mode, the RxHp
1010	// is controlled by the AGC core
1011	WarpRadio_v1_RxHpEnable(radio3);
1012	}
1013
1014	if(1 == MGC_AGC_Sel_Variable)
1015	{
1016	//Disable this radio's AGC if user has set AGC Mode
1017	warplab_AGC_WriteReg_RADIO3_AGC_EN(0);
1018	}
1019
1020	//if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n");
1021	if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n");
1022	sendACK(packetNo, command);
1023	break;
1024
1025	#ifdef WARPLAB_CONFIG_4RF
1026	case RADIO4_RXDIS:
1027	WarpRadio_v1_TxRxDisable(radio4);
1028
1029	if(0 == MGC_AGC_Sel_Variable)
1030	{
1031	//Enable the Rx HP filter
1032	// Only needed in Manual Gain Control (MGC) Mode
1033	// In Automatic Gain Control (AGC) Mode, the RxHp
1034	// is controlled by the AGC core
1035	WarpRadio_v1_RxHpEnable(radio4);
1036	}
1037
1038	if(1 == MGC_AGC_Sel_Variable)
1039	{
1040	//Disable this radio's AGC if user has set AGC Mode
1041	warplab_AGC_WriteReg_RADIO4_AGC_EN(0);
1042	}
1043
1044	//if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n");
1045	if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n");
1046	sendACK(packetNo, command);
1047	break;
1048	#endif
1049
1050	#ifdef WARPLAB_CONFIG_4RF
1051	case RADIO1_TXDATA:
1052	memcpy
1053	(
1054	(unsigned int )(WARPLAB_TXBUFF_RADIO1 + 4rxArg0),\
1055	(unsigned int *)(receivePtr32 + 3),\
1056	(bytesReceived-12)
1057	);
1058	sendACK(packetNo, command);
1059	break;
1060	#endif
1061
1062	case RADIO2_TXDATA:
1063	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
1064	//if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", (unsigned int )(receivePtr32 + 3), (unsigned int )(receivePtr32 + 4), (unsigned int )(receivePtr32 + 5), (unsigned int )(receivePtr32 + 6));
1065
1066	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
1067
1068	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
1069
1070	memcpy
1071	(
1072	(unsigned int )(WARPLAB_TXBUFF_RADIO2 + 4rxArg0),\
1073	(unsigned int *)(receivePtr32 + 3),\
1074	(bytesReceived-12)
1075	);
1076
1077	sendACK(packetNo, command);
1078	break;
1079
1080	case RADIO3_TXDATA:
1081	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0);
1082	//if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", (unsigned int )(receivePtr32 + 3), (unsigned int )(receivePtr32 + 4), (unsigned int )(receivePtr32 + 5), (unsigned int )(receivePtr32 + 6));
1083
1084	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0);
1085
1086	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 3 Tx (offset: %x)\n",rxArg0);
1087	/*
1088	memcpy
1089	(
1090	(unsigned int )(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMWO_TxBuff_Radio3_OFFSET + 4rxArg0),\
1091	(unsigned int *)(receivePtr32 + 3),\
1092	(bytesReceived-12)
1093	);
1094	*/
1095	memcpy
1096	(
1097	(unsigned int )(WARPLAB_TXBUFF_RADIO3 + 4rxArg0),\
1098	(unsigned int *)(receivePtr32 + 3),\
1099	(bytesReceived-12)
1100	);
1101	sendACK(packetNo, command);
1102	break;
1103
1104	#ifdef WARPLAB_CONFIG_4RF
1105	case RADIO4_TXDATA:
1106	memcpy
1107	(
1108	(unsigned int )(WARPLAB_TXBUFF_RADIO4 + 4rxArg0),\
1109	(unsigned int *)(receivePtr32 + 3),\
1110	(bytesReceived-12)
1111	);
1112	sendACK(packetNo, command);
1113	break;
1114	#endif
1115
1116	#ifdef WARPLAB_CONFIG_4RF
1117	case RADIO1_RXDATA:
1118	memcpy
1119	(
1120	(unsigned int *)(sendPtr32 + 4), \
1121	(unsigned int )(WARPLAB_RXBUFF_RADIO1 + 4rxArg0),\
1122	1024
1123	);
1124
1125	sendPtr32[0] = packetNo + 1;
1126	sendPtr32[1] = ACK;
1127	sendPtr32[2] = command;
1128	sendPtr32[3] = rxArg0;
1129	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1130	break;
1131	#endif
1132
1133	case RADIO2_RXDATA:
1134	//while(warplab_buffers_2x2_ReadReg_CaptureDone(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR) == 0) {}
1135
1136	/*
1137	memcpy
1138	(
1139	(unsigned int *)(sendPtr32 + 4), \
1140	(unsigned int )(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RxBuff_Radio2_OFFSET + 4rxArg0),\
1141	1024
1142	);
1143	*/
1144	memcpy
1145	(
1146	(unsigned int *)(sendPtr32 + 4), \
1147	(unsigned int )(WARPLAB_RXBUFF_RADIO2 + 4rxArg0),\
1148	1024
1149	);
1150
1151	//if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0);
1152	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RxBuff_Radio2_OFFSET + rxArg0));
1153
1154	sendPtr32[0] = packetNo + 1;
1155	sendPtr32[1] = ACK;
1156	sendPtr32[2] = command;
1157	sendPtr32[3] = rxArg0;
1158	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1159	break;
1160
1161	case RADIO3_RXDATA:
1162	//while(warplab_buffers_2x2_ReadReg_CaptureDone(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR) == 0) {}
1163
1164	/*
1165	memcpy
1166	(
1167	(unsigned int *)(sendPtr32 + 4), \
1168	(unsigned int )(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RxBuff_Radio3_OFFSET + 4rxArg0),\
1169	1024
1170	);
1171	*/
1172	memcpy
1173	(
1174	(unsigned int *)(sendPtr32 + 4), \
1175	(unsigned int )(WARPLAB_RXBUFF_RADIO3 + 4rxArg0),\
1176	1024
1177	);
1178
1179
1180	//if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0);
1181	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RxBuff_Radio3_OFFSET + rxArg0));
1182
1183	sendPtr32[0] = packetNo + 1;
1184	sendPtr32[1] = ACK;
1185	sendPtr32[2] = command;
1186	sendPtr32[3] = rxArg0;
1187	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1188	break;
1189
1190	#ifdef WARPLAB_CONFIG_4RF
1191	case RADIO4_RXDATA:
1192	memcpy
1193	(
1194	(unsigned int *)(sendPtr32 + 4), \
1195	(unsigned int )(WARPLAB_RXBUFF_RADIO4 + 4rxArg0),\
1196	1024
1197	);
1198
1199	sendPtr32[0] = packetNo + 1;
1200	sendPtr32[1] = ACK;
1201	sendPtr32[2] = command;
1202	sendPtr32[3] = rxArg0;
1203	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1204	break;
1205	#endif
1206
1207	#ifdef WARPLAB_CONFIG_4RF
1208	case RADIO1_RSSIDATA:
1209	memcpy
1210	(
1211	(unsigned int *)(sendPtr32 + 4), \
1212	(unsigned int )(WARPLAB_RSSIBUFF_RADIO1 + 4rxArg0),\
1213	1024
1214	);
1215	sendPtr32[0] = packetNo + 1;
1216	sendPtr32[1] = ACK;
1217	sendPtr32[2] = command;
1218	sendPtr32[3] = rxArg0;
1219	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1220	break;
1221	#endif
1222
1223	case RADIO2_RSSIDATA:
1224	//while(warplab_buffers_2x2_ReadReg_CaptureDone(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR) == 0) {}
1225
1226	/*
1227	memcpy
1228	(
1229	(unsigned int *)(sendPtr32 + 4), \
1230	(unsigned int )(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4rxArg0),\
1231	1024
1232	);
1233	*/
1234	memcpy
1235	(
1236	(unsigned int *)(sendPtr32 + 4), \
1237	(unsigned int )(WARPLAB_RSSIBUFF_RADIO2 + 4rxArg0),\
1238	1024
1239	);
1240
1241
1242	//if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0);
1243	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0));
1244
1245	sendPtr32[0] = packetNo + 1;
1246	sendPtr32[1] = ACK;
1247	sendPtr32[2] = command;
1248	sendPtr32[3] = rxArg0;
1249	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1250	break;
1251
1252	case RADIO3_RSSIDATA:
1253	//while(warplab_buffers_2x2_ReadReg_CaptureDone(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR) == 0) {}
1254
1255	/*
1256	memcpy
1257	(
1258	(unsigned int *)(sendPtr32 + 4), \
1259	(unsigned int )(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4rxArg0),\
1260	1024
1261	);
1262	*/
1263	memcpy
1264	(
1265	(unsigned int *)(sendPtr32 + 4), \
1266	(unsigned int )(WARPLAB_RSSIBUFF_RADIO3 + 4rxArg0),\
1267	1024
1268	);
1269
1270
1271	//if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0);
1272	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR + warplab_buffers_2x2_SMRO_RSSIBuff_Radio3_OFFSET + 4*rxArg0));
1273
1274	sendPtr32[0] = packetNo + 1;
1275	sendPtr32[1] = ACK;
1276	sendPtr32[2] = command;
1277	sendPtr32[3] = rxArg0;
1278	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1279	break;
1280
1281	#ifdef WARPLAB_CONFIG_4RF
1282	case RADIO4_RSSIDATA:
1283	memcpy
1284	(
1285	(unsigned int *)(sendPtr32 + 4), \
1286	(unsigned int )(WARPLAB_RSSIBUFF_RADIO4 + 4rxArg0),\
1287	1024
1288	);
1289	sendPtr32[0] = packetNo + 1;
1290	sendPtr32[1] = ACK;
1291	sendPtr32[2] = command;
1292	sendPtr32[3] = rxArg0;
1293	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1294	break;
1295	#endif
1296
1297	#ifdef WARPLAB_CONFIG_4RF
1298	case RADIO1TXBUFF_TXEN:
1299	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(1);
1300
1301	sendACK(packetNo, command);
1302	break;
1303	#endif
1304
1305	case RADIO2TXBUFF_TXEN:
1306	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(1);
1307
1308	sendACK(packetNo, command);
1309	break;
1310
1311	case RADIO3TXBUFF_TXEN:
1312	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(1);
1313
1314	sendACK(packetNo, command);
1315	break;
1316
1317	#ifdef WARPLAB_CONFIG_4RF
1318	case RADIO4TXBUFF_TXEN:
1319	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(1);
1320
1321	sendACK(packetNo, command);
1322	break;
1323	#endif
1324
1325	#ifdef WARPLAB_CONFIG_4RF
1326	case RADIO1TXBUFF_TXDIS:
1327	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0);
1328
1329	sendACK(packetNo, command);
1330	break;
1331	#endif
1332
1333	case RADIO2TXBUFF_TXDIS:
1334	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0);
1335
1336	sendACK(packetNo, command);
1337	break;
1338
1339	case RADIO3TXBUFF_TXDIS:
1340	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0);
1341
1342	sendACK(packetNo, command);
1343	break;
1344
1345	#ifdef WARPLAB_CONFIG_4RF
1346	case RADIO4TXBUFF_TXDIS:
1347	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0);
1348
1349	sendACK(packetNo, command);
1350	break;
1351	#endif
1352
1353	#ifdef WARPLAB_CONFIG_4RF
1354	case RADIO1RXBUFF_RXEN:
1355	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(1);
1356
1357	sendACK(packetNo, command);
1358	break;
1359	#endif
1360
1361	case RADIO2RXBUFF_RXEN:
1362	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(1);
1363
1364	sendACK(packetNo, command);
1365	break;
1366
1367	case RADIO3RXBUFF_RXEN:
1368	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(1);
1369
1370	sendACK(packetNo, command);
1371	break;
1372
1373	#ifdef WARPLAB_CONFIG_4RF
1374	case RADIO4RXBUFF_RXEN:
1375	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(1);
1376
1377	sendACK(packetNo, command);
1378	break;
1379	#endif
1380
1381	#ifdef WARPLAB_CONFIG_4RF
1382	case RADIO1RXBUFF_RXDIS:
1383	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0);
1384
1385	sendACK(packetNo, command);
1386	break;
1387	#endif
1388
1389	case RADIO2RXBUFF_RXDIS:
1390	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0);
1391
1392	sendACK(packetNo, command);
1393	break;
1394
1395	case RADIO3RXBUFF_RXDIS:
1396	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0);
1397
1398	sendACK(packetNo, command);
1399	break;
1400
1401	#ifdef WARPLAB_CONFIG_4RF
1402	case RADIO4RXBUFF_RXDIS:
1403	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0);
1404
1405	sendACK(packetNo, command);
1406	break;
1407	#endif
1408
1409	case RX_DONECHECK:
1410
1411	sendPtr32[0] = packetNo + 1;
1412	sendPtr32[1] = ACK;
1413	sendPtr32[2] = command;
1414
1415	if(warplab_buffers_ReadReg_CaptureDone(WARPLAB_BASEADDR) == 0)
1416	sendPtr32[3] = 0;
1417	else
1418	sendPtr32[3] = 1;
1419
1420	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1421	break;
1422
1423	case RX_DONEREADING:
1424	//warplab_buffers_2x2_WriteReg_DoneReading(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR, 1);
1425	//warplab_buffers_2x2_WriteReg_DoneReading(XPAR_warplab_buffers_2X2_OPBW_0_BASEADDR, 0);
1426
1427	sendACK(packetNo, command);
1428	break;
1429
1430	case RX_START:
1431	//if(DEBUG_LVL > 1) xil_printf("Starting Rx\n");
1432	//if(DEBUG_LVL > 1) xil_printf("Starting Rx\n");
1433	sendACK(packetNo, command);
1434
1435	if(waitForSync() == 0)
1436	{
1437	warplab_buffers_WriteReg_StartCapture(1);
1438	warplab_AGC_Start();
1439	warplab_buffers_WriteReg_StartCapture(0);
1440
1441	//if(DEBUG_LVL > 1) xil_printf("Capture started\n");
1442	}
1443	else
1444	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Rx Capture\n");
1445	break;
1446
1447	case TX_START:
1448	//if(DEBUG_LVL > 1) xil_printf("Starting Tx\n");
1449	if(DEBUG_LVL > 1) xil_printf("Starting Tx\n");
1450	sendACK(packetNo, command);
1451
1452	if(waitForSync() == 0)
1453	{
1454	warplab_buffers_WriteReg_StartTx(1);
1455	warplab_buffers_WriteReg_StartTx(0);
1456	//if(DEBUG_LVL > 1) xil_printf("Transmit started\n");
1457	}
1458	else
1459	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Tx\n");
1460	break;
1461
1462	case TX_STOP:
1463	sendACK(packetNo, command);
1464
1465	warplab_buffers_WriteReg_StopTx(1);
1466	warplab_buffers_WriteReg_StopTx(0);
1467
1468	break;
1469
1470	case TXRX_START:
1471	if(DEBUG_LVL > 1) xil_printf("Starting TxRX\n");
1472	sendACK(packetNo, command);
1473
1474	if(waitForSync() == 0)
1475	{
1476	warplab_buffers_WriteReg_StartTxRx(1);
1477	warplab_buffers_WriteReg_StartTxRx(0);
1478	}
1479	else
1480	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling TxRx\n");
1481	break;
1482
1483	case READ_AGC_DONE_ADDR:
1484	sendPtr32[0] = packetNo + 1;
1485	sendPtr32[1] = ACK;
1486	sendPtr32[2] = command;
1487
1488	sendPtr32[3] = warplab_buffers_ReadReg_AGCDoneAddr(WARPLAB_BASEADDR);
1489
1490	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1491	break;
1492
1493	#ifdef WARPLAB_CONFIG_4RF
1494	case READ_RADIO1AGCDONERSSI:
1495	sendPtr32[0] = packetNo + 1;
1496	sendPtr32[1] = ACK;
1497	sendPtr32[2] = command;
1498
1499	sendPtr32[3] = warplab_buffers_ReadReg_Radio1AGCDoneRSSI(WARPLAB_BASEADDR);
1500
1501	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1502	break;
1503	#endif
1504
1505	case READ_RADIO2AGCDONERSSI:
1506	sendPtr32[0] = packetNo + 1;
1507	sendPtr32[1] = ACK;
1508	sendPtr32[2] = command;
1509
1510	sendPtr32[3] = warplab_buffers_ReadReg_Radio2AGCDoneRSSI(WARPLAB_BASEADDR);
1511
1512	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1513	break;
1514
1515	case READ_RADIO3AGCDONERSSI:
1516	sendPtr32[0] = packetNo + 1;
1517	sendPtr32[1] = ACK;
1518	sendPtr32[2] = command;
1519
1520	sendPtr32[3] = warplab_buffers_ReadReg_Radio3AGCDoneRSSI(WARPLAB_BASEADDR);
1521
1522	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1523	break;
1524
1525	#ifdef WARPLAB_CONFIG_4RF
1526	case READ_RADIO4AGCDONERSSI:
1527	sendPtr32[0] = packetNo + 1;
1528	sendPtr32[1] = ACK;
1529	sendPtr32[2] = command;
1530
1531	sendPtr32[3] = warplab_buffers_ReadReg_Radio4AGCDoneRSSI(WARPLAB_BASEADDR);
1532
1533	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1534	break;
1535	#endif
1536
1537	case AGC_RESET:
1538	warplab_AGC_Reset();
1539	sendACK(packetNo, command);
1540	break;
1541
1542	case READ_AGC_GAINS:
1543	sendPtr32[0] = packetNo + 1;
1544	sendPtr32[1] = ACK;
1545	sendPtr32[2] = command;
1546
1547	sendPtr32[3] = warplab_AGC_GetGains();
1548
1549	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1550	break;
1551
1552	case SET_AGC_TARGET_dBm:
1553	agctarget = (int)receivePtr32[2];
1554	warplab_AGC_SetTarget(agctarget);
1555	xil_printf("agctarget = %d\n",agctarget);
1556	sendACK(packetNo, command);
1557	break;
1558
1559	case SET_AGC_DCO_EN_DIS:
1560	agc_dco_state = (unsigned int)receivePtr32[2];
1561	warplab_AGC_SetDCO(agc_dco_state);
1562	warplab_buffers_WriteReg_DCO_EN_SEL(agc_dco_state);
1563	xil_printf("agc_dco_state = %d\n",agc_dco_state);
1564	sendACK(packetNo, command);
1565	break;
1566
1567	case SET_AGC_NOISEEST_dBm:
1568	agcnoiseEst = (int)receivePtr32[2];
1569	warplab_AGC_setNoiseEstimate(agcnoiseEst);
1570	xil_printf("agctarget = %d\n",agctarget);
1571	sendACK(packetNo, command);
1572	break;
1573
1574	case SET_AGC_THRESHOLDS:
1575	warplab_AGC_WriteReg_Thresholds((unsigned int)receivePtr32[2]);
1576	sendACK(packetNo, command);
1577	break;
1578
1579	case SET_AGC_TRIG_DELAY:
1580	warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)receivePtr32[2]);
1581	sendACK(packetNo, command);
1582	break;
1583
1584	case READ_AGC_THRESHOLDS:
1585	sendPtr32[0] = packetNo + 1;
1586	sendPtr32[1] = ACK;
1587	sendPtr32[2] = command;
1588
1589	sendPtr32[3] = warplab_AGC_ReadReg_Thresholds(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1590
1591	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1592	break;
1593
1594	case CLOSE:
1595	if(DEBUG_LVL > 1) xil_printf("Closing sockets.\n");
1596	sendACK(packetNo, command);
1597	done = 1;
1598
1599	break;
1600
1601	case TX_TEST:
1602	if(DEBUG_LVL > 1) xil_printf("Starting Tx Test\n");
1603	sendACK(packetNo, command);
1604
1605	break;
1606
1607	default:
1608	if(DEBUG_LVL > 1) xil_printf("Received command (%d) is not recognized. Please retry transmission.\n", command);
1609
1610	sendPtr32[0] = packetNo + 1;
1611	sendPtr32[1] = NOACK;
1612	bytesSend = 8;
1613	xilsock_sendto(sock, sendBuffer, bytesSend, (struct sockaddr *)&addr, alen);
1614	}
1615	}
1616	}
1617
1618	shut_socket();
1619
1620	return 0;
1621	}
1622
1623	void sendACK(unsigned int packetNo, unsigned int commandToACK)
1624	{
1625	sendPtr32[0] = packetNo + 1;
1626	sendPtr32[1] = ACK;
1627	sendPtr32[2] = commandToACK;
1628	xilsock_sendto(sock, sendBuffer, 12, (struct sockaddr *)&addr, alen);
1629	return;
1630	}
1631
1632	unsigned char sevenSegmentMap(unsigned char x)
1633	{
1634	switch(x)
1635	{
1636	case(0x0) : return 0x007E;
1637	case(0x1) : return 0x0030;
1638	case(0x2) : return 0x006D;
1639	case(0x3) : return 0x0079;
1640	case(0x4) : return 0x0033;
1641	case(0x5) : return 0x005B;
1642	case(0x6) : return 0x005F;
1643	case(0x7) : return 0x0070;
1644	case(0x8) : return 0x007F;
1645	case(0x9) : return 0x007B;
1646
1647	case(0xA) : return 0x0077;
1648	case(0xB) : return 0x007F;
1649	case(0xC) : return 0x004E;
1650	case(0xD) : return 0x007E;
1651	case(0xE) : return 0x004F;
1652	case(0xF) : return 0x0047;
1653	default : return 0x0000;
1654	}
1655	}
1656
1657	#define XPAR_EEPROM_CONTROLLER_BASEADDR XPAR_EEPROM_CONTROLLER_MEM0_BASEADDR
1658	//New TxDCO calibration code
1659	int warpphy_applyTxDCOCalibration(unsigned int radioSelection)
1660	{
1661	int eepromStatus = 0;
1662	short calReadback = 0;
1663	signed short best_I, best_Q;
1664	unsigned char radioNum;
1665	Xuint8 memory[8], version, revision, valid, i;
1666	Xuint16 serial;
1667
1668	//Radio selection will be 0x11111111, 0x22222222, 0x44444444 or 0x88888888
1669	// corresponding to radios in slots 1, 2, 3 or 4
1670	// We need the slot number to initialize the EEPROM
1671	radioNum = (radioSelection & 0xF) == 1 ? 1 : ( (radioSelection & 0xF) == 2 ? 2 : ( (radioSelection & 0xF) == 4 ? 3 : 4 ) );
1672	if(DEBUG_LVL>2) xil_printf("Applying TxDCO correction for radio %d\n", radioNum);
1673
1674	//Mimic the radio test code, in hopes of a more stable EEPROM read...
1675	//Choose the EEPROM on the selected radio board; second arg is [0,1,2,3,4] for [FPGA, radio1, radio2, radio3, radio4]
1676	eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR, 0);
1677	if(eepromStatus != 0)
1678	{
1679	if(DEBUG_LVL>2) xil_printf("EEPROM Select Failed!\n");
1680	return -1;
1681	}
1682
1683	//Initialize the EEPROM controller
1684	eepromStatus = WarpEEPROM_Initialize((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR);
1685	if(eepromStatus != 0)
1686	{
1687	if(DEBUG_LVL>2) xil_printf("EEPROM Init Returned %x\n", eepromStatus);
1688	if(DEBUG_LVL>2) xil_printf("EEPROM Init Failed!\n");
1689	return -1;
1690	}
1691
1692	//Select the EEPROM on the current radio board
1693	eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, radioNum);
1694
1695	if(eepromStatus != 0)
1696	{
1697	if(DEBUG_LVL>2) xil_printf("TxDCO: EEPROM error\n");
1698	return -1;
1699	}
1700
1701	//Read the first page from the EERPOM
1702	WarpEEPROM_ReadMem((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 0, 0, memory);
1703	version = (memory[0] & 0xE0) >> 5;
1704	revision = (memory[1] & 0xE0) >> 5;
1705	valid = memory[1] & 0x1F;
1706
1707	if(DEBUG_LVL>2) xil_printf("\n\nEEPROM Values for Radio Board in Slot %d\n", radioNum);
1708
1709	if(DEBUG_LVL>2) xil_printf(" WARP Radio Board Version %d.%d\n", version, revision);
1710
1711	serial = WarpEEPROM_ReadWARPSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR);
1712
1713	if(DEBUG_LVL>2) xil_printf(" Serial Number (WARP): WR-a-%05d\n", serial);
1714
1715	WarpEEPROM_ReadDSSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, memory);
1716	if(DEBUG_LVL>2) print(" EEPROM Hard-wired Serial Number: ");
1717	if(DEBUG_LVL>2){
1718	for(i=1;i<7;i++)
1719	xil_printf(" %x",memory[7-i]);
1720	xil_printf("\n\n");
1721	}
1722	//Read the Tx DCO values
1723	calReadback = WarpEEPROM_ReadRadioCal((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 2, 1);
1724
1725	//Scale the stored values
1726	best_I = (signed short)(((signed char)(calReadback & 0xFF))<<1);
1727	best_Q = (signed short)(((signed char)((calReadback>>8) & 0xFF))<<1);
1728
1729	if(DEBUG_LVL>2) xil_printf("TxDCO: Applied values to radio %d - I: %d\tQ: %d\n", radioNum, best_I, best_Q);
1730
1731	//Finally, write the Tx DCO values to the DAC
1732	WarpRadio_v1_DACOffsetAdj(ICHAN, best_I, radioSelection);
1733	WarpRadio_v1_DACOffsetAdj(QCHAN, best_Q, radioSelection);
1734
1735	return 0;
1736	}
1737
1738
1739	void warplab_AGC_Reset()
1740	{
1741	// Cycle the agc's software reset port
1742
1743	warplab_AGC_WriteReg_SRESET_IN(1);
1744	usleep(10);
1745	warplab_AGC_WriteReg_SRESET_IN(0);
1746	usleep(100);
1747
1748	return;
1749	}
1750
1751	void warplab_AGC_MasterReset()
1752	{
1753	// Cycle the master reset register in the AGC and enable it
1754
1755	warplab_AGC_WriteReg_AGC_EN(0);
1756	usleep(10);
1757	warplab_AGC_WriteReg_MRESET_IN(0);
1758	usleep(10);
1759	warplab_AGC_WriteReg_MRESET_IN(1);
1760	usleep(10);
1761	warplab_AGC_WriteReg_MRESET_IN(0);
1762	usleep(10);
1763	warplab_AGC_WriteReg_AGC_EN(1);
1764
1765	return;
1766	}
1767
1768	void warplab_AGC_Start()
1769	{
1770	// Cycle the agc's packet in port
1771	warplab_AGC_WriteReg_PACKET_IN(1);
1772	usleep(10);
1773	warplab_AGC_WriteReg_PACKET_IN(0);
1774	usleep(100);
1775
1776	return;
1777	}
1778
1779	void warplab_AGC_Initialize(int noise_estimate)
1780	{
1781	int g_bbset = 0;
1782
1783	// First set all standard parameters
1784
1785	// Turn off both resets and the master enable
1786	warplab_AGC_WriteReg_AGC_EN(0);
1787	warplab_AGC_WriteReg_SRESET_IN(0);
1788	warplab_AGC_WriteReg_MRESET_IN(0);
1789
1790	// An adjustment parameter
1791	warplab_AGC_WriteReg_ADJ(8);
1792
1793	// Timing for the DC-offset correction
1794	warplab_AGC_WriteReg_DCO_Timing(0x12001000);
1795
1796	// Initial baseband gain setting
1797	warplab_AGC_WriteReg_GBB_init(52);
1798
1799	// RF gain AGCstate thresholds
1800	warplab_AGC_WriteReg_Thresholds(0xD5CBA6);
1801
1802	// Overall AGC timing
1803	warplab_AGC_WriteReg_Timing(0x9A962A28);//0x826E3C0A;
1804
1805	// vIQ and RSSI average lengths
1806	warplab_AGC_WriteReg_AVG_LEN(0x10F); //103
1807
1808	// Disable DCO, disable DCO subtraction
1809	warplab_AGC_WriteReg_Bits(0x0);
1810
1811	// Compute and set the initial g_BB gain value from the noise estimate
1812	// The initial g_bb sets noise to -19 db, assuming 32 db RF gain
1813
1814	g_bbset = -19 - 32 - noise_estimate;
1815	warplab_AGC_WriteReg_GBB_init(g_bbset);
1816
1817	// Perform a master reset
1818	warplab_AGC_MasterReset();
1819
1820	// Agc is now reset and enabled, ready to go!
1821	return;
1822	}
1823
1824	void warplab_AGC_setNoiseEstimate(int noise_estimate)
1825	{
1826	int g_bbset;
1827
1828	g_bbset = -19 - 32 - noise_estimate;
1829
1830	warplab_AGC_WriteReg_GBB_init(g_bbset);
1831
1832	return;
1833	}
1834
1835	unsigned int warplab_AGC_GetGains(void)
1836	{
1837	unsigned int gBB_A, gRF_A, gBB_B, gRF_B, gBB_C, gRF_C, gBB_D, gRF_D, gains;
1838
1839	// Get the gains from the registers
1840	gBB_A = warplab_AGC_ReadReg_GBB_A(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1841	gRF_A = warplab_AGC_ReadReg_GRF_A(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1842
1843	gBB_B = warplab_AGC_ReadReg_GBB_B(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1844	gRF_B = warplab_AGC_ReadReg_GRF_B(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1845
1846	gBB_C = warplab_AGC_ReadReg_GBB_C(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1847	gRF_C = warplab_AGC_ReadReg_GRF_C(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1848
1849	gBB_D = warplab_AGC_ReadReg_GBB_D(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1850	gRF_D = warplab_AGC_ReadReg_GRF_D(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1851
1852	// First concatenate the two radios together, into the gRF register
1853	// 2 lowest bits are RF, 5 higher bits are BB, last bit is unused
1854	// Multiply by 2^2, shift gBB right by 2 bits
1855
1856	gRF_A = gRF_A + (gBB_A * 4);
1857	gRF_B = gRF_B + (gBB_B * 4);
1858	gRF_C = gRF_C + (gBB_C * 4);
1859	gRF_D = gRF_D + (gBB_D * 4);
1860
1861	// Multiply by 2^8 shift gRF right by 8 bits
1862
1863	gains = gRF_A + (gRF_B * 256) + (gRF_C * 65536) + (gRF_D * 16777216);
1864
1865	return gains;
1866	}
1867
1868	void warplab_AGC_SetTarget(unsigned int target)
1869	{
1870	warplab_AGC_WriteReg_T_dB(target);
1871	return;
1872	}
1873
1874	void warplab_AGC_SetDCO(unsigned int AGCstate)
1875	{
1876	// Enables DCO and DCO subtraction (correction scheme and butterworth hipass are active)
1877
1878	unsigned int bits;
1879
1880	bits = warplab_AGC_ReadReg_Bits(XPAR_WARPLAB_BUFFERS_PLBW_AGC_PLBW_0_BASEADDR);
1881
1882	if(AGCstate)
1883	bits = bits \| 0x6;
1884	else
1885	bits = bits & 0x1;
1886
1887	warplab_AGC_WriteReg_Bits(bits);
1888
1889	return;
1890	}

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source: ResearchApps/PHY/WARPLAB/WARPLab_v6p2/C_Code_Reference/warplab.c

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