[1829] | 1 |
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| 2 | # ##############################################################################
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| 3 | # Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd
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| 4 | # Thu Jun 28 08:17:23 2012
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| 5 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1 (XPS 13 version)
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| 6 | # Family: virtex4
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| 7 | # Device: XC4VFX100
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| 8 | # Package: FF1517
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| 9 | # Speed Grade: -11
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| 10 | # Processor number: 1
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| 11 | # Processor 1: ppc405_0
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| 12 | # Processor clock frequency: 160.0
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| 13 | # Bus clock frequency: 80.0
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| 14 | # Debug Interface: FPGA JTAG
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| 15 | # ##############################################################################
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| 16 | PARAMETER VERSION = 2.1.0
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| 17 |
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| 18 |
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| 19 | PORT fpga_0_UserIO_LEDs_out_pin = fpga_0_UserIO_LEDs_out_pin, DIR = O, VEC = [0:7]
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| 20 | PORT fpga_0_UserIO_IOEx_SDA_pin = fpga_0_UserIO_IOEx_SDA_pin, DIR = O
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| 21 | PORT fpga_0_UserIO_IOEx_SCL_pin = fpga_0_UserIO_IOEx_SCL_pin, DIR = O
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| 22 | PORT fpga_0_UserIO_PB_in_pin = fpga_0_UserIO_PB_in_pin, DIR = I, VEC = [0:3]
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| 23 | PORT fpga_0_UserIO_DIPSW_in_pin = fpga_0_UserIO_DIPSW_in_pin, DIR = I, VEC = [0:3]
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| 24 | PORT fpga_0_rs232_db9_RX_pin = fpga_0_rs232_db9_RX_pin, DIR = I
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| 25 | PORT fpga_0_rs232_db9_TX_pin = fpga_0_rs232_db9_TX_pin, DIR = O
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| 26 | PORT fpga_0_rs232_usb_RX_pin = fpga_0_rs232_usb_RX_pin, DIR = I
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| 27 | PORT fpga_0_rs232_usb_TX_pin = fpga_0_rs232_usb_TX_pin, DIR = O
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| 28 | PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin, DIR = O
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| 29 | PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin, DIR = I
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| 30 | PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin, DIR = O, VEC = [7:0]
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| 31 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin, DIR = O
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| 32 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin, DIR = O
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| 33 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin, DIR = O
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| 34 | PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin, DIR = I, VEC = [7:0]
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| 35 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin, DIR = I
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| 36 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin, DIR = I
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| 37 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin, DIR = I
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| 38 | PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0_pin, DIR = O
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| 39 | PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0_pin, DIR = IO
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| 40 | PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk_pin, DIR = I
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| 41 | PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out_pin, DIR = O
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| 42 | PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out_pin, DIR = O
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| 43 | PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out_pin, DIR = O
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| 44 | PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out_pin, DIR = O
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| 45 | PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out_pin, DIR = O
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| 46 | PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out_pin, DIR = O
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| 47 | PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out_pin, DIR = O
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| 48 | PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out_pin, DIR = O
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| 49 | PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out_pin, DIR = O
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| 50 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin, DIR = O
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| 51 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin, DIR = O, VEC = [15:0]
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| 52 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
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| 53 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin, DIR = I, VEC = [13:0]
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| 54 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
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| 55 | PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B_pin, DIR = O, VEC = [6:0]
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| 56 | PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin, DIR = O, VEC = [1:0]
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| 57 | PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED_pin, DIR = O, VEC = [2:0]
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| 58 | PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin, DIR = I, VEC = [3:0]
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| 59 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
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| 60 | PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin, DIR = IO
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| 61 | PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin, DIR = O
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| 62 | PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data_pin, DIR = O
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| 63 | PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin, DIR = O
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| 64 | PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN_pin, DIR = O
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| 65 | PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn_pin, DIR = O
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| 66 | PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn_pin, DIR = O
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| 67 | PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP_pin, DIR = O
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| 68 | PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA_pin, DIR = O
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| 69 | PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA_pin, DIR = O
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| 70 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin, DIR = O
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| 71 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin, DIR = O
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| 72 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin, DIR = O
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| 73 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin, DIR = O
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| 74 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin, DIR = O
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| 75 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin, DIR = O
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| 76 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin, DIR = O
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| 77 | PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD_pin, DIR = I
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| 78 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin, DIR = I
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| 79 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin, DIR = I
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| 80 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin, DIR = I
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| 81 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin, DIR = I
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| 82 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin, DIR = O
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| 83 | PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data_pin, DIR = O
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| 84 | PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin, DIR = O
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| 85 | PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin, DIR = O
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| 86 | PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out_pin, DIR = O
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| 87 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin, DIR = O
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| 88 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin, DIR = O, VEC = [15:0]
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| 89 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin, DIR = O, VEC = [15:0]
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| 90 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin, DIR = I, VEC = [13:0]
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| 91 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin, DIR = I, VEC = [13:0]
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| 92 | PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B_pin, DIR = O, VEC = [6:0]
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| 93 | PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin, DIR = O, VEC = [1:0]
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| 94 | PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED_pin, DIR = O, VEC = [2:0]
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| 95 | PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin, DIR = I, VEC = [3:0]
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| 96 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0]
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| 97 | PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin, DIR = IO
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| 98 | PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin, DIR = O
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| 99 | PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data_pin, DIR = O
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| 100 | PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin, DIR = O
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| 101 | PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN_pin, DIR = O
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| 102 | PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn_pin, DIR = O
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| 103 | PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn_pin, DIR = O
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| 104 | PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP_pin, DIR = O
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| 105 | PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA_pin, DIR = O
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| 106 | PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA_pin, DIR = O
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| 107 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin, DIR = O
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| 108 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin, DIR = O
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| 109 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin, DIR = O
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| 110 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin, DIR = O
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| 111 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin, DIR = O
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| 112 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin, DIR = O
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| 113 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin, DIR = O
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| 114 | PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD_pin, DIR = I
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| 115 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin, DIR = I
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| 116 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin, DIR = I
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| 117 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin, DIR = I
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| 118 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin, DIR = I
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| 119 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin, DIR = O
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| 120 | PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data_pin, DIR = O
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| 121 | PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin, DIR = O
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| 122 | PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin, DIR = O
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| 123 | PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0_pin, DIR = IO
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| 124 | PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000
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| 125 | PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
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| 126 | PORT debug_status = rxrun & txrun, DIR = O, VEC = [1:0]
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| 127 | PORT debug_sw_gpio = debug_sw_gpio, DIR = O, VEC = [5:0]
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| 128 |
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| 129 |
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| 130 | BEGIN ppc405_virtex4
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| 131 | PARAMETER INSTANCE = ppc405_0
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| 132 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0
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| 133 | PARAMETER C_IDCR_BASEADDR = 0b0100000000
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| 134 | PARAMETER C_IDCR_HIGHADDR = 0b0111111111
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| 135 | PARAMETER HW_VER = 2.01.b
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| 136 | BUS_INTERFACE DPLB0 = plb
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| 137 | BUS_INTERFACE IPLB0 = plb
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| 138 | BUS_INTERFACE DSOCM = ppc405_0_docm
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| 139 | BUS_INTERFACE ISOCM = ppc405_0_iocm
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| 140 | BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus
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| 141 | BUS_INTERFACE RESETPPC = ppc_reset_bus
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| 142 | PORT CPMC405CLOCK = clk_160_0000MHzDCM0
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| 143 | END
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| 144 |
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| 145 | BEGIN isocm_v10
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| 146 | PARAMETER INSTANCE = ppc405_0_iocm
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| 147 | PARAMETER C_ISCNTLVALUE = 0xa3
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| 148 | PARAMETER HW_VER = 2.00.b
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| 149 | PORT ISOCM_Clk = clk_80_0000MHzDCM0
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| 150 | PORT SYS_Rst = sys_bus_reset
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| 151 | END
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| 152 |
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| 153 | BEGIN isbram_if_cntlr
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| 154 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr
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| 155 | PARAMETER HW_VER = 3.00.c
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| 156 | PARAMETER C_BASEADDR = 0xffff0000
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| 157 | PARAMETER C_HIGHADDR = 0xffffffff
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| 158 | BUS_INTERFACE ISOCM = ppc405_0_iocm
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| 159 | BUS_INTERFACE DCR_WRITE_PORT = ppc405_0_iocm_cntlr_porta
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| 160 | BUS_INTERFACE INSTRN_READ_PORT = ppc405_0_iocm_cntlr_portb
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| 161 | END
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| 162 |
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| 163 | BEGIN bram_block
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| 164 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr_bram
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| 165 | PARAMETER HW_VER = 1.00.a
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| 166 | BUS_INTERFACE PORTA = ppc405_0_iocm_cntlr_porta
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| 167 | BUS_INTERFACE PORTB = ppc405_0_iocm_cntlr_portb
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| 168 | END
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| 169 |
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| 170 | BEGIN dsocm_v10
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| 171 | PARAMETER INSTANCE = ppc405_0_docm
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| 172 | PARAMETER C_DSCNTLVALUE = 0xa3
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| 173 | PARAMETER HW_VER = 2.00.b
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| 174 | PORT DSOCM_Clk = clk_80_0000MHzDCM0
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| 175 | PORT SYS_Rst = sys_bus_reset
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| 176 | END
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| 177 |
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| 178 | BEGIN dsbram_if_cntlr
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| 179 | PARAMETER INSTANCE = ppc405_0_docm_cntlr
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| 180 | PARAMETER HW_VER = 3.00.c
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| 181 | PARAMETER C_BASEADDR = 0x40110000
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| 182 | PARAMETER C_HIGHADDR = 0x4011ffff
|
---|
| 183 | BUS_INTERFACE DSOCM = ppc405_0_docm
|
---|
| 184 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
| 185 | END
|
---|
| 186 |
|
---|
| 187 | BEGIN bram_block
|
---|
| 188 | PARAMETER INSTANCE = ppc405_0_docm_cntlr_bram
|
---|
| 189 | PARAMETER HW_VER = 1.00.a
|
---|
| 190 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta
|
---|
| 191 | END
|
---|
| 192 |
|
---|
| 193 | BEGIN plb_v46
|
---|
| 194 | PARAMETER INSTANCE = plb
|
---|
| 195 | PARAMETER C_DCR_INTFCE = 0
|
---|
| 196 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
| 197 | PARAMETER HW_VER = 1.05.a
|
---|
| 198 | PORT PLB_Clk = clk_80_0000MHzDCM0
|
---|
| 199 | PORT SYS_Rst = sys_bus_reset
|
---|
| 200 | END
|
---|
| 201 |
|
---|
| 202 | BEGIN xps_bram_if_cntlr
|
---|
| 203 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
---|
| 204 | PARAMETER C_SPLB_NATIVE_DWIDTH = 64
|
---|
| 205 | PARAMETER HW_VER = 1.00.b
|
---|
| 206 | PARAMETER C_BASEADDR = 0x00000000
|
---|
| 207 | PARAMETER C_HIGHADDR = 0x0000ffff
|
---|
| 208 | BUS_INTERFACE SPLB = plb
|
---|
| 209 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
| 210 | END
|
---|
| 211 |
|
---|
| 212 | BEGIN bram_block
|
---|
| 213 | PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
|
---|
| 214 | PARAMETER HW_VER = 1.00.a
|
---|
| 215 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port
|
---|
| 216 | END
|
---|
| 217 |
|
---|
| 218 | BEGIN warp_v4_userio
|
---|
| 219 | PARAMETER INSTANCE = UserIO
|
---|
| 220 | PARAMETER C_ADDRESS_0 = 0x40
|
---|
| 221 | PARAMETER C_ADDRESS_1 = 0x42
|
---|
| 222 | PARAMETER C_I2C_DIVIDER = 0x40
|
---|
| 223 | PARAMETER HW_VER = 1.00.a
|
---|
| 224 | PARAMETER C_BASEADDR = 0xc9600000
|
---|
| 225 | PARAMETER C_HIGHADDR = 0xc960ffff
|
---|
| 226 | BUS_INTERFACE SPLB = plb
|
---|
| 227 | PORT LEDs_out = fpga_0_UserIO_LEDs_out_pin
|
---|
| 228 | PORT IOEx_SDA = fpga_0_UserIO_IOEx_SDA_pin
|
---|
| 229 | PORT IOEx_SCL = fpga_0_UserIO_IOEx_SCL_pin
|
---|
| 230 | PORT PB_in = fpga_0_UserIO_PB_in_pin
|
---|
| 231 | PORT DIPSW_in = fpga_0_UserIO_DIPSW_in_pin
|
---|
| 232 | END
|
---|
| 233 |
|
---|
| 234 | BEGIN xps_uartlite
|
---|
| 235 | PARAMETER INSTANCE = rs232_db9
|
---|
| 236 | PARAMETER C_BAUDRATE = 57600
|
---|
| 237 | PARAMETER C_DATA_BITS = 8
|
---|
| 238 | PARAMETER C_USE_PARITY = 0
|
---|
| 239 | PARAMETER C_ODD_PARITY = 0
|
---|
| 240 | PARAMETER HW_VER = 1.02.a
|
---|
| 241 | PARAMETER C_BASEADDR = 0x84020000
|
---|
| 242 | PARAMETER C_HIGHADDR = 0x8402ffff
|
---|
| 243 | BUS_INTERFACE SPLB = plb
|
---|
| 244 | PORT RX = fpga_0_rs232_db9_RX_pin
|
---|
| 245 | PORT TX = fpga_0_rs232_db9_TX_pin
|
---|
| 246 | END
|
---|
| 247 |
|
---|
| 248 | BEGIN xps_uartlite
|
---|
| 249 | PARAMETER INSTANCE = rs232_usb
|
---|
| 250 | PARAMETER C_BAUDRATE = 57600
|
---|
| 251 | PARAMETER C_DATA_BITS = 8
|
---|
| 252 | PARAMETER C_USE_PARITY = 0
|
---|
| 253 | PARAMETER C_ODD_PARITY = 0
|
---|
| 254 | PARAMETER HW_VER = 1.02.a
|
---|
| 255 | PARAMETER C_BASEADDR = 0x84000000
|
---|
| 256 | PARAMETER C_HIGHADDR = 0x8400ffff
|
---|
| 257 | BUS_INTERFACE SPLB = plb
|
---|
| 258 | PORT RX = fpga_0_rs232_usb_RX_pin
|
---|
| 259 | PORT TX = fpga_0_rs232_usb_TX_pin
|
---|
| 260 | END
|
---|
| 261 |
|
---|
| 262 | BEGIN xps_ll_temac
|
---|
| 263 | PARAMETER INSTANCE = TriMode_MAC_GMII
|
---|
| 264 | PARAMETER C_NUM_IDELAYCTRL = 2
|
---|
| 265 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6
|
---|
| 266 | PARAMETER C_PHY_TYPE = 1
|
---|
| 267 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
| 268 | PARAMETER C_TEMAC_TYPE = 1
|
---|
| 269 | PARAMETER HW_VER = 2.03.a
|
---|
| 270 | PARAMETER C_BASEADDR = 0x87000000
|
---|
| 271 | PARAMETER C_HIGHADDR = 0x8707ffff
|
---|
| 272 | BUS_INTERFACE SPLB = plb
|
---|
| 273 | BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_llink0
|
---|
| 274 | PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin
|
---|
| 275 | PORT GTX_CLK_0 = clk_125_0000MHz
|
---|
| 276 | PORT REFCLK = clk_200_0000MHz
|
---|
| 277 | PORT LlinkTemac0_CLK = clk_80_0000MHzDCM0
|
---|
| 278 | PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin
|
---|
| 279 | PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin
|
---|
| 280 | PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin
|
---|
| 281 | PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin
|
---|
| 282 | PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin
|
---|
| 283 | PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin
|
---|
| 284 | PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin
|
---|
| 285 | PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin
|
---|
| 286 | PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin
|
---|
| 287 | PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0_pin
|
---|
| 288 | PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0_pin
|
---|
| 289 | END
|
---|
| 290 |
|
---|
| 291 | BEGIN clock_board_config
|
---|
| 292 | PARAMETER INSTANCE = clk_board_config
|
---|
| 293 | PARAMETER HW_VER = 1.05.a
|
---|
| 294 | PORT sys_clk = fpga_0_clk_board_config_sys_clk_pin
|
---|
| 295 | PORT sys_rst = net_gnd
|
---|
| 296 | PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out_pin
|
---|
| 297 | PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out_pin
|
---|
| 298 | PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out_pin
|
---|
| 299 | PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out_pin
|
---|
| 300 | PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out_pin
|
---|
| 301 | PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out_pin
|
---|
| 302 | PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out_pin
|
---|
| 303 | PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out_pin
|
---|
| 304 | PORT radio_clk_src_sel = net_gnd
|
---|
| 305 | PORT logic_clk_src_sel = net_gnd
|
---|
| 306 | PORT config_invalid = clk_board_config_config_invalid
|
---|
| 307 | END
|
---|
| 308 |
|
---|
| 309 | BEGIN radio_controller
|
---|
| 310 | PARAMETER INSTANCE = radio_controller_0
|
---|
| 311 | PARAMETER HW_VER = 1.30.a
|
---|
| 312 | PARAMETER C_BASEADDR = 0xcac00000
|
---|
| 313 | PARAMETER C_HIGHADDR = 0xcac0ffff
|
---|
| 314 | BUS_INTERFACE SPLB = plb_v46_40MHz
|
---|
| 315 | BUS_INTERFACE RC2RB_RAD2 = radio_controller_0_RC2RB_RAD2
|
---|
| 316 | BUS_INTERFACE RC2RB_RAD3 = radio_controller_0_RC2RB_RAD3
|
---|
| 317 | END
|
---|
| 318 |
|
---|
| 319 | BEGIN radio_bridge
|
---|
| 320 | PARAMETER INSTANCE = radio_bridge_slot_2
|
---|
| 321 | PARAMETER HW_VER = 1.30.a
|
---|
| 322 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD2
|
---|
| 323 | PORT converter_clock_in = clk_40_0000MHz
|
---|
| 324 | PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out_pin
|
---|
| 325 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin
|
---|
| 326 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin
|
---|
| 327 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin
|
---|
| 328 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin
|
---|
| 329 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin
|
---|
| 330 | PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B_pin
|
---|
| 331 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin
|
---|
| 332 | PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED_pin
|
---|
| 333 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin
|
---|
| 334 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin
|
---|
| 335 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin
|
---|
| 336 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin
|
---|
| 337 | PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data_pin
|
---|
| 338 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin
|
---|
| 339 | PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN_pin
|
---|
| 340 | PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn_pin
|
---|
| 341 | PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn_pin
|
---|
| 342 | PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP_pin
|
---|
| 343 | PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA_pin
|
---|
| 344 | PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA_pin
|
---|
| 345 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin
|
---|
| 346 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin
|
---|
| 347 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin
|
---|
| 348 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin
|
---|
| 349 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin
|
---|
| 350 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin
|
---|
| 351 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin
|
---|
| 352 | PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD_pin
|
---|
| 353 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
|
---|
| 354 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
|
---|
| 355 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin
|
---|
| 356 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin
|
---|
| 357 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin
|
---|
| 358 | PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data_pin
|
---|
| 359 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin
|
---|
| 360 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin
|
---|
| 361 | PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
|
---|
| 362 | PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
|
---|
| 363 | PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
|
---|
| 364 | PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I
|
---|
| 365 | PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q
|
---|
| 366 | PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I
|
---|
| 367 | PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q
|
---|
| 368 | PORT user_TxModelStart = radio2_txStart
|
---|
| 369 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
| 370 | PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
| 371 | PORT user_RxHP_external = agc_rxhp_b
|
---|
| 372 | PORT user_RxBB_gain = agc_g_bb_b
|
---|
| 373 | PORT user_RxRF_gain = agc_g_rf_b
|
---|
| 374 | END
|
---|
| 375 |
|
---|
| 376 | BEGIN radio_bridge
|
---|
| 377 | PARAMETER INSTANCE = radio_bridge_slot_3
|
---|
| 378 | PARAMETER HW_VER = 1.30.a
|
---|
| 379 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD3
|
---|
| 380 | PORT converter_clock_in = clk_40_0000MHz
|
---|
| 381 | PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out_pin
|
---|
| 382 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin
|
---|
| 383 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin
|
---|
| 384 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin
|
---|
| 385 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin
|
---|
| 386 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin
|
---|
| 387 | PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B_pin
|
---|
| 388 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin
|
---|
| 389 | PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED_pin
|
---|
| 390 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin
|
---|
| 391 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin
|
---|
| 392 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin
|
---|
| 393 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin
|
---|
| 394 | PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data_pin
|
---|
| 395 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin
|
---|
| 396 | PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN_pin
|
---|
| 397 | PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn_pin
|
---|
| 398 | PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn_pin
|
---|
| 399 | PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP_pin
|
---|
| 400 | PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA_pin
|
---|
| 401 | PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA_pin
|
---|
| 402 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin
|
---|
| 403 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin
|
---|
| 404 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin
|
---|
| 405 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin
|
---|
| 406 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin
|
---|
| 407 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin
|
---|
| 408 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin
|
---|
| 409 | PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD_pin
|
---|
| 410 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
|
---|
| 411 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
|
---|
| 412 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin
|
---|
| 413 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin
|
---|
| 414 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin
|
---|
| 415 | PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data_pin
|
---|
| 416 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin
|
---|
| 417 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin
|
---|
| 418 | PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
|
---|
| 419 | PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
|
---|
| 420 | PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
|
---|
| 421 | PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I
|
---|
| 422 | PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q
|
---|
| 423 | PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I
|
---|
| 424 | PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q
|
---|
| 425 | PORT user_TxModelStart = radio3_txStart
|
---|
| 426 | PORT user_RSSI_ADC_clk = rssi_clk_out
|
---|
| 427 | PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
| 428 | PORT user_RxHP_external = agc_rxhp_c
|
---|
| 429 | PORT user_RxBB_gain = agc_g_bb_c
|
---|
| 430 | PORT user_RxRF_gain = agc_g_rf_c
|
---|
| 431 | END
|
---|
| 432 |
|
---|
| 433 | BEGIN eeprom_onewire
|
---|
| 434 | PARAMETER INSTANCE = eeprom_controller
|
---|
| 435 | PARAMETER HW_VER = 1.10.a
|
---|
| 436 | PARAMETER C_MEM0_BASEADDR = 0xc5400000
|
---|
| 437 | PARAMETER C_MEM0_HIGHADDR = 0xc540ffff
|
---|
| 438 | BUS_INTERFACE SPLB = plb
|
---|
| 439 | PORT DQ0 = fpga_0_eeprom_controller_DQ0_pin
|
---|
| 440 | PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T
|
---|
| 441 | PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O
|
---|
| 442 | PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I
|
---|
| 443 | PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T
|
---|
| 444 | PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O
|
---|
| 445 | PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I
|
---|
| 446 | PORT DQ5_I = net_vcc
|
---|
| 447 | PORT DQ6_I = net_vcc
|
---|
| 448 | PORT DQ7_I = net_vcc
|
---|
| 449 | END
|
---|
| 450 |
|
---|
| 451 | BEGIN xps_ll_fifo
|
---|
| 452 | PARAMETER INSTANCE = TriMode_MAC_GMII_fifo
|
---|
| 453 | PARAMETER HW_VER = 1.02.a
|
---|
| 454 | PARAMETER C_BASEADDR = 0x81a00000
|
---|
| 455 | PARAMETER C_HIGHADDR = 0x81a0ffff
|
---|
| 456 | BUS_INTERFACE SPLB = plb
|
---|
| 457 | BUS_INTERFACE LLINK = TriMode_MAC_GMII_llink0
|
---|
| 458 | END
|
---|
| 459 |
|
---|
| 460 | BEGIN clock_generator
|
---|
| 461 | PARAMETER INSTANCE = clock_generator_0
|
---|
| 462 | PARAMETER C_CLKIN_FREQ = 40000000
|
---|
| 463 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
| 464 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
| 465 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
| 466 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
| 467 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
| 468 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
| 469 | PARAMETER C_CLKOUT1_GROUP = DCM0
|
---|
| 470 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
| 471 | PARAMETER C_CLKOUT2_FREQ = 200000000
|
---|
| 472 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
| 473 | PARAMETER C_CLKOUT2_GROUP = NONE
|
---|
| 474 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
| 475 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
| 476 | PARAMETER C_CLKOUT3_PHASE = 0
|
---|
| 477 | PARAMETER C_CLKOUT3_GROUP = NONE
|
---|
| 478 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
| 479 | PARAMETER C_CLKOUT4_FREQ = 80000000
|
---|
| 480 | PARAMETER C_CLKOUT4_PHASE = 0
|
---|
| 481 | PARAMETER C_CLKOUT4_GROUP = DCM0
|
---|
| 482 | PARAMETER C_CLKOUT4_BUF = TRUE
|
---|
| 483 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 484 | PARAMETER HW_VER = 4.03.a
|
---|
| 485 | PORT CLKIN = CLK_S
|
---|
| 486 | PORT CLKOUT0 = clk_125_0000MHz
|
---|
| 487 | PORT CLKOUT1 = clk_160_0000MHzDCM0
|
---|
| 488 | PORT CLKOUT2 = clk_200_0000MHz
|
---|
| 489 | PORT CLKOUT3 = clk_40_0000MHz
|
---|
| 490 | PORT CLKOUT4 = clk_80_0000MHzDCM0
|
---|
| 491 | PORT RST = clk_board_config_config_invalid
|
---|
| 492 | PORT LOCKED = Dcm_all_locked
|
---|
| 493 | END
|
---|
| 494 |
|
---|
| 495 | BEGIN jtagppc_cntlr
|
---|
| 496 | PARAMETER INSTANCE = jtagppc_cntlr_inst
|
---|
| 497 | PARAMETER HW_VER = 2.01.c
|
---|
| 498 | BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus
|
---|
| 499 | END
|
---|
| 500 |
|
---|
| 501 | BEGIN proc_sys_reset
|
---|
| 502 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
| 503 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
| 504 | PARAMETER HW_VER = 3.00.a
|
---|
| 505 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus
|
---|
| 506 | PORT Slowest_sync_clk = clk_40_0000MHz
|
---|
| 507 | PORT Ext_Reset_In = sys_rst_s
|
---|
| 508 | PORT Dcm_locked = Dcm_all_locked
|
---|
| 509 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
| 510 | PORT Peripheral_Reset = sys_periph_reset
|
---|
| 511 | END
|
---|
| 512 |
|
---|
| 513 | BEGIN plb_v46
|
---|
| 514 | PARAMETER INSTANCE = plb_v46_40MHz
|
---|
| 515 | PARAMETER C_DCR_INTFCE = 0
|
---|
| 516 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100
|
---|
| 517 | PARAMETER HW_VER = 1.05.a
|
---|
| 518 | PORT PLB_Clk = clk_40_0000MHz
|
---|
| 519 | PORT SYS_Rst = sys_bus_reset
|
---|
| 520 | END
|
---|
| 521 |
|
---|
| 522 | BEGIN plbv46_plbv46_bridge
|
---|
| 523 | PARAMETER INSTANCE = plbv46_plbv46_bridge_0
|
---|
| 524 | PARAMETER HW_VER = 1.04.a
|
---|
| 525 | PARAMETER C_BUS_CLOCK_RATIO = 2
|
---|
| 526 | PARAMETER C_NUM_ADDR_RNG = 2
|
---|
| 527 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000
|
---|
| 528 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff
|
---|
| 529 | PARAMETER C_RNG0_BASEADDR = 0xc6000000
|
---|
| 530 | PARAMETER C_RNG0_HIGHADDR = 0xc600ffff
|
---|
| 531 | PARAMETER C_RNG1_BASEADDR = 0xcac00000
|
---|
| 532 | PARAMETER C_RNG1_HIGHADDR = 0xcac0ffff
|
---|
| 533 | BUS_INTERFACE MPLB = plb_v46_40MHz
|
---|
| 534 | BUS_INTERFACE SPLB = plb
|
---|
| 535 | END
|
---|
| 536 |
|
---|
| 537 | BEGIN w2_warplab_buffers_plbw
|
---|
| 538 | PARAMETER INSTANCE = warplab_buffers_plbw_0
|
---|
| 539 | PARAMETER HW_VER = 1.00.a
|
---|
| 540 | PARAMETER C_BASEADDR = 0x83800000
|
---|
| 541 | PARAMETER C_HIGHADDR = 0x83bfffff
|
---|
| 542 | BUS_INTERFACE SPLB = plb
|
---|
| 543 | PORT sysgen_clk = clk_40_0000MHz
|
---|
| 544 | PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I
|
---|
| 545 | PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q
|
---|
| 546 | PORT radio2_adc_i_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin
|
---|
| 547 | PORT radio2_adc_q_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin
|
---|
| 548 | PORT startcapture = net_gnd
|
---|
| 549 | PORT StartTx = net_gnd
|
---|
| 550 | PORT StopTx = net_gnd
|
---|
| 551 | PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I
|
---|
| 552 | PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q
|
---|
| 553 | PORT rssi_adc_clk = rssi_clk_out
|
---|
| 554 | PORT debug_capturing = rxrun
|
---|
| 555 | PORT debug_transmitting = txrun
|
---|
| 556 | PORT debug_agc_done = agcsetdone
|
---|
| 557 | PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I
|
---|
| 558 | PORT radio3_adc_i_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin
|
---|
| 559 | PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q
|
---|
| 560 | PORT radio3_adc_q_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin
|
---|
| 561 | PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I
|
---|
| 562 | PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q
|
---|
| 563 | PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
| 564 | PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
| 565 | PORT agc_done = agc_is_done
|
---|
| 566 | PORT fromagc_radio1_i = dc_filtered_i_a
|
---|
| 567 | PORT fromagc_radio1_q = dc_filtered_q_a
|
---|
| 568 | PORT fromagc_radio2_i = dc_filtered_i_b
|
---|
| 569 | PORT fromagc_radio2_q = dc_filtered_q_b
|
---|
| 570 | PORT fromagc_radio3_i = dc_filtered_i_c
|
---|
| 571 | PORT fromagc_radio3_q = dc_filtered_q_c
|
---|
| 572 | PORT fromagc_radio4_i = dc_filtered_i_d
|
---|
| 573 | PORT fromagc_radio4_q = dc_filtered_q_d
|
---|
| 574 | END
|
---|
| 575 |
|
---|
| 576 | BEGIN w2_warplab_agc_plbw
|
---|
| 577 | PARAMETER INSTANCE = warplab_agc_plbw_0
|
---|
| 578 | PARAMETER HW_VER = 1.00.a
|
---|
| 579 | PARAMETER C_BASEADDR = 0xc6000000
|
---|
| 580 | PARAMETER C_HIGHADDR = 0xc600ffff
|
---|
| 581 | BUS_INTERFACE SPLB = plb_v46_40MHz
|
---|
| 582 | PORT sysgen_clk = clk_40_0000MHz
|
---|
| 583 | PORT rxhp_c = agc_rxhp_c
|
---|
| 584 | PORT rxhp_b = agc_rxhp_b
|
---|
| 585 | PORT g_rf_c = agc_g_rf_c
|
---|
| 586 | PORT g_rf_b = agc_g_rf_b
|
---|
| 587 | PORT g_bb_c = agc_g_bb_c
|
---|
| 588 | PORT g_bb_b = agc_g_bb_b
|
---|
| 589 | PORT agc_done = agc_is_done
|
---|
| 590 | PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D
|
---|
| 591 | PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D
|
---|
| 592 | PORT reset_in = net_gnd
|
---|
| 593 | PORT q_in_c = radio_bridge_slot_3_user_ADC_Q
|
---|
| 594 | PORT q_in_b = radio_bridge_slot_2_user_ADC_Q
|
---|
| 595 | PORT packet_in = net_gnd
|
---|
| 596 | PORT mreset_in = net_gnd
|
---|
| 597 | PORT i_in_c = radio_bridge_slot_3_user_ADC_I
|
---|
| 598 | PORT i_in_b = radio_bridge_slot_2_user_ADC_I
|
---|
| 599 | PORT i_out_a = dc_filtered_i_a
|
---|
| 600 | PORT i_out_b = dc_filtered_i_b
|
---|
| 601 | PORT i_out_c = dc_filtered_i_c
|
---|
| 602 | PORT i_out_d = dc_filtered_i_d
|
---|
| 603 | PORT q_out_a = dc_filtered_q_a
|
---|
| 604 | PORT q_out_b = dc_filtered_q_b
|
---|
| 605 | PORT q_out_c = dc_filtered_q_c
|
---|
| 606 | PORT q_out_d = dc_filtered_q_d
|
---|
| 607 | END
|
---|
| 608 |
|
---|
| 609 | BEGIN xps_central_dma
|
---|
| 610 | PARAMETER INSTANCE = xps_central_dma_0
|
---|
| 611 | PARAMETER HW_VER = 2.03.a
|
---|
| 612 | PARAMETER C_BASEADDR = 0x80200000
|
---|
| 613 | PARAMETER C_HIGHADDR = 0x8020ffff
|
---|
| 614 | BUS_INTERFACE MPLB = plb
|
---|
| 615 | BUS_INTERFACE SPLB = plb
|
---|
| 616 | END
|
---|
| 617 |
|
---|
| 618 | BEGIN xps_timer
|
---|
| 619 | PARAMETER INSTANCE = xps_timer_0
|
---|
| 620 | PARAMETER HW_VER = 1.02.a
|
---|
| 621 | PARAMETER C_BASEADDR = 0x83c00000
|
---|
| 622 | PARAMETER C_HIGHADDR = 0x83c0ffff
|
---|
| 623 | BUS_INTERFACE SPLB = plb
|
---|
| 624 | END
|
---|
| 625 |
|
---|
| 626 | BEGIN xps_gpio
|
---|
| 627 | PARAMETER INSTANCE = xps_gpio_0
|
---|
| 628 | PARAMETER HW_VER = 2.00.a
|
---|
| 629 | PARAMETER C_GPIO_WIDTH = 6
|
---|
| 630 | PARAMETER C_BASEADDR = 0x81400000
|
---|
| 631 | PARAMETER C_HIGHADDR = 0x8140ffff
|
---|
| 632 | BUS_INTERFACE SPLB = plb
|
---|
| 633 | PORT GPIO_IO_O = debug_sw_gpio
|
---|
| 634 | END
|
---|
| 635 |
|
---|