source: ResearchApps/PHY/WARPLAB/WARPLab_v6p2/EDK_files_w3_2radio/system.mhs

# ##############################################################################
# Template Project for WARP v3 Rev 1.1
# Family:    virtex6
# Device:    xc6vlx240t
# Package:   ff1156
# Speed Grade:  -2
# Processor number: 1
# Processor 1: microblaze_0
# Processor and primary bus clock frequency: 160.0 MHz
# Secondary bus clock frequency: 80.0 MHz
# ##############################################################################
 PARAMETER VERSION = 2.1.0


# User IO (LEDs, buttons, etc.) pins
 PORT USERIO_hexdisp_left_pin = USERIO_hexdisp_left_pin, DIR = O, VEC = [0:6]
 PORT USERIO_hexdisp_right_pin = USERIO_hexdisp_right_pin, DIR = O, VEC = [0:6]
 PORT USERIO_hexdisp_left_dp_pin = USERIO_hexdisp_left_dp_pin, DIR = O
 PORT USERIO_hexdisp_right_dp_pin = USERIO_hexdisp_right_dp_pin, DIR = O
 PORT USERIO_leds_red_pin = USERIO_leds_red_pin, DIR = O, VEC = [0:3]
 PORT USERIO_leds_green_pin = USERIO_leds_green_pin, DIR = O, VEC = [0:3]
 PORT USERIO_rfa_led_red_pin = USERIO_rfa_led_red_pin, DIR = O
 PORT USERIO_rfa_led_green_pin = USERIO_rfa_led_green_pin, DIR = O
 PORT USERIO_rfb_led_red_pin = USERIO_rfb_led_red_pin, DIR = O
 PORT USERIO_rfb_led_green_pin = USERIO_rfb_led_green_pin, DIR = O
 PORT USERIO_dipsw_pin = USERIO_dipsw_pin, DIR = I, VEC = [0:3]
 PORT USERIO_pb_u_pin = USERIO_pb_u_pin, DIR = I
 PORT USERIO_pb_m_pin = USERIO_pb_m_pin, DIR = I
 PORT USERIO_pb_d_pin = USERIO_pb_d_pin, DIR = I
# USB UART transceiver pins
 PORT UART_USB_RX_pin = UART_USB_RX_pin, DIR = I
 PORT UART_USB_TX_pin = UART_USB_TX_pin, DIR = O
# IIC EEPROM pins
 PORT IIC_EEPROM_iic_scl_pin = IIC_EEPROM_iic_scl_pin, DIR = IO
 PORT IIC_EEPROM_iic_sda_pin = IIC_EEPROM_iic_sda_pin, DIR = IO
# Eth A RGMII pins
 PORT ETH_A_TemacPhy_RST_n_pin = ETH_A_TemacPhy_RST_n_pin, DIR = O
 PORT ETH_A_RGMII_TXD_0_pin = ETH_A_RGMII_TXD_0_pin, DIR = O, VEC = [3:0]
 PORT ETH_A_RGMII_TX_CTL_0_pin = ETH_A_RGMII_TX_CTL_0_pin, DIR = O
 PORT ETH_A_RGMII_TXC_0_pin = ETH_A_RGMII_TXC_0_pin, DIR = O
 PORT ETH_A_RGMII_RXD_0_pin = ETH_A_RGMII_RXD_0_pin, DIR = I, VEC = [3:0]
 PORT ETH_A_RGMII_RX_CTL_0_pin = ETH_A_RGMII_RX_CTL_0_pin, DIR = I
 PORT ETH_A_RGMII_RXC_0_pin = ETH_A_RGMII_RXC_0_pin, DIR = I
 PORT ETH_A_MDC_0_pin = ETH_A_MDC_0_pin, DIR = O
 PORT ETH_A_MDIO_0_pin = ETH_A_MDIO_0_pin, DIR = IO
# Eth A RGMII pins
 PORT ETH_B_RGMII_TXD_0_pin = ETH_B_RGMII_TXD_0_pin, DIR = O, VEC = [3:0]
 PORT ETH_B_RGMII_TX_CTL_0_pin = ETH_B_RGMII_TX_CTL_0_pin, DIR = O
 PORT ETH_B_RGMII_TXC_0_pin = ETH_B_RGMII_TXC_0_pin, DIR = O
 PORT ETH_B_RGMII_RXD_0_pin = ETH_B_RGMII_RXD_0_pin, DIR = I, VEC = [3:0]
 PORT ETH_B_RGMII_RX_CTL_0_pin = ETH_B_RGMII_RX_CTL_0_pin, DIR = I
 PORT ETH_B_RGMII_RXC_0_pin = ETH_B_RGMII_RXC_0_pin, DIR = I
 PORT ETH_B_MDC_0_pin = ETH_B_MDC_0_pin, DIR = O
 PORT ETH_B_MDIO_0_pin = ETH_B_MDIO_0_pin, DIR = IO
# DDR3 SO-DIMM slot pins
 PORT DDR3_2GB_SODIMM_Clk_pin = DDR3_2GB_SODIMM_Clk_pin, DIR = O
 PORT DDR3_2GB_SODIMM_Clk_n_pin = DDR3_2GB_SODIMM_Clk_n_pin, DIR = O
 PORT DDR3_2GB_SODIMM_CE_pin = DDR3_2GB_SODIMM_CE_pin, DIR = O
 PORT DDR3_2GB_SODIMM_CS_n_pin = DDR3_2GB_SODIMM_CS_n_pin, DIR = O
 PORT DDR3_2GB_SODIMM_ODT_pin = DDR3_2GB_SODIMM_ODT_pin, DIR = O
 PORT DDR3_2GB_SODIMM_RAS_n_pin = DDR3_2GB_SODIMM_RAS_n_pin, DIR = O
 PORT DDR3_2GB_SODIMM_CAS_n_pin = DDR3_2GB_SODIMM_CAS_n_pin, DIR = O
 PORT DDR3_2GB_SODIMM_WE_n_pin = DDR3_2GB_SODIMM_WE_n_pin, DIR = O
 PORT DDR3_2GB_SODIMM_BankAddr_pin = DDR3_2GB_SODIMM_BankAddr_pin, DIR = O, VEC = [2:0]
 PORT DDR3_2GB_SODIMM_Addr_pin = DDR3_2GB_SODIMM_Addr_pin, DIR = O, VEC = [14:0]
 PORT DDR3_2GB_SODIMM_DQ_pin = DDR3_2GB_SODIMM_DQ_pin, DIR = IO, VEC = [31:0]
 PORT DDR3_2GB_SODIMM_DM_pin = DDR3_2GB_SODIMM_DM_pin, DIR = O, VEC = [3:0]
 PORT DDR3_2GB_SODIMM_Reset_n_pin = DDR3_2GB_SODIMM_Reset_n_pin, DIR = O
 PORT DDR3_2GB_SODIMM_DQS_pin = DDR3_2GB_SODIMM_DQS_pin, DIR = IO, VEC = [3:0]
 PORT DDR3_2GB_SODIMM_DQS_n_pin = DDR3_2GB_SODIMM_DQS_n_pin, DIR = IO, VEC = [3:0]
# AD9963 ADC/DAC control pins (RFA & RFB)
 PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O
 PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
 PORT RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O
 PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O
 PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O
 PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
 PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O
 PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O
# AD9512 clock buffer control pins (RF reference & sampling clocks)
 PORT clk_rfref_spi_cs_n_pin = clk_rfref_spi_cs_n, DIR = O
 PORT clk_rfref_spi_mosi_pin = clk_rfref_spi_mosi, DIR = O
 PORT clk_rfref_spi_sclk_pin = clk_rfref_spi_sclk, DIR = O
 PORT clk_rfref_spi_miso_pin = clk_rfref_spi_miso, DIR = I
 PORT clk_rfref_func_pin = net_vcc, DIR = O
 PORT clk_samp_spi_cs_n_pin = clk_samp_spi_cs_n, DIR = O
 PORT clk_samp_spi_mosi_pin = clk_samp_spi_mosi, DIR = O
 PORT clk_samp_spi_sclk_pin = clk_samp_spi_sclk, DIR = O
 PORT clk_samp_spi_miso_pin = clk_samp_spi_miso, DIR = I
 PORT clk_samp_func_pin = net_vcc, DIR = O
# RFA transceiver and front-end
 PORT RFA_TxEn_pin = RFA_TxEn, DIR = O
 PORT RFA_RxEn_pin = RFA_RxEn, DIR = O
 PORT RFA_RxHP_pin = RFA_RxHP, DIR = O
 PORT RFA_SHDN_pin = RFA_SHDN, DIR = O
 PORT RFA_SPI_SCLK_pin = RFA_SPI_SCLK, DIR = O
 PORT RFA_SPI_MOSI_pin = RFA_SPI_MOSI, DIR = O
 PORT RFA_SPI_CSn_pin = RFA_SPI_CSn, DIR = O
 PORT RFA_B_pin = RFA_B, DIR = O, VEC = [0:6]
 PORT RFA_LD_pin = RFA_LD, DIR = I
 PORT RFA_PAEn_24_pin = RFA_PAEn_24, DIR = O
 PORT RFA_PAEn_5_pin = RFA_PAEn_5, DIR = O
 PORT RFA_AntSw_pin = RFA_AntSw, DIR = O, VEC = [0:1]
# RFB transceiver and front-end
 PORT RFB_TxEn_pin = RFB_TxEn, DIR = O
 PORT RFB_RxEn_pin = RFB_RxEn, DIR = O
 PORT RFB_RxHP_pin = RFB_RxHP, DIR = O
 PORT RFB_SHDN_pin = RFB_SHDN, DIR = O
 PORT RFB_SPI_SCLK_pin = RFB_SPI_SCLK, DIR = O
 PORT RFB_SPI_MOSI_pin = RFB_SPI_MOSI, DIR = O
 PORT RFB_SPI_CSn_pin = RFB_SPI_CSn, DIR = O
 PORT RFB_B_pin = RFB_B, DIR = O, VEC = [0:6]
 PORT RFB_LD_pin = RFB_LD, DIR = I
 PORT RFB_PAEn_24_pin = RFB_PAEn_24, DIR = O
 PORT RFB_PAEn_5_pin = RFB_PAEn_5, DIR = O
 PORT RFB_AntSw_pin = RFB_AntSw, DIR = O, VEC = [0:1]
# RFA AD pins
 PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
 PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
 PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
 PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
 PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
 PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
# RFB AD pins
 PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
 PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
 PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
 PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
 PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
 PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
# RSSI ADC pins
 PORT RFA_RSSI_D = warplab_radio1_rssi_D, DIR = I, VEC = [9:0]
 PORT RFB_RSSI_D = warplab_radio2_rssi_D, DIR = I, VEC = [9:0]
 PORT RF_RSSI_CLK = warplab_rssi_clk, DIR = O
 PORT RF_RSSI_PD = net_gnd, DIR = O
# 80MHz sampling clock from AD9512
 PORT samp_clk_p_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
 PORT samp_clk_n_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
# 200MHz LVDS oscillator input
 PORT osc200_p_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
 PORT osc200_n_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
# System reset, tied to RESET push button
 PORT rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
 PORT debug_status = warplab_mimo_4x4_plbw_0_debug_capturing & warplab_mimo_4x4_plbw_0_debug_transmitting, DIR = O, VEC = [1:0]
 PORT debug_sw_gpio = debug_sw_gpio, DIR = O, VEC = [5:0]


BEGIN microblaze
 PARAMETER INSTANCE = microblaze_0
 PARAMETER C_USE_BARREL = 1
 PARAMETER C_DEBUG_ENABLED = 1
 PARAMETER HW_VER = 8.20.b
 PARAMETER C_UNALIGNED_EXCEPTIONS = 1
 BUS_INTERFACE DPLB = plb_primary
 BUS_INTERFACE IPLB = plb_primary
 BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
 BUS_INTERFACE DLMB = dlmb
 BUS_INTERFACE ILMB = ilmb
 PORT MB_RESET = mb_reset
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_primary
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_160MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = ilmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_160MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
 PARAMETER INSTANCE = dlmb
 PARAMETER HW_VER = 2.00.b
 PORT LMB_Clk = clk_160MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = dlmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = dlmb
 BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
 PARAMETER INSTANCE = ilmb_cntlr
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0x00000000
 PARAMETER C_HIGHADDR = 0x0000ffff
 BUS_INTERFACE SLMB = ilmb
 BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
 PARAMETER INSTANCE = lmb_bram
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = ilmb_port
 BUS_INTERFACE PORTB = dlmb_port
END

BEGIN w3_userio
 PARAMETER INSTANCE = w3_userio_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0xc0810000
 PARAMETER C_HIGHADDR = 0xc081ffff
 BUS_INTERFACE SPLB = plb_primary
 PORT hexdisp_left = USERIO_hexdisp_left_pin
 PORT hexdisp_right = USERIO_hexdisp_right_pin
 PORT hexdisp_left_dp = USERIO_hexdisp_left_dp_pin
 PORT hexdisp_right_dp = USERIO_hexdisp_right_dp_pin
 PORT leds_red = USERIO_leds_red_pin
 PORT leds_green = USERIO_leds_green_pin
 PORT rfa_led_red = USERIO_rfa_led_red_pin
 PORT rfa_led_green = USERIO_rfa_led_green_pin
 PORT rfb_led_red = USERIO_rfb_led_red_pin
 PORT rfb_led_green = USERIO_rfb_led_green_pin
 PORT dipsw = USERIO_dipsw_pin
 PORT pb_u = USERIO_pb_u_pin
 PORT pb_m = USERIO_pb_m_pin
 PORT pb_d = USERIO_pb_d_pin
 PORT usr_rfa_led_red = RFA_statLED_Rx
 PORT usr_rfa_led_green = RFA_statLED_Tx
 PORT usr_rfb_led_red = RFB_statLED_Rx
 PORT usr_rfb_led_green = RFB_statLED_Tx
 PORT DNA_Port_Clk = clk_40MHz
END

BEGIN w3_iic_eeprom
 PARAMETER INSTANCE = w3_iic_eeprom_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_BASEADDR = 0xc0870000
 PARAMETER C_HIGHADDR = 0xc087ffff
 BUS_INTERFACE SPLB = plb_primary
 PORT iic_scl = IIC_EEPROM_iic_scl_pin
 PORT iic_sda = IIC_EEPROM_iic_sda_pin
END

BEGIN xps_uartlite
 PARAMETER INSTANCE = UART_USB
 PARAMETER C_BAUDRATE = 57600
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_ODD_PARITY = 0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0xc0980000
 PARAMETER C_HIGHADDR = 0xc098ffff
 BUS_INTERFACE SPLB = plb_primary
 PORT RX = UART_USB_RX_pin
 PORT TX = UART_USB_TX_pin
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE = ETH_A
 PARAMETER C_NUM_IDELAYCTRL = 1
 PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y2
 PARAMETER C_PHY_TYPE = 3
 PARAMETER C_TEMAC1_ENABLED = 0
 PARAMETER C_BUS2CORE_CLK_RATIO = 1
 PARAMETER C_TEMAC_TYPE = 3
 PARAMETER C_TEMAC0_PHYADDR = 0b00001
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0xc0900000
 PARAMETER C_HIGHADDR = 0xc097ffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE LLINK0 = ETH_A_llink0
 PORT TemacPhy_RST_n = ETH_A_TemacPhy_RST_n_pin
 PORT GTX_CLK_0 = clk_125MHz
 PORT REFCLK = clk_200MHz
 PORT LlinkTemac0_CLK = clk_160MHz
 PORT RGMII_TXD_0 = ETH_A_RGMII_TXD_0_pin
 PORT RGMII_TX_CTL_0 = ETH_A_RGMII_TX_CTL_0_pin
 PORT RGMII_TXC_0 = ETH_A_RGMII_TXC_0_pin
 PORT RGMII_RXD_0 = ETH_A_RGMII_RXD_0_pin
 PORT RGMII_RX_CTL_0 = ETH_A_RGMII_RX_CTL_0_pin
 PORT RGMII_RXC_0 = ETH_A_RGMII_RXC_0_pin
 PORT MDC_0 = ETH_A_MDC_0_pin
 PORT MDIO_0 = ETH_A_MDIO_0_pin
END

BEGIN xps_ll_temac
 PARAMETER INSTANCE = ETH_B
 PARAMETER C_NUM_IDELAYCTRL = 0
 PARAMETER C_PHY_TYPE = 3
 PARAMETER C_TEMAC1_ENABLED = 0
 PARAMETER C_BUS2CORE_CLK_RATIO = 1
 PARAMETER C_TEMAC_TYPE = 3
 PARAMETER C_TEMAC0_PHYADDR = 0b00001
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0xc0880000
 PARAMETER C_HIGHADDR = 0xc08fffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE LLINK0 = ETH_B_llink0
 PORT GTX_CLK_0 = clk_125MHz
 PORT REFCLK = clk_200MHz
 PORT LlinkTemac0_CLK = clk_160MHz
 PORT RGMII_TXD_0 = ETH_B_RGMII_TXD_0_pin
 PORT RGMII_TX_CTL_0 = ETH_B_RGMII_TX_CTL_0_pin
 PORT RGMII_TXC_0 = ETH_B_RGMII_TXC_0_pin
 PORT RGMII_RXD_0 = ETH_B_RGMII_RXD_0_pin
 PORT RGMII_RX_CTL_0 = ETH_B_RGMII_RX_CTL_0_pin
 PORT RGMII_RXC_0 = ETH_B_RGMII_RXC_0_pin
 PORT MDC_0 = ETH_B_MDC_0_pin
 PORT MDIO_0 = ETH_B_MDIO_0_pin
END

BEGIN mpmc
 PARAMETER INSTANCE = DDR3_2GB_SODIMM
 PARAMETER C_NUM_PORTS = 1
 PARAMETER C_MEM_TYPE = DDR3
 PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
 PARAMETER C_MEM_ODT_TYPE = 1
 PARAMETER C_MEM_REG_DIMM = 0
 PARAMETER C_MEM_CLK_WIDTH = 1
 PARAMETER C_MEM_ODT_WIDTH = 1
 PARAMETER C_MEM_CE_WIDTH = 1
 PARAMETER C_MEM_CS_N_WIDTH = 1
 PARAMETER C_MEM_DATA_WIDTH = 32
 PARAMETER C_MEM_NDQS_COL0 = 4
 PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000003020100
 PARAMETER C_PIM0_BASETYPE = 2
 PARAMETER HW_VER = 6.05.a
 PARAMETER C_FAMILY = virtex6
 PARAMETER C_MPMC_BASEADDR = 0x40000000
 PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
 BUS_INTERFACE SPLB0 = plb_primary
 PORT MPMC_Clk0 = clk_160MHz
 PORT MPMC_Clk_200MHz = clk_200MHz
 PORT MPMC_Rst = sys_periph_reset
 PORT MPMC_Clk_Mem = clk_320MHz
 PORT MPMC_Clk_Rd_Base = clk_320MHz_nobuf_varphase
 PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
 PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
 PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
 PORT DDR3_Clk = DDR3_2GB_SODIMM_Clk_pin
 PORT DDR3_Clk_n = DDR3_2GB_SODIMM_Clk_n_pin
 PORT DDR3_CE = DDR3_2GB_SODIMM_CE_pin
 PORT DDR3_CS_n = DDR3_2GB_SODIMM_CS_n_pin
 PORT DDR3_ODT = DDR3_2GB_SODIMM_ODT_pin
 PORT DDR3_RAS_n = DDR3_2GB_SODIMM_RAS_n_pin
 PORT DDR3_CAS_n = DDR3_2GB_SODIMM_CAS_n_pin
 PORT DDR3_WE_n = DDR3_2GB_SODIMM_WE_n_pin
 PORT DDR3_BankAddr = DDR3_2GB_SODIMM_BankAddr_pin
 PORT DDR3_Addr = DDR3_2GB_SODIMM_Addr_pin
 PORT DDR3_DQ = DDR3_2GB_SODIMM_DQ_pin
 PORT DDR3_DM = DDR3_2GB_SODIMM_DM_pin
 PORT DDR3_Reset_n = DDR3_2GB_SODIMM_Reset_n_pin
 PORT DDR3_DQS = DDR3_2GB_SODIMM_DQS_pin
 PORT DDR3_DQS_n = DDR3_2GB_SODIMM_DQS_n_pin
END

BEGIN xps_ll_fifo
 PARAMETER INSTANCE = ETH_A_fifo
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0xc09d0000
 PARAMETER C_HIGHADDR = 0xc09dffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE LLINK = ETH_A_llink0
END

BEGIN xps_ll_fifo
 PARAMETER INSTANCE = ETH_B_fifo
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0xc09b0000
 PARAMETER C_HIGHADDR = 0xc09bffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE LLINK = ETH_B_llink0
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_ProcBusSamp_Clocks
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
# 80MHz clock input (driven by AD9512 for sampling clock)
 PARAMETER C_CLKIN_FREQ = 80000000
# 2x Sampling clock 0 deg phase
 PARAMETER C_CLKOUT0_FREQ = 80000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
# MB and primary PLB
 PARAMETER C_CLKOUT1_FREQ = 160000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT1_BUF = TRUE
# Sampling clock 0 deg phase
 PARAMETER C_CLKOUT2_FREQ = 40000000
 PARAMETER C_CLKOUT2_PHASE = 0
 PARAMETER C_CLKOUT2_GROUP = MMCM0
 PARAMETER C_CLKOUT2_BUF = TRUE
# Sampling clock 90 deg phase
 PARAMETER C_CLKOUT3_FREQ = 40000000
 PARAMETER C_CLKOUT3_PHASE = 90
 PARAMETER C_CLKOUT3_BUF = TRUE
 PARAMETER C_CLKOUT3_GROUP = MMCM0
 PORT CLKIN = ad_refclk_in
 PORT CLKOUT0 = clk_80MHz
 PORT CLKOUT1 = clk_160MHz
 PORT CLKOUT2 = clk_40MHz
 PORT CLKOUT3 = clk_40MHz_90degphase
 PORT RST = sys_rst_s
 PORT LOCKED = clk_gen_0_locked
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_asyncClks
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
# 200MHz clock input (driven by 200MHz LVDS oscillator)
 PARAMETER C_CLKIN_FREQ = 200000000
# TEMAC TxClk
 PARAMETER C_CLKOUT0_FREQ = 125000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = NONE
 PARAMETER C_CLKOUT0_BUF = TRUE
# IDELAYCTRL refclk
 PARAMETER C_CLKOUT1_FREQ = 200000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = NONE
 PARAMETER C_CLKOUT1_BUF = TRUE
 PORT CLKIN = osc200_in
 PORT CLKOUT0 = clk_125MHz
 PORT CLKOUT1 = clk_200MHz
 PORT RST = sys_rst_s
 PORT LOCKED = clk_gen_1_locked
END

BEGIN clock_generator
 PARAMETER INSTANCE = clock_generator_MPMC_Clocks
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 4.03.a
# 80MHz clock input (driven by other clock generator)
 PARAMETER C_CLKIN_FREQ = 80000000
# MPMC DRAM clock (2x bus)
 PARAMETER C_CLKOUT0_FREQ = 320000000
 PARAMETER C_CLKOUT0_PHASE = 0
 PARAMETER C_CLKOUT0_GROUP = MMCM0
 PARAMETER C_CLKOUT0_BUF = TRUE
# MPMC DRAM clock (2x bus, variable phase)
 PARAMETER C_CLKOUT1_FREQ = 320000000
 PARAMETER C_CLKOUT1_PHASE = 0
 PARAMETER C_CLKOUT1_GROUP = MMCM0
 PARAMETER C_CLKOUT1_BUF = FALSE
 PARAMETER C_CLKOUT1_VARIABLE_PHASE = TRUE
 PARAMETER C_PSDONE_GROUP = MMCM0
 PORT CLKIN = clk_80MHz
 PORT CLKOUT0 = clk_320MHz
 PORT CLKOUT1 = clk_320MHz_nobuf_varphase
 PORT PSCLK = clk_80MHz
 PORT PSEN = MPMC_DCM_PSEN
 PORT PSINCDEC = MPMC_DCM_PSINCDEC
 PORT PSDONE = MPMC_DCM_PSDONE
 PORT RST = sys_rst_s
 PORT LOCKED = clk_gen_2_locked
END

BEGIN mdm
 PARAMETER INSTANCE = mdm_0
 PARAMETER C_MB_DBG_PORTS = 1
 PARAMETER C_USE_UART = 1
 PARAMETER HW_VER = 2.00.b
 PARAMETER C_BASEADDR = 0xc0860000
 PARAMETER C_HIGHADDR = 0xc086ffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
 PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
 PARAMETER INSTANCE = proc_sys_reset_0
 PARAMETER C_EXT_RESET_HIGH = 1
 PARAMETER HW_VER = 3.00.a
 PORT Slowest_sync_clk = clk_40MHz
 PORT Ext_Reset_In = sys_rst_s
 PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
 PORT Dcm_locked = clk_gen_all_locked
 PORT MB_Reset = mb_reset
 PORT Bus_Struct_Reset = sys_bus_reset
 PORT Peripheral_Reset = sys_periph_reset
END

BEGIN util_reduced_logic
 PARAMETER INSTANCE = clk_gen_locked_AND
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_OPERATION = AND
 PARAMETER C_SIZE = 3
 PORT Op1 = clk_gen_0_locked & clk_gen_1_locked & clk_gen_2_locked
 PORT Res = clk_gen_all_locked
END

BEGIN bram_block
 PARAMETER INSTANCE = bram_block_0
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_0
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0xc0840000
 PARAMETER C_HIGHADDR = 0xc085ffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
END

BEGIN bram_block
 PARAMETER INSTANCE = bram_block_1
 PARAMETER HW_VER = 1.00.a
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
END

BEGIN xps_bram_if_cntlr
 PARAMETER INSTANCE = xps_bram_if_cntlr_1
 PARAMETER HW_VER = 1.00.b
 PARAMETER C_SPLB_NATIVE_DWIDTH = 32
 PARAMETER C_BASEADDR = 0xc09f0000
 PARAMETER C_HIGHADDR = 0xc09fffff
 BUS_INTERFACE SPLB = plb_primary
 BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
END

BEGIN xps_timer
 PARAMETER INSTANCE = xps_timer_0
 PARAMETER HW_VER = 1.02.a
 PARAMETER C_BASEADDR = 0x80a00000
 PARAMETER C_HIGHADDR = 0x80a0ffff
 BUS_INTERFACE SPLB = plb_secondary_80MHz
END

# ###############
# WARP pcores
# ###############
BEGIN w3_clock_controller
 PARAMETER INSTANCE = w3_clock_controller_0
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0xc0990000
 PARAMETER C_HIGHADDR = 0xc099ffff
 BUS_INTERFACE SPLB = plb_primary
 PORT rfref_spi_cs_n = clk_rfref_spi_cs_n
 PORT samp_spi_cs_n = clk_samp_spi_cs_n
 PORT samp_spi_mosi = clk_samp_spi_mosi
 PORT rfref_spi_mosi = clk_rfref_spi_mosi
 PORT samp_spi_sclk = clk_samp_spi_sclk
 PORT rfref_spi_sclk = clk_rfref_spi_sclk
 PORT samp_spi_miso = clk_samp_spi_miso
 PORT rfref_spi_miso = clk_rfref_spi_miso
 PORT usr_status = net_gnd
END

BEGIN w3_ad_controller
 PARAMETER INSTANCE = w3_ad_controller_0
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0xc09e0000
 PARAMETER C_HIGHADDR = 0xc09effff
 BUS_INTERFACE SPLB = plb_primary
 PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
 PORT RFB_AD_reset_n = RFB_AD_reset_n
 PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
 PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
 PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
 PORT RFA_AD_reset_n = RFA_AD_reset_n
 PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
 PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
END

BEGIN radio_controller
 PARAMETER INSTANCE = radio_controller_0
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_BASEADDR = 0xc0800000
 PARAMETER C_HIGHADDR = 0xc080ffff
 BUS_INTERFACE SPLB = plb_primary
 PORT RFA_TxEn = RFA_TxEn
 PORT RFA_RxEn = RFA_RxEn
 PORT RFA_RxHP = RFA_RxHP
 PORT RFA_SHDN = RFA_SHDN
 PORT RFA_SPI_SCLK = RFA_SPI_SCLK
 PORT RFA_SPI_MOSI = RFA_SPI_MOSI
 PORT RFA_SPI_CSn = RFA_SPI_CSn
 PORT RFA_B = RFA_B
 PORT RFA_LD = RFA_LD
 PORT RFA_PAEn_24 = RFA_PAEn_24
 PORT RFA_PAEn_5 = RFA_PAEn_5
 PORT RFA_AntSw = RFA_AntSw
 PORT RFB_TxEn = RFB_TxEn
 PORT RFB_RxEn = RFB_RxEn
 PORT RFB_RxHP = RFB_RxHP
 PORT RFB_SHDN = RFB_SHDN
 PORT RFB_SPI_SCLK = RFB_SPI_SCLK
 PORT RFB_SPI_MOSI = RFB_SPI_MOSI
 PORT RFB_SPI_CSn = RFB_SPI_CSn
 PORT RFB_B = RFB_B
 PORT RFB_LD = RFB_LD
 PORT RFB_PAEn_24 = RFB_PAEn_24
 PORT RFB_PAEn_5 = RFB_PAEn_5
 PORT RFB_AntSw = RFB_AntSw
 PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
 PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
 PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
 PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
 PORT usr_RFA_RxHP = agc_rxhp_a
 PORT usr_RFB_RxHP = agc_rxhp_b
 PORT usr_RFA_RxGainRF = agc_g_rf_a
 PORT usr_RFB_RxGainRF = agc_g_rf_b
 PORT usr_RFA_RxGainBB = agc_g_bb_a
 PORT usr_RFB_RxGainBB = agc_g_bb_b
END

BEGIN w3_ad_bridge
 PARAMETER INSTANCE = w3_ad_bridge_0
# exclude IDELAYCTRL, since TEMACs include them
 PARAMETER INCLUDE_IDELAYCTRL = 0
 PARAMETER HW_VER = 3.00.g
# Clock ports (inputs to w3_ad_bridge)
 PORT clk200 = net_gnd
 PORT sys_samp_clk_Tx = clk_40MHz
 PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
 PORT sys_samp_clk_Rx = clk_40MHz
# Top-level AD9963 ports
 PORT ad_RFA_TXD = rfa_txd
 PORT ad_RFA_TXCLK = rfa_txclk
 PORT ad_RFA_TXIQ = rfa_txiq
 PORT ad_RFA_TRXD = rfa_trxd
 PORT ad_RFA_TRXCLK = rfa_trxclk
 PORT ad_RFA_TRXIQ = rfa_trxiq
 PORT ad_RFB_TXD = rfb_txd
 PORT ad_RFB_TXCLK = rfb_txclk
 PORT ad_RFB_TXIQ = rfb_txiq
 PORT ad_RFB_TRXD = rfb_trxd
 PORT ad_RFB_TRXCLK = rfb_trxclk
 PORT ad_RFB_TRXIQ = rfb_trxiq
# ####
# User ports - connect these to custom logic
# Each port is Fix12_11
 PORT user_RFA_TXD_I = warplab_radio1_Tx_I
 PORT user_RFA_TXD_Q = warplab_radio1_Tx_Q
 PORT user_RFA_RXD_I = warplab_radio1_Rx_I
 PORT user_RFA_RXD_Q = warplab_radio1_Rx_Q
 PORT user_RFB_TXD_I = warplab_radio2_Tx_I
 PORT user_RFB_TXD_Q = warplab_radio2_Tx_Q
 PORT user_RFB_RXD_I = warplab_radio2_Rx_I
 PORT user_RFB_RXD_Q = warplab_radio2_Rx_Q
END

# RFA Rx
# PORT user_RFA_RXD_I = <user net>
# PORT user_RFA_RXD_Q = <user net>
# RFB Rx
# PORT user_RFB_RXD_I = <user net>
# PORT user_RFB_RXD_Q = <user net>
BEGIN plbv46_plbv46_bridge
 PARAMETER INSTANCE = plb_primary_secondary_bridge
 PARAMETER HW_VER = 1.04.a
 PARAMETER C_BUS_CLOCK_RATIO = 2
 PARAMETER C_NUM_ADDR_RNG = 1
 PARAMETER C_BRIDGE_BASEADDR = 0xc0830000
 PARAMETER C_BRIDGE_HIGHADDR = 0xc083ffff
 PARAMETER C_RNG0_BASEADDR = 0x80800000
 PARAMETER C_RNG0_HIGHADDR = 0x80ffffff
 BUS_INTERFACE MPLB = plb_secondary_80MHz
 BUS_INTERFACE SPLB = plb_primary
END

BEGIN plb_v46
 PARAMETER INSTANCE = plb_secondary_80MHz
 PARAMETER HW_VER = 1.05.a
 PORT PLB_Clk = clk_80MHz
 PORT SYS_Rst = sys_bus_reset
END

BEGIN xps_sysmon_adc
 PARAMETER INSTANCE = xps_sysmon_adc_0
 PARAMETER HW_VER = 3.00.b
 PARAMETER C_DCLK_RATIO = 2
 PARAMETER C_BASEADDR = 0xc09c0000
 PARAMETER C_HIGHADDR = 0xc09cffff
 BUS_INTERFACE SPLB = plb_primary
END

BEGIN w3_warplab_buffers_plbw
 PARAMETER INSTANCE = warplab_buffers_plbw_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x80c00000
 PARAMETER C_HIGHADDR = 0x80ffffff
 BUS_INTERFACE SPLB = plb_secondary_80MHz
 PORT sysgen_clk = clk_40MHz
 PORT radio1_dac_i = warplab_radio1_Tx_I
 PORT radio1_dac_q = warplab_radio1_Tx_Q
 PORT radio2_dac_i = warplab_radio2_Tx_I
 PORT radio2_dac_q = warplab_radio2_Tx_Q
 PORT radio1_adc_i = warplab_radio1_Rx_I
 PORT radio1_adc_q = warplab_radio1_Rx_Q
 PORT radio2_adc_i = warplab_radio2_Rx_I
 PORT radio2_adc_q = warplab_radio2_Rx_Q
 PORT radio1_rssi = warplab_radio1_rssi_D
 PORT radio2_rssi = warplab_radio2_rssi_D
 PORT rssi_adc_clk = warplab_rssi_clk
 PORT startcapture = net_gnd
 PORT starttx = net_gnd
 PORT stoptx = net_gnd
 PORT agc_done = agc_is_done
 PORT fromagc_radio1_i = dc_filtered_i_a
 PORT fromagc_radio1_q = dc_filtered_q_a
 PORT fromagc_radio2_i = dc_filtered_i_b
 PORT fromagc_radio2_q = dc_filtered_q_b
 PORT debug_capturing = warplab_mimo_4x4_plbw_0_debug_capturing
 PORT debug_transmitting = warplab_mimo_4x4_plbw_0_debug_transmitting
END

BEGIN w3_warplab_agc_plbw
 PARAMETER INSTANCE = warplab_agc_plbw_0
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BASEADDR = 0x80900000
 PARAMETER C_HIGHADDR = 0x8090ffff
 BUS_INTERFACE SPLB = plb_secondary_80MHz
 PORT sysgen_clk = clk_40MHz
 PORT rxhp_b = agc_rxhp_b
 PORT rxhp_a = agc_rxhp_a
 PORT g_rf_b = agc_g_rf_b
 PORT g_rf_a = agc_g_rf_a
 PORT g_bb_b = agc_g_bb_b
 PORT g_bb_a = agc_g_bb_a
 PORT agc_done = agc_is_done
 PORT rssi_in_b = warplab_radio2_rssi_D
 PORT rssi_in_a = warplab_radio1_rssi_D
 PORT reset_in = net_gnd
 PORT q_in_b = warplab_radio2_Rx_Q
 PORT q_in_a = warplab_radio1_Rx_Q
 PORT packet_in = net_gnd
 PORT mreset_in = net_gnd
 PORT i_in_b = warplab_radio2_Rx_I
 PORT i_in_a = warplab_radio1_Rx_I
 PORT i_out_a = dc_filtered_i_a
 PORT i_out_b = dc_filtered_i_b
 PORT q_out_a = dc_filtered_q_a
 PORT q_out_b = dc_filtered_q_b
END

BEGIN xps_central_dma
 PARAMETER INSTANCE = xps_central_dma_0
 PARAMETER HW_VER = 2.03.a
 PARAMETER C_BASEADDR = 0xc09a0000
 PARAMETER C_HIGHADDR = 0xc09affff
 BUS_INTERFACE MPLB = plb_primary
 BUS_INTERFACE SPLB = plb_primary
END

BEGIN xps_gpio
 PARAMETER INSTANCE = xps_gpio_0
 PARAMETER HW_VER = 2.00.a
 PARAMETER C_GPIO_WIDTH = 6
 PARAMETER C_BASEADDR = 0xc0820000
 PARAMETER C_HIGHADDR = 0xc082ffff
 BUS_INTERFACE SPLB = plb_primary
 PORT GPIO_IO_O = debug_sw_gpio
END