1 | |
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2 | # ############################################################################## |
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3 | # Created by Base System Builder Wizard for Xilinx EDK 13.4 Build EDK_O.87xd |
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4 | # Thu Jun 28 08:17:23 2012 |
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5 | # Target Board: Rice University - WARP Project WARP Kits (FPGA/Clock/Radio Boards) Rev FPGA 2.2 / Radio 1.4 / Clock 1.1 (XPS 13 version) |
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6 | # Family: virtex4 |
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7 | # Device: XC4VFX100 |
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8 | # Package: FF1517 |
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9 | # Speed Grade: -11 |
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10 | # Processor number: 1 |
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11 | # Processor 1: ppc405_0 |
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12 | # Processor clock frequency: 160.0 |
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13 | # Bus clock frequency: 80.0 |
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14 | # Debug Interface: FPGA JTAG |
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15 | # ############################################################################## |
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16 | PARAMETER VERSION = 2.1.0 |
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17 | |
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18 | |
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19 | PORT fpga_0_UserIO_LEDs_out_pin = fpga_0_UserIO_LEDs_out_pin, DIR = O, VEC = [0:7] |
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20 | PORT fpga_0_UserIO_IOEx_SDA_pin = fpga_0_UserIO_IOEx_SDA_pin, DIR = O |
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21 | PORT fpga_0_UserIO_IOEx_SCL_pin = fpga_0_UserIO_IOEx_SCL_pin, DIR = O |
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22 | PORT fpga_0_UserIO_PB_in_pin = fpga_0_UserIO_PB_in_pin, DIR = I, VEC = [0:3] |
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23 | PORT fpga_0_UserIO_DIPSW_in_pin = fpga_0_UserIO_DIPSW_in_pin, DIR = I, VEC = [0:3] |
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24 | PORT fpga_0_rs232_db9_RX_pin = fpga_0_rs232_db9_RX_pin, DIR = I |
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25 | PORT fpga_0_rs232_db9_TX_pin = fpga_0_rs232_db9_TX_pin, DIR = O |
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26 | PORT fpga_0_rs232_usb_RX_pin = fpga_0_rs232_usb_RX_pin, DIR = I |
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27 | PORT fpga_0_rs232_usb_TX_pin = fpga_0_rs232_usb_TX_pin, DIR = O |
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28 | PORT fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin, DIR = O |
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29 | PORT fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin, DIR = I |
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30 | PORT fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin, DIR = O, VEC = [7:0] |
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31 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin, DIR = O |
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32 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin, DIR = O |
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33 | PORT fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin, DIR = O |
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34 | PORT fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin, DIR = I, VEC = [7:0] |
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35 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin, DIR = I |
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36 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin, DIR = I |
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37 | PORT fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin, DIR = I |
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38 | PORT fpga_0_TriMode_MAC_GMII_MDC_0_pin = fpga_0_TriMode_MAC_GMII_MDC_0_pin, DIR = O |
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39 | PORT fpga_0_TriMode_MAC_GMII_MDIO_0_pin = fpga_0_TriMode_MAC_GMII_MDIO_0_pin, DIR = IO |
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40 | PORT fpga_0_clk_board_config_sys_clk_pin = fpga_0_clk_board_config_sys_clk_pin, DIR = I |
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41 | PORT fpga_0_clk_board_config_cfg_radio_dat_out_pin = fpga_0_clk_board_config_cfg_radio_dat_out_pin, DIR = O |
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42 | PORT fpga_0_clk_board_config_cfg_radio_csb_out_pin = fpga_0_clk_board_config_cfg_radio_csb_out_pin, DIR = O |
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43 | PORT fpga_0_clk_board_config_cfg_radio_en_out_pin = fpga_0_clk_board_config_cfg_radio_en_out_pin, DIR = O |
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44 | PORT fpga_0_clk_board_config_cfg_radio_clk_out_pin = fpga_0_clk_board_config_cfg_radio_clk_out_pin, DIR = O |
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45 | PORT fpga_0_clk_board_config_cfg_logic_dat_out_pin = fpga_0_clk_board_config_cfg_logic_dat_out_pin, DIR = O |
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46 | PORT fpga_0_clk_board_config_cfg_logic_csb_out_pin = fpga_0_clk_board_config_cfg_logic_csb_out_pin, DIR = O |
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47 | PORT fpga_0_clk_board_config_cfg_logic_en_out_pin = fpga_0_clk_board_config_cfg_logic_en_out_pin, DIR = O |
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48 | PORT fpga_0_clk_board_config_cfg_logic_clk_out_pin = fpga_0_clk_board_config_cfg_logic_clk_out_pin, DIR = O |
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49 | PORT fpga_0_radio_bridge_slot_1_converter_clock_out_pin = fpga_0_radio_bridge_slot_1_converter_clock_out_pin, DIR = O |
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50 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin, DIR = O |
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51 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_I_pin = fpga_0_radio_bridge_slot_1_radio_DAC_I_pin, DIR = O, VEC = [15:0] |
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52 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin, DIR = O, VEC = [15:0] |
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53 | PORT fpga_0_radio_bridge_slot_1_radio_ADC_I_pin = fpga_0_radio_bridge_slot_1_radio_ADC_I_pin, DIR = I, VEC = [13:0] |
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54 | PORT fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin, DIR = I, VEC = [13:0] |
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55 | PORT fpga_0_radio_bridge_slot_1_radio_B_pin = fpga_0_radio_bridge_slot_1_radio_B_pin, DIR = O, VEC = [6:0] |
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56 | PORT fpga_0_radio_bridge_slot_1_radio_ANTSW_pin = fpga_0_radio_bridge_slot_1_radio_ANTSW_pin, DIR = O, VEC = [1:0] |
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57 | PORT fpga_0_radio_bridge_slot_1_radio_LED_pin = fpga_0_radio_bridge_slot_1_radio_LED_pin, DIR = O, VEC = [2:0] |
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58 | PORT fpga_0_radio_bridge_slot_1_radio_DIPSW_pin = fpga_0_radio_bridge_slot_1_radio_DIPSW_pin, DIR = I, VEC = [3:0] |
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59 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0] |
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60 | PORT fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin, DIR = IO |
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61 | PORT fpga_0_radio_bridge_slot_1_radio_spi_clk_pin = fpga_0_radio_bridge_slot_1_radio_spi_clk_pin, DIR = O |
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62 | PORT fpga_0_radio_bridge_slot_1_radio_spi_data_pin = fpga_0_radio_bridge_slot_1_radio_spi_data_pin, DIR = O |
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63 | PORT fpga_0_radio_bridge_slot_1_radio_spi_cs_pin = fpga_0_radio_bridge_slot_1_radio_spi_cs_pin, DIR = O |
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64 | PORT fpga_0_radio_bridge_slot_1_radio_SHDN_pin = fpga_0_radio_bridge_slot_1_radio_SHDN_pin, DIR = O |
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65 | PORT fpga_0_radio_bridge_slot_1_radio_TxEn_pin = fpga_0_radio_bridge_slot_1_radio_TxEn_pin, DIR = O |
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66 | PORT fpga_0_radio_bridge_slot_1_radio_RxEn_pin = fpga_0_radio_bridge_slot_1_radio_RxEn_pin, DIR = O |
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67 | PORT fpga_0_radio_bridge_slot_1_radio_RxHP_pin = fpga_0_radio_bridge_slot_1_radio_RxHP_pin, DIR = O |
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68 | PORT fpga_0_radio_bridge_slot_1_radio_24PA_pin = fpga_0_radio_bridge_slot_1_radio_24PA_pin, DIR = O |
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69 | PORT fpga_0_radio_bridge_slot_1_radio_5PA_pin = fpga_0_radio_bridge_slot_1_radio_5PA_pin, DIR = O |
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70 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin, DIR = O |
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71 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin, DIR = O |
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72 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin, DIR = O |
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73 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin, DIR = O |
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74 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin, DIR = O |
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75 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin, DIR = O |
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76 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin, DIR = O |
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77 | PORT fpga_0_radio_bridge_slot_1_radio_LD_pin = fpga_0_radio_bridge_slot_1_radio_LD_pin, DIR = I |
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78 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin, DIR = I |
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79 | PORT fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin, DIR = I |
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80 | PORT fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin, DIR = I |
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81 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin, DIR = I |
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82 | PORT fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin, DIR = O |
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83 | PORT fpga_0_radio_bridge_slot_1_dac_spi_data_pin = fpga_0_radio_bridge_slot_1_dac_spi_data_pin, DIR = O |
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84 | PORT fpga_0_radio_bridge_slot_1_dac_spi_cs_pin = fpga_0_radio_bridge_slot_1_dac_spi_cs_pin, DIR = O |
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85 | PORT fpga_0_radio_bridge_slot_1_dac_spi_clk_pin = fpga_0_radio_bridge_slot_1_dac_spi_clk_pin, DIR = O |
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86 | PORT fpga_0_radio_bridge_slot_2_converter_clock_out_pin = fpga_0_radio_bridge_slot_2_converter_clock_out_pin, DIR = O |
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87 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin, DIR = O |
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88 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_I_pin = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin, DIR = O, VEC = [15:0] |
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89 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin, DIR = O, VEC = [15:0] |
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90 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_I_pin = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin, DIR = I, VEC = [13:0] |
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91 | PORT fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin, DIR = I, VEC = [13:0] |
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92 | PORT fpga_0_radio_bridge_slot_2_radio_B_pin = fpga_0_radio_bridge_slot_2_radio_B_pin, DIR = O, VEC = [6:0] |
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93 | PORT fpga_0_radio_bridge_slot_2_radio_ANTSW_pin = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin, DIR = O, VEC = [1:0] |
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94 | PORT fpga_0_radio_bridge_slot_2_radio_LED_pin = fpga_0_radio_bridge_slot_2_radio_LED_pin, DIR = O, VEC = [2:0] |
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95 | PORT fpga_0_radio_bridge_slot_2_radio_DIPSW_pin = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin, DIR = I, VEC = [3:0] |
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96 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0] |
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97 | PORT fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin, DIR = IO |
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98 | PORT fpga_0_radio_bridge_slot_2_radio_spi_clk_pin = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin, DIR = O |
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99 | PORT fpga_0_radio_bridge_slot_2_radio_spi_data_pin = fpga_0_radio_bridge_slot_2_radio_spi_data_pin, DIR = O |
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100 | PORT fpga_0_radio_bridge_slot_2_radio_spi_cs_pin = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin, DIR = O |
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101 | PORT fpga_0_radio_bridge_slot_2_radio_SHDN_pin = fpga_0_radio_bridge_slot_2_radio_SHDN_pin, DIR = O |
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102 | PORT fpga_0_radio_bridge_slot_2_radio_TxEn_pin = fpga_0_radio_bridge_slot_2_radio_TxEn_pin, DIR = O |
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103 | PORT fpga_0_radio_bridge_slot_2_radio_RxEn_pin = fpga_0_radio_bridge_slot_2_radio_RxEn_pin, DIR = O |
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104 | PORT fpga_0_radio_bridge_slot_2_radio_RxHP_pin = fpga_0_radio_bridge_slot_2_radio_RxHP_pin, DIR = O |
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105 | PORT fpga_0_radio_bridge_slot_2_radio_24PA_pin = fpga_0_radio_bridge_slot_2_radio_24PA_pin, DIR = O |
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106 | PORT fpga_0_radio_bridge_slot_2_radio_5PA_pin = fpga_0_radio_bridge_slot_2_radio_5PA_pin, DIR = O |
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107 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin, DIR = O |
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108 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin, DIR = O |
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109 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin, DIR = O |
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110 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin, DIR = O |
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111 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin, DIR = O |
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112 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin, DIR = O |
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113 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin, DIR = O |
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114 | PORT fpga_0_radio_bridge_slot_2_radio_LD_pin = fpga_0_radio_bridge_slot_2_radio_LD_pin, DIR = I |
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115 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin, DIR = I |
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116 | PORT fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin, DIR = I |
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117 | PORT fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin, DIR = I |
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118 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin, DIR = I |
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119 | PORT fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin, DIR = O |
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120 | PORT fpga_0_radio_bridge_slot_2_dac_spi_data_pin = fpga_0_radio_bridge_slot_2_dac_spi_data_pin, DIR = O |
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121 | PORT fpga_0_radio_bridge_slot_2_dac_spi_cs_pin = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin, DIR = O |
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122 | PORT fpga_0_radio_bridge_slot_2_dac_spi_clk_pin = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin, DIR = O |
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123 | PORT fpga_0_radio_bridge_slot_3_converter_clock_out_pin = fpga_0_radio_bridge_slot_3_converter_clock_out_pin, DIR = O |
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124 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin, DIR = O |
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125 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_I_pin = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin, DIR = O, VEC = [15:0] |
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126 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin, DIR = O, VEC = [15:0] |
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127 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_I_pin = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin, DIR = I, VEC = [13:0] |
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128 | PORT fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin, DIR = I, VEC = [13:0] |
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129 | PORT fpga_0_radio_bridge_slot_3_radio_B_pin = fpga_0_radio_bridge_slot_3_radio_B_pin, DIR = O, VEC = [6:0] |
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130 | PORT fpga_0_radio_bridge_slot_3_radio_ANTSW_pin = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin, DIR = O, VEC = [1:0] |
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131 | PORT fpga_0_radio_bridge_slot_3_radio_LED_pin = fpga_0_radio_bridge_slot_3_radio_LED_pin, DIR = O, VEC = [2:0] |
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132 | PORT fpga_0_radio_bridge_slot_3_radio_DIPSW_pin = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin, DIR = I, VEC = [3:0] |
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133 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0] |
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134 | PORT fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin, DIR = IO |
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135 | PORT fpga_0_radio_bridge_slot_3_radio_spi_clk_pin = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin, DIR = O |
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136 | PORT fpga_0_radio_bridge_slot_3_radio_spi_data_pin = fpga_0_radio_bridge_slot_3_radio_spi_data_pin, DIR = O |
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137 | PORT fpga_0_radio_bridge_slot_3_radio_spi_cs_pin = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin, DIR = O |
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138 | PORT fpga_0_radio_bridge_slot_3_radio_SHDN_pin = fpga_0_radio_bridge_slot_3_radio_SHDN_pin, DIR = O |
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139 | PORT fpga_0_radio_bridge_slot_3_radio_TxEn_pin = fpga_0_radio_bridge_slot_3_radio_TxEn_pin, DIR = O |
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140 | PORT fpga_0_radio_bridge_slot_3_radio_RxEn_pin = fpga_0_radio_bridge_slot_3_radio_RxEn_pin, DIR = O |
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141 | PORT fpga_0_radio_bridge_slot_3_radio_RxHP_pin = fpga_0_radio_bridge_slot_3_radio_RxHP_pin, DIR = O |
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142 | PORT fpga_0_radio_bridge_slot_3_radio_24PA_pin = fpga_0_radio_bridge_slot_3_radio_24PA_pin, DIR = O |
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143 | PORT fpga_0_radio_bridge_slot_3_radio_5PA_pin = fpga_0_radio_bridge_slot_3_radio_5PA_pin, DIR = O |
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144 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin, DIR = O |
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145 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin, DIR = O |
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146 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin, DIR = O |
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147 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin, DIR = O |
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148 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin, DIR = O |
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149 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin, DIR = O |
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150 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin, DIR = O |
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151 | PORT fpga_0_radio_bridge_slot_3_radio_LD_pin = fpga_0_radio_bridge_slot_3_radio_LD_pin, DIR = I |
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152 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin, DIR = I |
---|
153 | PORT fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin, DIR = I |
---|
154 | PORT fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin, DIR = I |
---|
155 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin, DIR = I |
---|
156 | PORT fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin, DIR = O |
---|
157 | PORT fpga_0_radio_bridge_slot_3_dac_spi_data_pin = fpga_0_radio_bridge_slot_3_dac_spi_data_pin, DIR = O |
---|
158 | PORT fpga_0_radio_bridge_slot_3_dac_spi_cs_pin = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin, DIR = O |
---|
159 | PORT fpga_0_radio_bridge_slot_3_dac_spi_clk_pin = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin, DIR = O |
---|
160 | PORT fpga_0_radio_bridge_slot_4_converter_clock_out_pin = fpga_0_radio_bridge_slot_4_converter_clock_out_pin, DIR = O |
---|
161 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin, DIR = O |
---|
162 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_I_pin = fpga_0_radio_bridge_slot_4_radio_DAC_I_pin, DIR = O, VEC = [15:0] |
---|
163 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin = fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin, DIR = O, VEC = [15:0] |
---|
164 | PORT fpga_0_radio_bridge_slot_4_radio_ADC_I_pin = fpga_0_radio_bridge_slot_4_radio_ADC_I_pin, DIR = I, VEC = [13:0] |
---|
165 | PORT fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin = fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin, DIR = I, VEC = [13:0] |
---|
166 | PORT fpga_0_radio_bridge_slot_4_radio_B_pin = fpga_0_radio_bridge_slot_4_radio_B_pin, DIR = O, VEC = [6:0] |
---|
167 | PORT fpga_0_radio_bridge_slot_4_radio_ANTSW_pin = fpga_0_radio_bridge_slot_4_radio_ANTSW_pin, DIR = O, VEC = [1:0] |
---|
168 | PORT fpga_0_radio_bridge_slot_4_radio_LED_pin = fpga_0_radio_bridge_slot_4_radio_LED_pin, DIR = O, VEC = [2:0] |
---|
169 | PORT fpga_0_radio_bridge_slot_4_radio_DIPSW_pin = fpga_0_radio_bridge_slot_4_radio_DIPSW_pin, DIR = I, VEC = [3:0] |
---|
170 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin, DIR = I, VEC = [9:0] |
---|
171 | PORT fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin, DIR = IO |
---|
172 | PORT fpga_0_radio_bridge_slot_4_radio_spi_clk_pin = fpga_0_radio_bridge_slot_4_radio_spi_clk_pin, DIR = O |
---|
173 | PORT fpga_0_radio_bridge_slot_4_radio_spi_data_pin = fpga_0_radio_bridge_slot_4_radio_spi_data_pin, DIR = O |
---|
174 | PORT fpga_0_radio_bridge_slot_4_radio_spi_cs_pin = fpga_0_radio_bridge_slot_4_radio_spi_cs_pin, DIR = O |
---|
175 | PORT fpga_0_radio_bridge_slot_4_radio_SHDN_pin = fpga_0_radio_bridge_slot_4_radio_SHDN_pin, DIR = O |
---|
176 | PORT fpga_0_radio_bridge_slot_4_radio_TxEn_pin = fpga_0_radio_bridge_slot_4_radio_TxEn_pin, DIR = O |
---|
177 | PORT fpga_0_radio_bridge_slot_4_radio_RxEn_pin = fpga_0_radio_bridge_slot_4_radio_RxEn_pin, DIR = O |
---|
178 | PORT fpga_0_radio_bridge_slot_4_radio_RxHP_pin = fpga_0_radio_bridge_slot_4_radio_RxHP_pin, DIR = O |
---|
179 | PORT fpga_0_radio_bridge_slot_4_radio_24PA_pin = fpga_0_radio_bridge_slot_4_radio_24PA_pin, DIR = O |
---|
180 | PORT fpga_0_radio_bridge_slot_4_radio_5PA_pin = fpga_0_radio_bridge_slot_4_radio_5PA_pin, DIR = O |
---|
181 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin, DIR = O |
---|
182 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin, DIR = O |
---|
183 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin, DIR = O |
---|
184 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin, DIR = O |
---|
185 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin, DIR = O |
---|
186 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin, DIR = O |
---|
187 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin, DIR = O |
---|
188 | PORT fpga_0_radio_bridge_slot_4_radio_LD_pin = fpga_0_radio_bridge_slot_4_radio_LD_pin, DIR = I |
---|
189 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin, DIR = I |
---|
190 | PORT fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin, DIR = I |
---|
191 | PORT fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin, DIR = I |
---|
192 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin = fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin, DIR = I |
---|
193 | PORT fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin = fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin, DIR = O |
---|
194 | PORT fpga_0_radio_bridge_slot_4_dac_spi_data_pin = fpga_0_radio_bridge_slot_4_dac_spi_data_pin, DIR = O |
---|
195 | PORT fpga_0_radio_bridge_slot_4_dac_spi_cs_pin = fpga_0_radio_bridge_slot_4_dac_spi_cs_pin, DIR = O |
---|
196 | PORT fpga_0_radio_bridge_slot_4_dac_spi_clk_pin = fpga_0_radio_bridge_slot_4_dac_spi_clk_pin, DIR = O |
---|
197 | PORT fpga_0_eeprom_controller_DQ0_pin = fpga_0_eeprom_controller_DQ0_pin, DIR = IO |
---|
198 | PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 40000000 |
---|
199 | PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1 |
---|
200 | PORT debug_status = rxrun & txrun, DIR = O, VEC = [1:0] |
---|
201 | PORT debug_sw_gpio = debug_sw_gpio, DIR = O, VEC = [5:0] |
---|
202 | PORT warplab_buffers_plbw_0_startcapture_pin = net_warplab_buffers_plbw_0_startcapture_pin, DIR = I |
---|
203 | |
---|
204 | |
---|
205 | BEGIN ppc405_virtex4 |
---|
206 | PARAMETER INSTANCE = ppc405_0 |
---|
207 | PARAMETER C_FASTEST_PLB_CLOCK = DPLB0 |
---|
208 | PARAMETER C_IDCR_BASEADDR = 0b0100000000 |
---|
209 | PARAMETER C_IDCR_HIGHADDR = 0b0111111111 |
---|
210 | PARAMETER HW_VER = 2.01.b |
---|
211 | BUS_INTERFACE DPLB0 = plb |
---|
212 | BUS_INTERFACE IPLB0 = plb |
---|
213 | BUS_INTERFACE DSOCM = ppc405_0_docm |
---|
214 | BUS_INTERFACE ISOCM = ppc405_0_iocm |
---|
215 | BUS_INTERFACE JTAGPPC = ppc405_0_jtagppc_bus |
---|
216 | BUS_INTERFACE RESETPPC = ppc_reset_bus |
---|
217 | PORT CPMC405CLOCK = clk_160_0000MHzDCM0 |
---|
218 | END |
---|
219 | |
---|
220 | BEGIN isocm_v10 |
---|
221 | PARAMETER INSTANCE = ppc405_0_iocm |
---|
222 | PARAMETER C_ISCNTLVALUE = 0xa3 |
---|
223 | PARAMETER HW_VER = 2.00.b |
---|
224 | PORT ISOCM_Clk = clk_80_0000MHzDCM0 |
---|
225 | PORT SYS_Rst = sys_bus_reset |
---|
226 | END |
---|
227 | |
---|
228 | BEGIN isbram_if_cntlr |
---|
229 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr |
---|
230 | PARAMETER HW_VER = 3.00.c |
---|
231 | PARAMETER C_BASEADDR = 0xffff0000 |
---|
232 | PARAMETER C_HIGHADDR = 0xffffffff |
---|
233 | BUS_INTERFACE ISOCM = ppc405_0_iocm |
---|
234 | BUS_INTERFACE DCR_WRITE_PORT = ppc405_0_iocm_cntlr_porta |
---|
235 | BUS_INTERFACE INSTRN_READ_PORT = ppc405_0_iocm_cntlr_portb |
---|
236 | END |
---|
237 | |
---|
238 | BEGIN bram_block |
---|
239 | PARAMETER INSTANCE = ppc405_0_iocm_cntlr_bram |
---|
240 | PARAMETER HW_VER = 1.00.a |
---|
241 | BUS_INTERFACE PORTA = ppc405_0_iocm_cntlr_porta |
---|
242 | BUS_INTERFACE PORTB = ppc405_0_iocm_cntlr_portb |
---|
243 | END |
---|
244 | |
---|
245 | BEGIN dsocm_v10 |
---|
246 | PARAMETER INSTANCE = ppc405_0_docm |
---|
247 | PARAMETER C_DSCNTLVALUE = 0xa3 |
---|
248 | PARAMETER HW_VER = 2.00.b |
---|
249 | PORT DSOCM_Clk = clk_80_0000MHzDCM0 |
---|
250 | PORT SYS_Rst = sys_bus_reset |
---|
251 | END |
---|
252 | |
---|
253 | BEGIN dsbram_if_cntlr |
---|
254 | PARAMETER INSTANCE = ppc405_0_docm_cntlr |
---|
255 | PARAMETER HW_VER = 3.00.c |
---|
256 | PARAMETER C_BASEADDR = 0x40110000 |
---|
257 | PARAMETER C_HIGHADDR = 0x4011ffff |
---|
258 | BUS_INTERFACE DSOCM = ppc405_0_docm |
---|
259 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta |
---|
260 | END |
---|
261 | |
---|
262 | BEGIN bram_block |
---|
263 | PARAMETER INSTANCE = ppc405_0_docm_cntlr_bram |
---|
264 | PARAMETER HW_VER = 1.00.a |
---|
265 | BUS_INTERFACE PORTA = ppc405_0_docm_cntlr_porta |
---|
266 | END |
---|
267 | |
---|
268 | BEGIN plb_v46 |
---|
269 | PARAMETER INSTANCE = plb |
---|
270 | PARAMETER C_DCR_INTFCE = 0 |
---|
271 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 |
---|
272 | PARAMETER HW_VER = 1.05.a |
---|
273 | PORT PLB_Clk = clk_80_0000MHzDCM0 |
---|
274 | PORT SYS_Rst = sys_bus_reset |
---|
275 | END |
---|
276 | |
---|
277 | BEGIN xps_bram_if_cntlr |
---|
278 | PARAMETER INSTANCE = xps_bram_if_cntlr_1 |
---|
279 | PARAMETER C_SPLB_NATIVE_DWIDTH = 64 |
---|
280 | PARAMETER HW_VER = 1.00.b |
---|
281 | PARAMETER C_BASEADDR = 0x00000000 |
---|
282 | PARAMETER C_HIGHADDR = 0x0000ffff |
---|
283 | BUS_INTERFACE SPLB = plb |
---|
284 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port |
---|
285 | END |
---|
286 | |
---|
287 | BEGIN bram_block |
---|
288 | PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram |
---|
289 | PARAMETER HW_VER = 1.00.a |
---|
290 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_port |
---|
291 | END |
---|
292 | |
---|
293 | BEGIN warp_v4_userio |
---|
294 | PARAMETER INSTANCE = UserIO |
---|
295 | PARAMETER C_ADDRESS_0 = 0x40 |
---|
296 | PARAMETER C_ADDRESS_1 = 0x42 |
---|
297 | PARAMETER C_I2C_DIVIDER = 0x40 |
---|
298 | PARAMETER HW_VER = 1.00.a |
---|
299 | PARAMETER C_BASEADDR = 0xc9600000 |
---|
300 | PARAMETER C_HIGHADDR = 0xc960ffff |
---|
301 | BUS_INTERFACE SPLB = plb |
---|
302 | PORT LEDs_out = fpga_0_UserIO_LEDs_out_pin |
---|
303 | PORT IOEx_SDA = fpga_0_UserIO_IOEx_SDA_pin |
---|
304 | PORT IOEx_SCL = fpga_0_UserIO_IOEx_SCL_pin |
---|
305 | PORT PB_in = fpga_0_UserIO_PB_in_pin |
---|
306 | PORT DIPSW_in = fpga_0_UserIO_DIPSW_in_pin |
---|
307 | END |
---|
308 | |
---|
309 | BEGIN xps_uartlite |
---|
310 | PARAMETER INSTANCE = rs232_db9 |
---|
311 | PARAMETER C_BAUDRATE = 57600 |
---|
312 | PARAMETER C_DATA_BITS = 8 |
---|
313 | PARAMETER C_USE_PARITY = 0 |
---|
314 | PARAMETER C_ODD_PARITY = 0 |
---|
315 | PARAMETER HW_VER = 1.02.a |
---|
316 | PARAMETER C_BASEADDR = 0x84020000 |
---|
317 | PARAMETER C_HIGHADDR = 0x8402ffff |
---|
318 | BUS_INTERFACE SPLB = plb |
---|
319 | PORT RX = fpga_0_rs232_db9_RX_pin |
---|
320 | PORT TX = fpga_0_rs232_db9_TX_pin |
---|
321 | END |
---|
322 | |
---|
323 | BEGIN xps_uartlite |
---|
324 | PARAMETER INSTANCE = rs232_usb |
---|
325 | PARAMETER C_BAUDRATE = 57600 |
---|
326 | PARAMETER C_DATA_BITS = 8 |
---|
327 | PARAMETER C_USE_PARITY = 0 |
---|
328 | PARAMETER C_ODD_PARITY = 0 |
---|
329 | PARAMETER HW_VER = 1.02.a |
---|
330 | PARAMETER C_BASEADDR = 0x84000000 |
---|
331 | PARAMETER C_HIGHADDR = 0x8400ffff |
---|
332 | BUS_INTERFACE SPLB = plb |
---|
333 | PORT RX = fpga_0_rs232_usb_RX_pin |
---|
334 | PORT TX = fpga_0_rs232_usb_TX_pin |
---|
335 | END |
---|
336 | |
---|
337 | BEGIN xps_ll_temac |
---|
338 | PARAMETER INSTANCE = TriMode_MAC_GMII |
---|
339 | PARAMETER C_NUM_IDELAYCTRL = 2 |
---|
340 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X1Y5-IDELAYCTRL_X1Y6 |
---|
341 | PARAMETER C_PHY_TYPE = 1 |
---|
342 | PARAMETER C_BUS2CORE_CLK_RATIO = 1 |
---|
343 | PARAMETER C_TEMAC_TYPE = 1 |
---|
344 | PARAMETER HW_VER = 2.03.a |
---|
345 | PARAMETER C_BASEADDR = 0x87000000 |
---|
346 | PARAMETER C_HIGHADDR = 0x8707ffff |
---|
347 | BUS_INTERFACE SPLB = plb |
---|
348 | BUS_INTERFACE LLINK0 = TriMode_MAC_GMII_llink0 |
---|
349 | PORT TemacPhy_RST_n = fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin |
---|
350 | PORT GTX_CLK_0 = clk_125_0000MHz |
---|
351 | PORT REFCLK = clk_200_0000MHz |
---|
352 | PORT LlinkTemac0_CLK = clk_80_0000MHzDCM0 |
---|
353 | PORT MII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin |
---|
354 | PORT GMII_TXD_0 = fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin |
---|
355 | PORT GMII_TX_EN_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin |
---|
356 | PORT GMII_TX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin |
---|
357 | PORT GMII_TX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin |
---|
358 | PORT GMII_RXD_0 = fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin |
---|
359 | PORT GMII_RX_DV_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin |
---|
360 | PORT GMII_RX_ER_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin |
---|
361 | PORT GMII_RX_CLK_0 = fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin |
---|
362 | PORT MDC_0 = fpga_0_TriMode_MAC_GMII_MDC_0_pin |
---|
363 | PORT MDIO_0 = fpga_0_TriMode_MAC_GMII_MDIO_0_pin |
---|
364 | END |
---|
365 | |
---|
366 | BEGIN clock_board_config |
---|
367 | PARAMETER INSTANCE = clk_board_config |
---|
368 | PARAMETER HW_VER = 1.05.a |
---|
369 | PARAMETER radio_clk_out4_mode = 0x1eff |
---|
370 | PARAMETER radio_clk_out7_mode = 0x1eff |
---|
371 | PARAMETER logic_clk_out0_mode = 0x08ff |
---|
372 | PARAMETER logic_clk_out1_mode = 0x08ff |
---|
373 | PARAMETER radio_clk_source_sel_mode = 1 |
---|
374 | PARAMETER logic_clk_source_sel_mode = 1 |
---|
375 | PARAMETER fpga_radio_clk_source = 1 |
---|
376 | PARAMETER fpga_logic_clk_source = 1 |
---|
377 | PARAMETER radio_clk_forward_out_mode = 0x08FF |
---|
378 | PARAMETER logic_clk_forward_out_mode = 0x1EFF |
---|
379 | PORT sys_clk = fpga_0_clk_board_config_sys_clk_pin |
---|
380 | PORT sys_rst = net_gnd |
---|
381 | PORT cfg_radio_dat_out = fpga_0_clk_board_config_cfg_radio_dat_out_pin |
---|
382 | PORT cfg_radio_csb_out = fpga_0_clk_board_config_cfg_radio_csb_out_pin |
---|
383 | PORT cfg_radio_en_out = fpga_0_clk_board_config_cfg_radio_en_out_pin |
---|
384 | PORT cfg_radio_clk_out = fpga_0_clk_board_config_cfg_radio_clk_out_pin |
---|
385 | PORT cfg_logic_dat_out = fpga_0_clk_board_config_cfg_logic_dat_out_pin |
---|
386 | PORT cfg_logic_csb_out = fpga_0_clk_board_config_cfg_logic_csb_out_pin |
---|
387 | PORT cfg_logic_en_out = fpga_0_clk_board_config_cfg_logic_en_out_pin |
---|
388 | PORT cfg_logic_clk_out = fpga_0_clk_board_config_cfg_logic_clk_out_pin |
---|
389 | PORT radio_clk_src_sel = radio2_dipsw_zero |
---|
390 | PORT logic_clk_src_sel = radio2_dipsw_one |
---|
391 | PORT config_invalid = clk_board_config_config_invalid |
---|
392 | END |
---|
393 | |
---|
394 | BEGIN util_bus_split |
---|
395 | PARAMETER INSTANCE = util_bus_split_0 |
---|
396 | PARAMETER HW_VER = 1.00.a |
---|
397 | PARAMETER C_SIZE_IN = 4 |
---|
398 | PARAMETER C_SPLIT = 2 |
---|
399 | PORT Sig = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin |
---|
400 | PORT Out1 = radio2_dipsw_zero & radio2_dipsw_one |
---|
401 | END |
---|
402 | |
---|
403 | BEGIN radio_controller |
---|
404 | PARAMETER INSTANCE = radio_controller_0 |
---|
405 | PARAMETER HW_VER = 1.30.a |
---|
406 | PARAMETER C_BASEADDR = 0xcac00000 |
---|
407 | PARAMETER C_HIGHADDR = 0xcac0ffff |
---|
408 | BUS_INTERFACE SPLB = plb_v46_40MHz |
---|
409 | BUS_INTERFACE RC2RB_RAD1 = radio_controller_0_RC2RB_RAD1 |
---|
410 | BUS_INTERFACE RC2RB_RAD2 = radio_controller_0_RC2RB_RAD2 |
---|
411 | BUS_INTERFACE RC2RB_RAD3 = radio_controller_0_RC2RB_RAD3 |
---|
412 | BUS_INTERFACE RC2RB_RAD4 = radio_controller_0_RC2RB_RAD4 |
---|
413 | END |
---|
414 | |
---|
415 | BEGIN radio_bridge |
---|
416 | PARAMETER INSTANCE = radio_bridge_slot_1 |
---|
417 | PARAMETER HW_VER = 1.30.a |
---|
418 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD1 |
---|
419 | PORT converter_clock_in = clk_40_0000MHz |
---|
420 | PORT converter_clock_out = fpga_0_radio_bridge_slot_1_converter_clock_out_pin |
---|
421 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_clk_pin |
---|
422 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_1_radio_DAC_I_pin |
---|
423 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_1_radio_DAC_Q_pin |
---|
424 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_1_radio_ADC_I_pin |
---|
425 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_1_radio_ADC_Q_pin |
---|
426 | PORT radio_B = fpga_0_radio_bridge_slot_1_radio_B_pin |
---|
427 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_1_radio_ANTSW_pin |
---|
428 | PORT radio_LED = fpga_0_radio_bridge_slot_1_radio_LED_pin |
---|
429 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_1_radio_DIPSW_pin |
---|
430 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_D_pin |
---|
431 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_1_radio_EEPROM_IO_pin |
---|
432 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_1_radio_spi_clk_pin |
---|
433 | PORT radio_spi_data = fpga_0_radio_bridge_slot_1_radio_spi_data_pin |
---|
434 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_1_radio_spi_cs_pin |
---|
435 | PORT radio_SHDN = fpga_0_radio_bridge_slot_1_radio_SHDN_pin |
---|
436 | PORT radio_TxEn = fpga_0_radio_bridge_slot_1_radio_TxEn_pin |
---|
437 | PORT radio_RxEn = fpga_0_radio_bridge_slot_1_radio_RxEn_pin |
---|
438 | PORT radio_RxHP = fpga_0_radio_bridge_slot_1_radio_RxHP_pin |
---|
439 | PORT radio_24PA = fpga_0_radio_bridge_slot_1_radio_24PA_pin |
---|
440 | PORT radio_5PA = fpga_0_radio_bridge_slot_1_radio_5PA_pin |
---|
441 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DCS_pin |
---|
442 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_1_radio_RX_ADC_DFS_pin |
---|
443 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNA_pin |
---|
444 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_PWDNB_pin |
---|
445 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_CLAMP_pin |
---|
446 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_HIZ_pin |
---|
447 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_SLEEP_pin |
---|
448 | PORT radio_LD = fpga_0_radio_bridge_slot_1_radio_LD_pin |
---|
449 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin |
---|
450 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin |
---|
451 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_1_radio_RSSI_ADC_OTR_pin |
---|
452 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_1_radio_DAC_PLL_LOCK_pin |
---|
453 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_1_radio_DAC_RESET_pin |
---|
454 | PORT dac_spi_data = fpga_0_radio_bridge_slot_1_dac_spi_data_pin |
---|
455 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_1_dac_spi_cs_pin |
---|
456 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_1_dac_spi_clk_pin |
---|
457 | PORT user_EEPROM_IO_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T |
---|
458 | PORT user_EEPROM_IO_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O |
---|
459 | PORT user_EEPROM_IO_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I |
---|
460 | PORT user_ADC_I = radio_bridge_slot_1_user_ADC_I |
---|
461 | PORT user_ADC_Q = radio_bridge_slot_1_user_ADC_Q |
---|
462 | PORT user_DAC_I = radio_bridge_slot_1_user_DAC_I |
---|
463 | PORT user_DAC_Q = radio_bridge_slot_1_user_DAC_Q |
---|
464 | PORT user_TxModelStart = radio1_txStart |
---|
465 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
466 | PORT user_RSSI_ADC_D = radio_bridge_slot_1_user_RSSI_ADC_D |
---|
467 | PORT user_RxHP_external = agc_rxhp_a |
---|
468 | PORT user_RxBB_gain = agc_g_bb_a |
---|
469 | PORT user_RxRF_gain = agc_g_rf_a |
---|
470 | END |
---|
471 | |
---|
472 | BEGIN radio_bridge |
---|
473 | PARAMETER INSTANCE = radio_bridge_slot_2 |
---|
474 | PARAMETER HW_VER = 1.30.a |
---|
475 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD2 |
---|
476 | PORT converter_clock_in = clk_40_0000MHz |
---|
477 | PORT converter_clock_out = fpga_0_radio_bridge_slot_2_converter_clock_out_pin |
---|
478 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin |
---|
479 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_2_radio_DAC_I_pin |
---|
480 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin |
---|
481 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_2_radio_ADC_I_pin |
---|
482 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin |
---|
483 | PORT radio_B = fpga_0_radio_bridge_slot_2_radio_B_pin |
---|
484 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_2_radio_ANTSW_pin |
---|
485 | PORT radio_LED = fpga_0_radio_bridge_slot_2_radio_LED_pin |
---|
486 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_2_radio_DIPSW_pin |
---|
487 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin |
---|
488 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin |
---|
489 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_2_radio_spi_clk_pin |
---|
490 | PORT radio_spi_data = fpga_0_radio_bridge_slot_2_radio_spi_data_pin |
---|
491 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_2_radio_spi_cs_pin |
---|
492 | PORT radio_SHDN = fpga_0_radio_bridge_slot_2_radio_SHDN_pin |
---|
493 | PORT radio_TxEn = fpga_0_radio_bridge_slot_2_radio_TxEn_pin |
---|
494 | PORT radio_RxEn = fpga_0_radio_bridge_slot_2_radio_RxEn_pin |
---|
495 | PORT radio_RxHP = fpga_0_radio_bridge_slot_2_radio_RxHP_pin |
---|
496 | PORT radio_24PA = fpga_0_radio_bridge_slot_2_radio_24PA_pin |
---|
497 | PORT radio_5PA = fpga_0_radio_bridge_slot_2_radio_5PA_pin |
---|
498 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin |
---|
499 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin |
---|
500 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin |
---|
501 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin |
---|
502 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin |
---|
503 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin |
---|
504 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin |
---|
505 | PORT radio_LD = fpga_0_radio_bridge_slot_2_radio_LD_pin |
---|
506 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin |
---|
507 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin |
---|
508 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin |
---|
509 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin |
---|
510 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin |
---|
511 | PORT dac_spi_data = fpga_0_radio_bridge_slot_2_dac_spi_data_pin |
---|
512 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_2_dac_spi_cs_pin |
---|
513 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_2_dac_spi_clk_pin |
---|
514 | PORT user_EEPROM_IO_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T |
---|
515 | PORT user_EEPROM_IO_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O |
---|
516 | PORT user_EEPROM_IO_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I |
---|
517 | PORT user_ADC_I = radio_bridge_slot_2_user_ADC_I |
---|
518 | PORT user_ADC_Q = radio_bridge_slot_2_user_ADC_Q |
---|
519 | PORT user_DAC_I = radio_bridge_slot_2_user_DAC_I |
---|
520 | PORT user_DAC_Q = radio_bridge_slot_2_user_DAC_Q |
---|
521 | PORT user_TxModelStart = radio2_txStart |
---|
522 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
523 | PORT user_RSSI_ADC_D = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
524 | PORT user_RxHP_external = agc_rxhp_b |
---|
525 | PORT user_RxBB_gain = agc_g_bb_b |
---|
526 | PORT user_RxRF_gain = agc_g_rf_b |
---|
527 | END |
---|
528 | |
---|
529 | BEGIN radio_bridge |
---|
530 | PARAMETER INSTANCE = radio_bridge_slot_3 |
---|
531 | PARAMETER HW_VER = 1.30.a |
---|
532 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD3 |
---|
533 | PORT converter_clock_in = clk_40_0000MHz |
---|
534 | PORT converter_clock_out = fpga_0_radio_bridge_slot_3_converter_clock_out_pin |
---|
535 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin |
---|
536 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_3_radio_DAC_I_pin |
---|
537 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin |
---|
538 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_3_radio_ADC_I_pin |
---|
539 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin |
---|
540 | PORT radio_B = fpga_0_radio_bridge_slot_3_radio_B_pin |
---|
541 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_3_radio_ANTSW_pin |
---|
542 | PORT radio_LED = fpga_0_radio_bridge_slot_3_radio_LED_pin |
---|
543 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_3_radio_DIPSW_pin |
---|
544 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin |
---|
545 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin |
---|
546 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_3_radio_spi_clk_pin |
---|
547 | PORT radio_spi_data = fpga_0_radio_bridge_slot_3_radio_spi_data_pin |
---|
548 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_3_radio_spi_cs_pin |
---|
549 | PORT radio_SHDN = fpga_0_radio_bridge_slot_3_radio_SHDN_pin |
---|
550 | PORT radio_TxEn = fpga_0_radio_bridge_slot_3_radio_TxEn_pin |
---|
551 | PORT radio_RxEn = fpga_0_radio_bridge_slot_3_radio_RxEn_pin |
---|
552 | PORT radio_RxHP = fpga_0_radio_bridge_slot_3_radio_RxHP_pin |
---|
553 | PORT radio_24PA = fpga_0_radio_bridge_slot_3_radio_24PA_pin |
---|
554 | PORT radio_5PA = fpga_0_radio_bridge_slot_3_radio_5PA_pin |
---|
555 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin |
---|
556 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin |
---|
557 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin |
---|
558 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin |
---|
559 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin |
---|
560 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin |
---|
561 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin |
---|
562 | PORT radio_LD = fpga_0_radio_bridge_slot_3_radio_LD_pin |
---|
563 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin |
---|
564 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin |
---|
565 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin |
---|
566 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin |
---|
567 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin |
---|
568 | PORT dac_spi_data = fpga_0_radio_bridge_slot_3_dac_spi_data_pin |
---|
569 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_3_dac_spi_cs_pin |
---|
570 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_3_dac_spi_clk_pin |
---|
571 | PORT user_EEPROM_IO_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T |
---|
572 | PORT user_EEPROM_IO_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O |
---|
573 | PORT user_EEPROM_IO_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I |
---|
574 | PORT user_ADC_I = radio_bridge_slot_3_user_ADC_I |
---|
575 | PORT user_ADC_Q = radio_bridge_slot_3_user_ADC_Q |
---|
576 | PORT user_DAC_I = radio_bridge_slot_3_user_DAC_I |
---|
577 | PORT user_DAC_Q = radio_bridge_slot_3_user_DAC_Q |
---|
578 | PORT user_TxModelStart = radio3_txStart |
---|
579 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
580 | PORT user_RSSI_ADC_D = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
581 | PORT user_RxHP_external = agc_rxhp_c |
---|
582 | PORT user_RxBB_gain = agc_g_bb_c |
---|
583 | PORT user_RxRF_gain = agc_g_rf_c |
---|
584 | END |
---|
585 | |
---|
586 | BEGIN radio_bridge |
---|
587 | PARAMETER INSTANCE = radio_bridge_slot_4 |
---|
588 | PARAMETER HW_VER = 1.30.a |
---|
589 | BUS_INTERFACE RC2RB_RAD = radio_controller_0_RC2RB_RAD4 |
---|
590 | PORT converter_clock_in = clk_40_0000MHz |
---|
591 | PORT converter_clock_out = fpga_0_radio_bridge_slot_4_converter_clock_out_pin |
---|
592 | PORT radio_RSSI_ADC_clk = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_clk_pin |
---|
593 | PORT radio_DAC_I = fpga_0_radio_bridge_slot_4_radio_DAC_I_pin |
---|
594 | PORT radio_DAC_Q = fpga_0_radio_bridge_slot_4_radio_DAC_Q_pin |
---|
595 | PORT radio_ADC_I = fpga_0_radio_bridge_slot_4_radio_ADC_I_pin |
---|
596 | PORT radio_ADC_Q = fpga_0_radio_bridge_slot_4_radio_ADC_Q_pin |
---|
597 | PORT radio_B = fpga_0_radio_bridge_slot_4_radio_B_pin |
---|
598 | PORT radio_ANTSW = fpga_0_radio_bridge_slot_4_radio_ANTSW_pin |
---|
599 | PORT radio_LED = fpga_0_radio_bridge_slot_4_radio_LED_pin |
---|
600 | PORT radio_DIPSW = fpga_0_radio_bridge_slot_4_radio_DIPSW_pin |
---|
601 | PORT radio_RSSI_ADC_D = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_D_pin |
---|
602 | PORT radio_EEPROM_IO = fpga_0_radio_bridge_slot_4_radio_EEPROM_IO_pin |
---|
603 | PORT radio_spi_clk = fpga_0_radio_bridge_slot_4_radio_spi_clk_pin |
---|
604 | PORT radio_spi_data = fpga_0_radio_bridge_slot_4_radio_spi_data_pin |
---|
605 | PORT radio_spi_cs = fpga_0_radio_bridge_slot_4_radio_spi_cs_pin |
---|
606 | PORT radio_SHDN = fpga_0_radio_bridge_slot_4_radio_SHDN_pin |
---|
607 | PORT radio_TxEn = fpga_0_radio_bridge_slot_4_radio_TxEn_pin |
---|
608 | PORT radio_RxEn = fpga_0_radio_bridge_slot_4_radio_RxEn_pin |
---|
609 | PORT radio_RxHP = fpga_0_radio_bridge_slot_4_radio_RxHP_pin |
---|
610 | PORT radio_24PA = fpga_0_radio_bridge_slot_4_radio_24PA_pin |
---|
611 | PORT radio_5PA = fpga_0_radio_bridge_slot_4_radio_5PA_pin |
---|
612 | PORT radio_RX_ADC_DCS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DCS_pin |
---|
613 | PORT radio_RX_ADC_DFS = fpga_0_radio_bridge_slot_4_radio_RX_ADC_DFS_pin |
---|
614 | PORT radio_RX_ADC_PWDNA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNA_pin |
---|
615 | PORT radio_RX_ADC_PWDNB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_PWDNB_pin |
---|
616 | PORT radio_RSSI_ADC_CLAMP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_CLAMP_pin |
---|
617 | PORT radio_RSSI_ADC_HIZ = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_HIZ_pin |
---|
618 | PORT radio_RSSI_ADC_SLEEP = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_SLEEP_pin |
---|
619 | PORT radio_LD = fpga_0_radio_bridge_slot_4_radio_LD_pin |
---|
620 | PORT radio_RX_ADC_OTRA = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin |
---|
621 | PORT radio_RX_ADC_OTRB = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin |
---|
622 | PORT radio_RSSI_ADC_OTR = fpga_0_radio_bridge_slot_4_radio_RSSI_ADC_OTR_pin |
---|
623 | PORT radio_DAC_PLL_LOCK = fpga_0_radio_bridge_slot_4_radio_DAC_PLL_LOCK_pin |
---|
624 | PORT radio_DAC_RESET = fpga_0_radio_bridge_slot_4_radio_DAC_RESET_pin |
---|
625 | PORT dac_spi_data = fpga_0_radio_bridge_slot_4_dac_spi_data_pin |
---|
626 | PORT dac_spi_cs = fpga_0_radio_bridge_slot_4_dac_spi_cs_pin |
---|
627 | PORT dac_spi_clk = fpga_0_radio_bridge_slot_4_dac_spi_clk_pin |
---|
628 | PORT user_EEPROM_IO_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T |
---|
629 | PORT user_EEPROM_IO_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O |
---|
630 | PORT user_EEPROM_IO_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I |
---|
631 | PORT user_ADC_I = radio_bridge_slot_4_user_ADC_I |
---|
632 | PORT user_ADC_Q = radio_bridge_slot_4_user_ADC_Q |
---|
633 | PORT user_DAC_I = radio_bridge_slot_4_user_DAC_I |
---|
634 | PORT user_DAC_Q = radio_bridge_slot_4_user_DAC_Q |
---|
635 | PORT user_TxModelStart = radio4_txStart |
---|
636 | PORT user_RSSI_ADC_clk = rssi_clk_out |
---|
637 | PORT user_RSSI_ADC_D = radio_bridge_slot_4_user_RSSI_ADC_D |
---|
638 | PORT user_RxHP_external = agc_rxhp_d |
---|
639 | PORT user_RxBB_gain = agc_g_bb_d |
---|
640 | PORT user_RxRF_gain = agc_g_rf_d |
---|
641 | END |
---|
642 | |
---|
643 | BEGIN eeprom_onewire |
---|
644 | PARAMETER INSTANCE = eeprom_controller |
---|
645 | PARAMETER HW_VER = 1.10.a |
---|
646 | PARAMETER C_MEM0_BASEADDR = 0xc5400000 |
---|
647 | PARAMETER C_MEM0_HIGHADDR = 0xc540ffff |
---|
648 | BUS_INTERFACE SPLB = plb |
---|
649 | PORT DQ0 = fpga_0_eeprom_controller_DQ0_pin |
---|
650 | PORT DQ1_T = eeprom_controller_DQ1_T_radio_bridge_slot_1_user_EEPROM_IO_T |
---|
651 | PORT DQ1_O = eeprom_controller_DQ1_O_radio_bridge_slot_1_user_EEPROM_IO_O |
---|
652 | PORT DQ1_I = eeprom_controller_DQ1_I_radio_bridge_slot_1_user_EEPROM_IO_I |
---|
653 | PORT DQ2_T = eeprom_controller_DQ2_T_radio_bridge_slot_2_user_EEPROM_IO_T |
---|
654 | PORT DQ2_O = eeprom_controller_DQ2_O_radio_bridge_slot_2_user_EEPROM_IO_O |
---|
655 | PORT DQ2_I = eeprom_controller_DQ2_I_radio_bridge_slot_2_user_EEPROM_IO_I |
---|
656 | PORT DQ3_T = eeprom_controller_DQ3_T_radio_bridge_slot_3_user_EEPROM_IO_T |
---|
657 | PORT DQ3_O = eeprom_controller_DQ3_O_radio_bridge_slot_3_user_EEPROM_IO_O |
---|
658 | PORT DQ3_I = eeprom_controller_DQ3_I_radio_bridge_slot_3_user_EEPROM_IO_I |
---|
659 | PORT DQ4_T = eeprom_controller_DQ4_T_radio_bridge_slot_4_user_EEPROM_IO_T |
---|
660 | PORT DQ4_O = eeprom_controller_DQ4_O_radio_bridge_slot_4_user_EEPROM_IO_O |
---|
661 | PORT DQ4_I = eeprom_controller_DQ4_I_radio_bridge_slot_4_user_EEPROM_IO_I |
---|
662 | PORT DQ5_I = net_vcc |
---|
663 | PORT DQ6_I = net_vcc |
---|
664 | PORT DQ7_I = net_vcc |
---|
665 | END |
---|
666 | |
---|
667 | BEGIN xps_ll_fifo |
---|
668 | PARAMETER INSTANCE = TriMode_MAC_GMII_fifo |
---|
669 | PARAMETER HW_VER = 1.02.a |
---|
670 | PARAMETER C_BASEADDR = 0x81a00000 |
---|
671 | PARAMETER C_HIGHADDR = 0x81a0ffff |
---|
672 | BUS_INTERFACE SPLB = plb |
---|
673 | BUS_INTERFACE LLINK = TriMode_MAC_GMII_llink0 |
---|
674 | END |
---|
675 | |
---|
676 | BEGIN clock_generator |
---|
677 | PARAMETER INSTANCE = clock_generator_0 |
---|
678 | PARAMETER C_CLKIN_FREQ = 40000000 |
---|
679 | PARAMETER C_CLKOUT0_FREQ = 125000000 |
---|
680 | PARAMETER C_CLKOUT0_PHASE = 0 |
---|
681 | PARAMETER C_CLKOUT0_GROUP = NONE |
---|
682 | PARAMETER C_CLKOUT0_BUF = TRUE |
---|
683 | PARAMETER C_CLKOUT1_FREQ = 160000000 |
---|
684 | PARAMETER C_CLKOUT1_PHASE = 0 |
---|
685 | PARAMETER C_CLKOUT1_GROUP = DCM0 |
---|
686 | PARAMETER C_CLKOUT1_BUF = TRUE |
---|
687 | PARAMETER C_CLKOUT2_FREQ = 200000000 |
---|
688 | PARAMETER C_CLKOUT2_PHASE = 0 |
---|
689 | PARAMETER C_CLKOUT2_GROUP = NONE |
---|
690 | PARAMETER C_CLKOUT2_BUF = TRUE |
---|
691 | PARAMETER C_CLKOUT3_FREQ = 40000000 |
---|
692 | PARAMETER C_CLKOUT3_PHASE = 0 |
---|
693 | PARAMETER C_CLKOUT3_GROUP = NONE |
---|
694 | PARAMETER C_CLKOUT3_BUF = TRUE |
---|
695 | PARAMETER C_CLKOUT4_FREQ = 80000000 |
---|
696 | PARAMETER C_CLKOUT4_PHASE = 0 |
---|
697 | PARAMETER C_CLKOUT4_GROUP = DCM0 |
---|
698 | PARAMETER C_CLKOUT4_BUF = TRUE |
---|
699 | PARAMETER C_EXT_RESET_HIGH = 1 |
---|
700 | PARAMETER HW_VER = 4.03.a |
---|
701 | PORT CLKIN = CLK_S |
---|
702 | PORT CLKOUT0 = clk_125_0000MHz |
---|
703 | PORT CLKOUT1 = clk_160_0000MHzDCM0 |
---|
704 | PORT CLKOUT2 = clk_200_0000MHz |
---|
705 | PORT CLKOUT3 = clk_40_0000MHz |
---|
706 | PORT CLKOUT4 = clk_80_0000MHzDCM0 |
---|
707 | PORT RST = clk_board_config_config_invalid |
---|
708 | PORT LOCKED = Dcm_all_locked |
---|
709 | END |
---|
710 | |
---|
711 | BEGIN jtagppc_cntlr |
---|
712 | PARAMETER INSTANCE = jtagppc_cntlr_inst |
---|
713 | PARAMETER HW_VER = 2.01.c |
---|
714 | BUS_INTERFACE JTAGPPC0 = ppc405_0_jtagppc_bus |
---|
715 | END |
---|
716 | |
---|
717 | BEGIN proc_sys_reset |
---|
718 | PARAMETER INSTANCE = proc_sys_reset_0 |
---|
719 | PARAMETER C_EXT_RESET_HIGH = 1 |
---|
720 | PARAMETER HW_VER = 3.00.a |
---|
721 | BUS_INTERFACE RESETPPC0 = ppc_reset_bus |
---|
722 | PORT Slowest_sync_clk = clk_40_0000MHz |
---|
723 | PORT Ext_Reset_In = sys_rst_s |
---|
724 | PORT Dcm_locked = Dcm_all_locked |
---|
725 | PORT Bus_Struct_Reset = sys_bus_reset |
---|
726 | PORT Peripheral_Reset = sys_periph_reset |
---|
727 | END |
---|
728 | |
---|
729 | BEGIN plb_v46 |
---|
730 | PARAMETER INSTANCE = plb_v46_40MHz |
---|
731 | PARAMETER C_DCR_INTFCE = 0 |
---|
732 | PARAMETER C_NUM_CLK_PLB2OPB_REARB = 100 |
---|
733 | PARAMETER HW_VER = 1.05.a |
---|
734 | PORT PLB_Clk = clk_40_0000MHz |
---|
735 | PORT SYS_Rst = sys_bus_reset |
---|
736 | END |
---|
737 | |
---|
738 | BEGIN plbv46_plbv46_bridge |
---|
739 | PARAMETER INSTANCE = plbv46_plbv46_bridge_0 |
---|
740 | PARAMETER HW_VER = 1.04.a |
---|
741 | PARAMETER C_BUS_CLOCK_RATIO = 2 |
---|
742 | PARAMETER C_NUM_ADDR_RNG = 2 |
---|
743 | PARAMETER C_BRIDGE_BASEADDR = 0x86200000 |
---|
744 | PARAMETER C_BRIDGE_HIGHADDR = 0x8620ffff |
---|
745 | PARAMETER C_RNG0_BASEADDR = 0xc6000000 |
---|
746 | PARAMETER C_RNG0_HIGHADDR = 0xc600ffff |
---|
747 | PARAMETER C_RNG1_BASEADDR = 0xcac00000 |
---|
748 | PARAMETER C_RNG1_HIGHADDR = 0xcac0ffff |
---|
749 | BUS_INTERFACE MPLB = plb_v46_40MHz |
---|
750 | BUS_INTERFACE SPLB = plb |
---|
751 | END |
---|
752 | |
---|
753 | BEGIN w2_warplab_buffers_plbw |
---|
754 | PARAMETER INSTANCE = warplab_buffers_plbw_0 |
---|
755 | PARAMETER HW_VER = 1.00.a |
---|
756 | PARAMETER C_BASEADDR = 0x83800000 |
---|
757 | PARAMETER C_HIGHADDR = 0x83bfffff |
---|
758 | BUS_INTERFACE SPLB = plb |
---|
759 | PORT sysgen_clk = clk_40_0000MHz |
---|
760 | PORT radio2_adc_i = radio_bridge_slot_2_user_ADC_I |
---|
761 | PORT radio2_adc_q = radio_bridge_slot_2_user_ADC_Q |
---|
762 | PORT radio2_adc_i_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin |
---|
763 | PORT radio2_adc_q_otr = fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin |
---|
764 | PORT startcapture = net_warplab_buffers_plbw_0_startcapture_pin |
---|
765 | PORT StartTx = net_gnd |
---|
766 | PORT StopTx = net_gnd |
---|
767 | PORT radio2_dac_i = radio_bridge_slot_2_user_DAC_I |
---|
768 | PORT radio2_dac_q = radio_bridge_slot_2_user_DAC_Q |
---|
769 | PORT rssi_adc_clk = rssi_clk_out |
---|
770 | PORT debug_capturing = rxrun |
---|
771 | PORT debug_transmitting = txrun |
---|
772 | PORT debug_agc_done = agcsetdone |
---|
773 | PORT radio3_adc_i = radio_bridge_slot_3_user_ADC_I |
---|
774 | PORT radio3_adc_i_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin |
---|
775 | PORT radio3_adc_q = radio_bridge_slot_3_user_ADC_Q |
---|
776 | PORT radio3_adc_q_otr = fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin |
---|
777 | PORT radio3_dac_i = radio_bridge_slot_3_user_DAC_I |
---|
778 | PORT radio3_dac_q = radio_bridge_slot_3_user_DAC_Q |
---|
779 | PORT radio4_dac_q = radio_bridge_slot_4_user_DAC_Q |
---|
780 | PORT radio4_dac_i = radio_bridge_slot_4_user_DAC_I |
---|
781 | PORT radio1_dac_q = radio_bridge_slot_1_user_DAC_Q |
---|
782 | PORT radio1_dac_i = radio_bridge_slot_1_user_DAC_I |
---|
783 | PORT radio4_adc_q_otr = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRB_pin |
---|
784 | PORT radio4_adc_q = radio_bridge_slot_4_user_ADC_Q |
---|
785 | PORT radio4_adc_i_otr = fpga_0_radio_bridge_slot_4_radio_RX_ADC_OTRA_pin |
---|
786 | PORT radio4_adc_i = radio_bridge_slot_4_user_ADC_I |
---|
787 | PORT radio1_adc_q_otr = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRB_pin |
---|
788 | PORT radio1_adc_q = radio_bridge_slot_1_user_ADC_Q |
---|
789 | PORT radio1_adc_i_otr = fpga_0_radio_bridge_slot_1_radio_RX_ADC_OTRA_pin |
---|
790 | PORT radio1_adc_i = radio_bridge_slot_1_user_ADC_I |
---|
791 | PORT radio1_rssi = radio_bridge_slot_1_user_RSSI_ADC_D |
---|
792 | PORT radio2_rssi = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
793 | PORT radio3_rssi = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
794 | PORT radio4_rssi = radio_bridge_slot_4_user_RSSI_ADC_D |
---|
795 | PORT agc_done = agc_is_done |
---|
796 | PORT fromagc_radio1_i = dc_filtered_i_a |
---|
797 | PORT fromagc_radio1_q = dc_filtered_q_a |
---|
798 | PORT fromagc_radio2_i = dc_filtered_i_b |
---|
799 | PORT fromagc_radio2_q = dc_filtered_q_b |
---|
800 | PORT fromagc_radio3_i = dc_filtered_i_c |
---|
801 | PORT fromagc_radio3_q = dc_filtered_q_c |
---|
802 | PORT fromagc_radio4_i = dc_filtered_i_d |
---|
803 | PORT fromagc_radio4_q = dc_filtered_q_d |
---|
804 | END |
---|
805 | |
---|
806 | BEGIN w2_warplab_agc_plbw |
---|
807 | PARAMETER INSTANCE = warplab_agc_plbw_0 |
---|
808 | PARAMETER HW_VER = 1.00.a |
---|
809 | PARAMETER C_BASEADDR = 0xc6000000 |
---|
810 | PARAMETER C_HIGHADDR = 0xc600ffff |
---|
811 | BUS_INTERFACE SPLB = plb_v46_40MHz |
---|
812 | PORT sysgen_clk = clk_40_0000MHz |
---|
813 | PORT rxhp_d = agc_rxhp_d |
---|
814 | PORT rxhp_c = agc_rxhp_c |
---|
815 | PORT rxhp_b = agc_rxhp_b |
---|
816 | PORT rxhp_a = agc_rxhp_a |
---|
817 | PORT g_rf_d = agc_g_rf_d |
---|
818 | PORT g_rf_c = agc_g_rf_c |
---|
819 | PORT g_rf_b = agc_g_rf_b |
---|
820 | PORT g_rf_a = agc_g_rf_a |
---|
821 | PORT g_bb_d = agc_g_bb_d |
---|
822 | PORT g_bb_c = agc_g_bb_c |
---|
823 | PORT g_bb_b = agc_g_bb_b |
---|
824 | PORT g_bb_a = agc_g_bb_a |
---|
825 | PORT agc_done = agc_is_done |
---|
826 | PORT rssi_in_d = radio_bridge_slot_4_user_RSSI_ADC_D |
---|
827 | PORT rssi_in_c = radio_bridge_slot_3_user_RSSI_ADC_D |
---|
828 | PORT rssi_in_b = radio_bridge_slot_2_user_RSSI_ADC_D |
---|
829 | PORT rssi_in_a = radio_bridge_slot_1_user_RSSI_ADC_D |
---|
830 | PORT reset_in = net_gnd |
---|
831 | PORT q_in_d = radio_bridge_slot_4_user_ADC_Q |
---|
832 | PORT q_in_c = radio_bridge_slot_3_user_ADC_Q |
---|
833 | PORT q_in_b = radio_bridge_slot_2_user_ADC_Q |
---|
834 | PORT q_in_a = radio_bridge_slot_1_user_ADC_Q |
---|
835 | PORT packet_in = net_gnd |
---|
836 | PORT mreset_in = net_gnd |
---|
837 | PORT i_in_d = radio_bridge_slot_4_user_ADC_I |
---|
838 | PORT i_in_c = radio_bridge_slot_3_user_ADC_I |
---|
839 | PORT i_in_b = radio_bridge_slot_2_user_ADC_I |
---|
840 | PORT i_in_a = radio_bridge_slot_1_user_ADC_I |
---|
841 | PORT i_out_a = dc_filtered_i_a |
---|
842 | PORT i_out_b = dc_filtered_i_b |
---|
843 | PORT i_out_c = dc_filtered_i_c |
---|
844 | PORT i_out_d = dc_filtered_i_d |
---|
845 | PORT q_out_a = dc_filtered_q_a |
---|
846 | PORT q_out_b = dc_filtered_q_b |
---|
847 | PORT q_out_c = dc_filtered_q_c |
---|
848 | PORT q_out_d = dc_filtered_q_d |
---|
849 | END |
---|
850 | |
---|
851 | BEGIN xps_central_dma |
---|
852 | PARAMETER INSTANCE = xps_central_dma_0 |
---|
853 | PARAMETER HW_VER = 2.03.a |
---|
854 | PARAMETER C_BASEADDR = 0x80200000 |
---|
855 | PARAMETER C_HIGHADDR = 0x8020ffff |
---|
856 | BUS_INTERFACE MPLB = plb |
---|
857 | BUS_INTERFACE SPLB = plb |
---|
858 | END |
---|
859 | |
---|
860 | BEGIN xps_timer |
---|
861 | PARAMETER INSTANCE = xps_timer_0 |
---|
862 | PARAMETER HW_VER = 1.02.a |
---|
863 | PARAMETER C_BASEADDR = 0x83c00000 |
---|
864 | PARAMETER C_HIGHADDR = 0x83c0ffff |
---|
865 | BUS_INTERFACE SPLB = plb |
---|
866 | END |
---|
867 | |
---|
868 | BEGIN xps_gpio |
---|
869 | PARAMETER INSTANCE = xps_gpio_0 |
---|
870 | PARAMETER HW_VER = 2.00.a |
---|
871 | PARAMETER C_GPIO_WIDTH = 6 |
---|
872 | PARAMETER C_BASEADDR = 0x81400000 |
---|
873 | PARAMETER C_HIGHADDR = 0x8140ffff |
---|
874 | BUS_INTERFACE SPLB = plb |
---|
875 | PORT GPIO_IO_O = debug_sw_gpio |
---|
876 | END |
---|
877 | |
---|