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warplab.c

Last change on this file was 1879, checked in by murphpo, 12 years ago

File size: 53.7 KB

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1	////////////////////////////////////////////////////////////////////////////////
2	//
3	// File : warplab.c v6.4
4	// Date : 2013, Jan 3
5	// Author : P. Murphy, S. Gupta, M. Duarte, C. Hunter
6	//
7	// Changelog:
8	// v6.4
9	// - Added 4-radio support for WARP v3
10	// v6.3b
11	// - Fixed RFA/RFB typo in HPF command
12	// v6.3
13	// - No changes to C-code other than the print that says what version it is
14	// - Small bugfixes to UCF for WARP v2 and WARP v3
15	//
16	////////////////////////////////////////////////////////////////////////////////
17
18	#include "xparameters.h"
19	#include <xilnet_config.h>
20	#include <xilnet_xilsock.h>
21	#include <xilnet_mac.h>
22	#include "xstatus.h"
23	#include <stdlib.h>
24	#include <string.h>
25	#include "math.h"
26	#include "radio_controller.h"
27	#include "warplab_defines.h"
28	#include "warplab_regmacros.h"
29	#include "stdio.h"
30	#include "xtmrctr.h"
31	#include "w3_userio.h"
32	#include "w3_ad_controller.h"
33	#include "w3_clock_controller.h"
34	#include "w3_iic_eeprom.h"
35	#include "Xio.h"
36	#include "xlltemac.h"
37	#include "xllfifo.h"
38	#include "xdmacentral.h"
39	#include "xdmacentral_l.h"
40	#include "warp_hw_ver.h"
41
42	#define WARPLAB_MAJOR_VER 6
43	#define WARPLAB_MINOR_VER 4
44
45	#define RC_BASEADDR XPAR_RADIO_CONTROLLER_0_BASEADDR
46	#define AD_BASEADDR XPAR_W3_AD_CONTROLLER_0_BASEADDR
47	#define CLK_BASEADDR XPAR_W3_CLOCK_CONTROLLER_0_BASEADDR
48	#define EEPROM_BASEADDR XPAR_W3_IIC_EEPROM_ONBOARD_BASEADDR
49	#define EEPROM_FMC_BASEADDR XPAR_W3_IIC_EEPROM_FMC_BASEADDR
50	#define USERIO_BASEADDR XPAR_W3_USERIO_0_BASEADDR
51	#define TIMER_FREQ XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ
52	#define WARPLAB_TXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO1
53	#define WARPLAB_TXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO2
54	#define WARPLAB_TXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO3
55	#define WARPLAB_TXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_TXBUFF_RADIO4
56	#define WARPLAB_RXBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO1
57	#define WARPLAB_RXBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO2
58	#define WARPLAB_RXBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO3
59	#define WARPLAB_RXBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RXBUFF_RADIO4
60	#define WARPLAB_RSSIBUFF_RADIO1 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO1
61	#define WARPLAB_RSSIBUFF_RADIO2 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO2
62	#define WARPLAB_RSSIBUFF_RADIO3 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO3
63	#define WARPLAB_RSSIBUFF_RADIO4 XPAR_WARPLAB_BUFFERS_PLBW_0_MEMMAP_RSSIBUFF_RADIO4
64	#define TEMAC_DEVICE_ID XPAR_LLTEMAC_0_DEVICE_ID
65	#define FIFO_DEVICE_ID XPAR_LLFIFO_0_DEVICE_ID
66	#define TMRCTR_DEVICE_ID XPAR_TMRCTR_0_DEVICE_ID
67	#define TIMER_COUNTER_0 0
68
69
70	//#define WARPLAB_CONFIG_2RF 1 // Comment in if board in 2x2 configuration
71	#define WARPLAB_CONFIG_4RF 1 // Comment in if board in 4x4 configuration
72	// Currently not applicable to WARP v3
73
74
75	#ifdef WARPLAB_CONFIG_4RF
76	#define ALL_RF_SEL (RC_RFA \| RC_RFB \| RC_RFC \| RC_RFD)
77	#define ALL_AD_SEL (RFA_AD_CS \| RFB_AD_CS \| RFC_AD_CS \| RFD_AD_CS)
78	#else
79	#define ALL_RF_SEL (RC_RFA \| RC_RFB)
80	#define ALL_AD_SEL (RFA_AD_CS \| RFB_AD_CS)
81	#endif
82
83	static XDmaCentral DmaCentralInst;
84	static XDmaCentral_Config *DMAConfigPtr;
85	XLlTemac TemacInstance;
86	XLlTemac_Config *MacCfgPtr;
87	XLlFifo FifoInstance;
88	XTmrCtr TimerCounter; /* The instance of the Tmrctr Device */
89
90	u8 numSync;
91	u8 hw_generation;
92	u8 numRadios;
93
94	#define ENET_LINK_SPEED 1000
95	#define BUFSIZE 2000
96	#define DEBUG_LVL 0
97
98
99	#define WAITDURATION_SEC 2
100
101	unsigned int sendPtr32[(BUFSIZE+3)/4];
102	unsigned char * const sendBuffer = (unsigned char *) sendPtr32;
103	unsigned int receivePtr32[(BUFSIZE+3)/4];
104	unsigned char * const receiveBuffer = (unsigned char *) receivePtr32;
105	unsigned int myPort;
106
107	int sock; // UDP socket
108	struct sockaddr_in addr;
109	unsigned int alen = 0;
110	char node;
111
112	unsigned int ReadWrite;
113	unsigned char Radios_WirelessChan;
114	unsigned char Radios_Tx_LPF_Corn_Freq;
115	unsigned char Radios_Rx_LPF_Corn_Freq;
116	unsigned char Radio1_TxGain_BB, Radio1_TxGain_RF, Radio1_RxGain_BB, Radio1_RxGain_RF;
117	unsigned char Radio2_TxGain_BB, Radio2_TxGain_RF, Radio2_RxGain_BB, Radio2_RxGain_RF;
118	unsigned char Radio3_TxGain_BB, Radio3_TxGain_RF, Radio3_RxGain_BB, Radio3_RxGain_RF;
119	unsigned char Radio4_TxGain_BB, Radio4_TxGain_RF, Radio4_RxGain_BB, Radio4_RxGain_RF;
120
121	unsigned int AgcIsDoneAddr;
122	unsigned int MGC_AGC_Sel_Variable = 0; // By default MGC is selected
123
124	//----------------------------------
125	// Functions
126	void sendACK(unsigned int packetNo, unsigned int commandToACK);
127	unsigned char sevenSegmentMap(unsigned char x);
128	int warpphy_applyTxDCOCorrection(unsigned int radioSelection);
129	void warplab_AGC_Reset();
130	void warplab_AGC_MasterReset();
131	void warplab_AGC_Start();
132	void warplab_AGC_Initialize(int noise_estimate);
133	void warplab_AGC_setNoiseEstimate(int noise_estimate);
134	unsigned int warplab_AGC_GetGains(void);
135	void warplab_AGC_SetTarget(unsigned int target);
136	void warplab_AGC_SetDCO(unsigned int AGCstate);
137	int warpphy_applyTxDCOCalibration(unsigned int radioSelection);
138	// In WARPLab there is no decimation filter in the AGC, there is a downsampling only, so in WARPLab a function equivalent to
139	// ofdm_AGC_FiltSel is not needed
140
141	int w3_node_init() {
142
143	int status;
144	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
145	int ret = XST_SUCCESS;
146
147	microblaze_enable_exceptions();
148
149	//Initialize the AD9512 clock buffers (RF reference and sampling clocks)
150	status = clk_init(CLK_BASEADDR, 2);
151	if(status != XST_SUCCESS) {
152	xil_printf("w3_node_init: Error in clk_init (%d)\n", status);
153	ret = XST_FAILURE;
154	}
155
156	//Set divider to 2 (for 40MHz clock) to RF A/B AD9963's
157	clk_config_dividers(CLK_BASEADDR, 2, (CLK_SAMP_OUTSEL_AD_RFB \| CLK_SAMP_OUTSEL_AD_RFA));
158
159	#if WARPLAB_CONFIG_4RF
160	//Turn on clocks to FMC
161	clk_config_outputs(CLK_BASEADDR, CLK_OUTPUT_ON, (CLK_SAMP_OUTSEL_FMC \| CLK_RFREF_OUTSEL_FMC));
162
163	//FMC samp clock divider = 2 (40MHz sampling reference, same as on-board AD9963 ref clk)
164	clk_config_dividers(CLK_BASEADDR, 2, CLK_SAMP_OUTSEL_FMC);
165
166	//FMC RF ref clock divider = 2 (40MHz RF reference, same as on-board MAX2829 ref clk)
167	clk_config_dividers(CLK_BASEADDR, 2, CLK_RFREF_OUTSEL_FMC);
168	#endif
169
170	//Initialize the AD9963 ADCs/DACs
171	status = ad_init(AD_BASEADDR, ALL_AD_SEL, 2);
172	if(status != XST_SUCCESS) {
173	xil_printf("w3_node_init: Error in ad_init (%d)\n", status);
174	ret = XST_FAILURE;
175	}
176
177	//Initialize the radio_controller core and MAX2829 transceivers
178	status = radio_controller_init(RC_BASEADDR, (ALL_RF_SEL), 1, 1);
179	if(status != XST_SUCCESS) {
180	xil_printf("w3_node_init: Error in radio_controller_initialize (%d)\n", status);
181	ret = XST_FAILURE;
182	}
183
184	//Initialize the EEPROM read/write core
185	iic_eeprom_init(EEPROM_BASEADDR, 0x64);
186	if(status != XST_SUCCESS) {
187	xil_printf("w3_node_init: Error in IIC_EEPROM_init (%d)\n", status);
188	ret = XST_FAILURE;
189	}
190
191	/*
192	* Initialize the timer counter so that it's ready to use,
193	* specify the device ID that is generated in xparameters.h
194	*/
195	status = XTmrCtr_Initialize(TmrCtrInstancePtr, TMRCTR_DEVICE_ID);
196	if (status != XST_SUCCESS) {
197	xil_printf("w3_node_init: Error in XtmrCtr_Initialize (%d)\n", status);
198	ret = XST_FAILURE;
199	}
200
201	/*
202	* Perform a self-test to ensure that the hardware was built
203	* correctly, use the 1st timer in the device (0)
204	*/
205	status = XTmrCtr_SelfTest(TmrCtrInstancePtr, 0);
206	if (status != XST_SUCCESS) {
207	ret = XST_FAILURE;
208	}
209
210	// Set timer 0 to into a "count down" mode
211	XTmrCtr_SetOptions(TmrCtrInstancePtr, 0, (XTC_DOWN_COUNT_OPTION));
212
213	///// Project-Specific Initializations /////
214	node = userio_read_inputs(USERIO_BASEADDR)&W3_USERIO_DIPSW;
215	userio_write_hexdisp_left(USERIO_BASEADDR, (node+1)%10);
216
217	radio_controller_setTxGainSource(RC_BASEADDR, (ALL_RF_SEL), RC_GAINSRC_SPI);
218	radio_controller_setRxGainSource(RC_BASEADDR, (ALL_RF_SEL), RC_GAINSRC_SPI);
219
220	radio_controller_apply_TxDCO_calibration(AD_BASEADDR, EEPROM_BASEADDR, (ALL_RF_SEL));
221
222	//Set Tx bandwidth to nominal mode
223	Radios_Tx_LPF_Corn_Freq = 1;
224	radio_controller_setRadioParam(RC_BASEADDR, (ALL_RF_SEL), RC_PARAMID_TXLPF_BW, Radios_Tx_LPF_Corn_Freq);
225
226	//Set Rx bandwidth to nominal mode
227	Radios_Rx_LPF_Corn_Freq = 1;
228	radio_controller_setRadioParam(RC_BASEADDR, (ALL_RF_SEL), RC_PARAMID_RXLPF_BW, Radios_Rx_LPF_Corn_Freq);
229
230	//Set Radios to use 30KHz cutoff on HPF
231	radio_controller_setRadioParam(RC_BASEADDR, (ALL_RF_SEL), RC_PARAMID_RXHPF_HIGH_CUTOFF_EN, 1);
232
233	radio_controller_setRadioParam(RC_BASEADDR, (ALL_RF_SEL), RC_PARAMID_TXLINEARITY_VGA, 2);
234
235
236
237	///Timer Setup///
238	XTmrCtr_SetResetValue(TmrCtrInstancePtr,1,0); //Sets it so issuing a "start" command begins at counter=0
239	/////////////////
240
241	radio_controller_TxRxDisable(RC_BASEADDR, (ALL_RF_SEL));
242
243
244	#ifdef WARP_HW_VER_v3
245	hw_generation = 3;
246	#elif defined WARP_HW_VER_v2
247	hw_generation = 2;
248	#elif defined WARP_HW_VER_v1
249	hw_generation = 1;
250	#endif
251
252	#ifdef WARPLAB_CONFIG_2RF
253	numRadios = 2;
254	#elif defined WARPLAB_CONFIG_4RF
255	numRadios = 4;
256	#endif
257
258
259
260	return ret;
261	}
262
263	void usleep(u32 duration){
264	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
265	XTmrCtr_SetResetValue(TmrCtrInstancePtr,0,duration*(TIMER_FREQ/1000000));
266
267	XTmrCtr_Start(TmrCtrInstancePtr,0);
268
269	volatile u8 isExpired = 0;
270	while(isExpired!=1){
271	isExpired = XTmrCtr_IsExpired(TmrCtrInstancePtr,0);
272	}
273	XTmrCtr_Reset(TmrCtrInstancePtr,0);
274	return;
275	}
276
277
278	void init_net() {
279	int Status;
280	xil_printf("Configuring network\n");
281
282	mb_hw_addr[0] = 0x00;
283	mb_hw_addr[1] = 0x50;
284	mb_hw_addr[2] = 0xc2;
285	mb_hw_addr[3] = 0x63;
286	mb_hw_addr[4] = 0x36;
287	mb_hw_addr[5] = node+0x63;
288
289	mb_ip_addr[0] = 10;
290	mb_ip_addr[1] = 0;
291	mb_ip_addr[2] = 0;
292	mb_ip_addr[3] = node+1;
293
294	//Define the last octet of the IP address used for SYNC packets. The first three will be the mb_ip_addr.
295	sync_IP_octet = 255;
296
297	myPort = 9000 + node;
298
299	xilnet_eth_init_hw_addr_tbl();
300
301	if(DEBUG_LVL > 1) xil_printf("... initializing DMA\n");
302	/************************DMA*****************************/
303	//Lookup the DMA configuration information
304	DMAConfigPtr = XDmaCentral_LookupConfig(XPAR_XPS_CENTRAL_DMA_0_DEVICE_ID);
305
306	//Initialize the config struct
307	Status = XDmaCentral_CfgInitialize(&DmaCentralInst, DMAConfigPtr, DMAConfigPtr->BaseAddress);
308	if (Status != XST_SUCCESS){
309	xil_printf("... ... DMA CfgInitialize failed!\n");
310	return;
311	}
312
313	//Disable Interrupts
314	XDmaCentral_InterruptEnableSet(&DmaCentralInst, 0);
315	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
316	/************************************************************/
317
318	/*****************Ethernet********************************/
319	if(DEBUG_LVL > 1) xil_printf("... initializing Ethernet\n");
320	MacCfgPtr = XLlTemac_LookupConfig(TEMAC_DEVICE_ID);
321	Status = XLlTemac_CfgInitialize(&TemacInstance, MacCfgPtr, MacCfgPtr->BaseAddress);
322	XLlFifo_Initialize(&FifoInstance, XLlTemac_LlDevBaseAddress(&TemacInstance));
323	if (Status != XST_SUCCESS)
324	xil_printf("... ... EMAC init error\n");
325
326	if (!XLlTemac_IsFifo(&TemacInstance))
327	xil_printf("... ... EMAC hw config incorrect\n");
328
329
330
331	Status = XLlTemac_ClearOptions(&TemacInstance, XTE_LENTYPE_ERR_OPTION \| XTE_FLOW_CONTROL_OPTION \| XTE_FCS_STRIP_OPTION);// \| XTE_MULTICAST_OPTION);
332	Status \|= XLlTemac_SetOptions(&TemacInstance, XTE_PROMISC_OPTION \| XTE_MULTICAST_OPTION \| XTE_BROADCAST_OPTION \| XTE_RECEIVER_ENABLE_OPTION \| XTE_TRANSMITTER_ENABLE_OPTION); //\| XTE_JUMBO_OPTION
333	if (Status != XST_SUCCESS)
334	xil_printf("... ... Error setting EMAC options\n, code %d", Status);
335
336	// Make sure the TEMAC is ready
337	Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET);
338	while ((Status & XTE_RDY_HARD_ACS_RDY_MASK) == 0)
339	{
340	Status = XLlTemac_ReadReg(TemacInstance.Config.BaseAddress, XTE_RDY_OFFSET);
341	}
342
343	XLlTemac_SetOperatingSpeed(&TemacInstance, ENET_LINK_SPEED);
344	usleep(1 * 10000);
345
346	XLlTemac_Start(&TemacInstance);
347	if(DEBUG_LVL > 1) xil_printf("... ... complete!\n");
348	/************************************************************/
349
350	// Initialize the MAC OPB base address (MAC driver in net/mac.c)
351	xilnet_mac_init((void )&FifoInstance,(void )&DmaCentralInst);
352
353
354	if(DEBUG_LVL > 1) xil_printf("... complete!\n");
355	// Print IP address
356	if(DEBUG_LVL > 0) xil_printf("IP Address: %d.%d.%d.%d \n", mb_ip_addr[0], mb_ip_addr[1],mb_ip_addr[2],mb_ip_addr[3]);
357	}
358
359
360	void init_socket() {
361
362	sock = xilsock_socket(AF_INET, SOCK_DGRAM, 0); // Create UDP socket with domain Internet and UDP connection.
363	if (sock == -1) {
364	if(DEBUG_LVL > 0) xil_printf("Error in creating socket\n");
365	exit(-1);
366	}
367
368	addr.sin_family = AF_INET;
369	addr.sin_port = myPort;
370	addr.sin_addr.s_addr = INADDR_ANY; // Create the input socket with any incoming address. (0x00000000)
371
372	XStatus bind = xilsock_bind(sock, (struct sockaddr *)&addr, sizeof(struct sockaddr));
373	if (bind == -1) {
374	if(DEBUG_LVL > 0) xil_printf("Unable to bind socket\n");
375	exit(-1);
376	}
377	alen = sizeof(struct sockaddr);
378	if(DEBUG_LVL > 0) xil_printf("Listening on UDP port %d.\n", myPort);
379	}
380
381	void shut_socket() {
382	xilsock_close(sock);
383	}
384
385	int waitForSync()
386	{
387	unsigned int n;
388	XTmrCtr *TmrCtrInstancePtr = &TimerCounter;
389	XTmrCtr_Start(TmrCtrInstancePtr, 1);
390
391	while(XTmrCtr_GetValue(TmrCtrInstancePtr, 1) < (WAITDURATION_SEC*XPAR_XPS_TIMER_0_CLOCK_FREQ_HZ)){
392	n = xilnet_eth_recv_frame(receiveBuffer, BUFSIZE);
393	if(n==9999)
394	{
395	//xil_printf("Got Sync\n");
396	numSync++;
397	return 0;
398	}
399	}
400
401	XTmrCtr_Stop(TmrCtrInstancePtr, 1);
402
403	int numblinks;
404	for(numblinks=0;numblinks<10;numblinks++){
405	userio_write_leds_red(USERIO_BASEADDR,0xF);
406	usleep(100000);
407	userio_write_leds_red(USERIO_BASEADDR,0x0);
408	usleep(100000);
409	userio_write_leds_red(USERIO_BASEADDR,0xF);
410	}
411	userio_write_leds_red(USERIO_BASEADDR,0x0);
412	userio_write_leds_green(USERIO_BASEADDR,0x0);
413
414	xil_printf("NoSync\n");
415	return 1;
416	}
417
418	int main() {
419
420	int bytesReceived;
421	int bytesSend;
422	int command;
423	int packetNo;
424	int status;
425	unsigned int rxArg0;
426	char done = 0;
427	unsigned char sevenSeg1 = 0x1;
428	int agctarget = -14;
429	int agcnoiseEst = -95;
430	unsigned int agc_dco_state;
431
432	status = w3_node_init();
433	if(status != 0) {
434	xil_printf("Error in w3_node_init()! Exiting\n");
435	return -1;
436	}
437
438	//Initialize the xilnet stack & default sockets
439	init_net();
440	init_socket();
441
442	#ifdef WARPLAB_CONFIG_2RF
443	xil_printf("WARPLab 2x2");
444	#elif defined WARPLAB_CONFIG_4RF
445	xil_printf("WARPLab 4x4");
446	#endif
447	xil_printf(" v%d.%d (compiled %s %s)\r\n", WARPLAB_MAJOR_VER, WARPLAB_MINOR_VER, __DATE__, __TIME__);
448	xil_printf("Waiting for commands from MATLAB\r\n");
449
450	userio_write_leds_red(USERIO_BASEADDR,0x5);
451	int numblinks;
452	for(numblinks=0;numblinks<10;numblinks++){
453	userio_toggle_leds_red(USERIO_BASEADDR,0xF);
454	usleep(100000);
455	}
456	userio_write_leds_red(USERIO_BASEADDR,0x0);
457	userio_write_leds_green(USERIO_BASEADDR,0x0);
458
459	XLlFifo_Reset(&FifoInstance);
460
461
462
463	while(done == 0) {
464
465	if(DEBUG_LVL > 3) xil_printf("\|");
466
467	bytesReceived = xilsock_recvfrom(sock, receiveBuffer, BUFSIZE, (struct sockaddr *)&addr, &alen); // Wait to receive data
468
469	if (bytesReceived > 0) { // Check for valid packet
470
471	packetNo = receivePtr32[0];
472	command = receivePtr32[1];
473	rxArg0 = receivePtr32[2];
474
475	//Rotate the single active bit
476	sevenSeg1 = ( ((sevenSeg1<<1)&0x7E) \| ((sevenSeg1>>5)&0x7E) );
477
478	userio_write_hexdisp_right(USERIO_BASEADDR, sevenSeg1<<1);
479
480	if(DEBUG_LVL > 2) xil_printf("=============\nPacket Received\n Length: %d\n Packet No.: %d\n Command No: %d\n", bytesReceived, packetNo, command);
481
482	switch(command) { // Decode on incoming command
483
484	case INITIALIZE:
485	//if(DEBUG_LVL > 1) xil_printf("Initializing Node...");
486	warplab_buffers_WriteReg_TxDelay(0);
487	warplab_buffers_WriteReg_StartCapture(0);
488	warplab_buffers_WriteReg_TxLength((unsigned int)16383);
489	warplab_buffers_WriteReg_TransMode(0);
490	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0);
491	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0);
492	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0);
493	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0);
494	warplab_AGC_WriteReg_RADIO1_AGC_EN(0); // No radio on slot 1
495	warplab_AGC_WriteReg_RADIO2_AGC_EN(0);
496	warplab_AGC_WriteReg_RADIO3_AGC_EN(0);
497	warplab_AGC_WriteReg_RADIO4_AGC_EN(0); // No radio on slot 4
498	warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)50);
499	warplab_buffers_WriteReg_MGC_AGC_SEL(0);// Select MGC by default
500	warplab_AGC_WriteReg_AGC_EN(0);
501	MGC_AGC_Sel_Variable = 0;
502	#ifdef WARPLAB_CONFIG_4RF
503	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0);
504	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0);
505	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0);
506	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0);
507	#endif
508	sendACK(packetNo, command);
509	break;
510
511	case NETWORKCHECK:
512	sendPtr32[0] = packetNo + 1;
513	sendPtr32[1] = ACK;
514	sendPtr32[2] = command;
515	sendPtr32[3] = numSync;
516	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
517	numSync = 0;
518	waitForSync();
519	break;
520
521	case BOARDINFO:
522	sendPtr32[0] = packetNo + 1;
523	sendPtr32[1] = ACK;
524	sendPtr32[2] = command;
525	sendPtr32[3] = w3_eeprom_readSerialNum(EEPROM_BASEADDR);
526	sendPtr32[4] = userio_read_fpga_dna_msb(USERIO_BASEADDR);
527	sendPtr32[5] = userio_read_fpga_dna_lsb(USERIO_BASEADDR);
528	sendPtr32[6] = (hw_generation<<24)\|(numRadios<<16)\|(WARPLAB_MAJOR_VER<<8)\|(WARPLAB_MINOR_VER);
529	xilsock_sendto(sock, sendBuffer, 28, (struct sockaddr *)&addr, alen);
530	break;
531
532	case TX_DELAY:
533
534	ReadWrite = (unsigned int)receivePtr32[2];
535	if(0 == ReadWrite)
536	{
537	sendPtr32[0] = packetNo + 1;
538	sendPtr32[1] = ACK;
539	sendPtr32[2] = command;
540
541	sendPtr32[3] = warplab_mimo_ReadReg_TxDelay(WARPLAB_BASEADDR);
542
543	if(DEBUG_LVL > 2) xil_printf("Read capt offset of %d\n", (unsigned int)receivePtr32[3]);
544	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
545	}
546	if(1 == ReadWrite)
547	{
548	//If the user requests a TX_DELAY that's too big, write the maximum instead
549	warplab_buffers_WriteReg_TxDelay((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]);
550	if(DEBUG_LVL > 2) xil_printf("Set capt offset to %d\n", (unsigned int)receivePtr32[3]);
551	sendACK(packetNo, command);
552	}
553
554	break;
555
556	case TX_LENGTH:
557	ReadWrite = (unsigned int)receivePtr32[2];
558	if(0 == ReadWrite)
559	{
560	sendPtr32[0] = packetNo + 1;
561	sendPtr32[1] = ACK;
562	sendPtr32[2] = command;
563
564	sendPtr32[3] = warplab_mimo_ReadReg_TxLength(WARPLAB_BASEADDR);
565
566	if(DEBUG_LVL > 2) xil_printf("Read TxLength of %d\n", (unsigned int)receivePtr32[3]);
567	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
568	}
569	if(1 == ReadWrite)
570	{
571	//If the user requests a TX_LENGTH that's too big, write the maximum instead
572	warplab_buffers_WriteReg_TxLength((unsigned int)receivePtr32[3] > 16383 ? 16383 : (unsigned int)receivePtr32[3]);
573	if(DEBUG_LVL > 2) xil_printf("Set TxLength to %d\n", (unsigned int)receivePtr32[3]);
574	sendACK(packetNo, command);
575	}
576	break;
577
578	case TX_MODE:
579	ReadWrite = (unsigned int)receivePtr32[2];
580	if(0 == ReadWrite)
581	{
582	sendPtr32[0] = packetNo + 1;
583	sendPtr32[1] = ACK;
584	sendPtr32[2] = command;
585
586	sendPtr32[3] = warplab_mimo_ReadReg_TransMode(WARPLAB_BASEADDR);
587
588	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
589	}
590	if(1 == ReadWrite)
591	{
592	warplab_buffers_WriteReg_TransMode((unsigned int)receivePtr32[3]);
593	sendACK(packetNo, command);
594	}
595	break;
596
597
598	case RX1BUFFERS_DEBUG:
599
600	break;
601
602	case RX2BUFFERS_DEBUG:
603
604	break;
605
606	#ifdef WARPLAB_CONFIG_4RF
607	case RX3BUFFERS_DEBUG:
608
609	break;
610
611	case RX4BUFFERS_DEBUG:
612
613	break;
614	#endif
615
616	case MGC_AGC_SEL:
617	//ReadWrite = (unsigned int)receivePtr32[2];
618	MGC_AGC_Sel_Variable = (unsigned int)receivePtr32[2];
619	//if(0 == ReadWrite)
620	//{
621	// sendPtr32[0] = packetNo + 1;
622	// sendPtr32[1] = ACK;
623	// sendPtr32[2] = command;
624
625	// sendPtr32[3] = warplab_mimo_4x4_ReadReg_MGC_AGC_SEL(XPAR_WARPLAB_MIMO_4X4_OPBW_0_BASEADDR);
626
627	// xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
628	//}
629	//if(1 == ReadWrite)
630	//{
631	warplab_buffers_WriteReg_MGC_AGC_SEL(MGC_AGC_Sel_Variable);
632
633	if(0 == MGC_AGC_Sel_Variable)
634	{
635	warplab_AGC_WriteReg_AGC_EN(0);
636	radio_controller_setCtrlSource(RC_BASEADDR, (ALL_RF_SEL), RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_REG);
637	radio_controller_setRxGainSource(RC_BASEADDR, (ALL_RF_SEL), RC_GAINSRC_SPI);
638	}
639	if(1 == MGC_AGC_Sel_Variable)
640	{
641	radio_controller_setCtrlSource(RC_BASEADDR, (ALL_RF_SEL), RC_REG0_RXHP_CTRLSRC, RC_CTRLSRC_HW);
642	radio_controller_setRxGainSource(RC_BASEADDR, (ALL_RF_SEL), RC_GAINSRC_HW);
643
644	// Initialize the AGC
645	warplab_AGC_Initialize(agcnoiseEst);
646	warplab_AGC_setNoiseEstimate(agcnoiseEst);
647	// ofdm_AGC_FiltSel(0); No decimation option in WARPLab AGC
648	warplab_AGC_SetDCO(0);
649	warplab_AGC_SetTarget(agctarget);
650	warplab_AGC_Reset();
651	}
652
653	sendACK(packetNo, command);
654	//}
655	break;
656
657	case CARRIER_CHANNEL:
658	Radios_WirelessChan = ((unsigned int)receivePtr32[2]);
659
660	//Channels in [1...37] are valid
661	// Values in [1...14] select 2.4GHz channels [1...14]
662	// Values in [15...37] select a 5GHz channels [1...23]
663	if(Radios_WirelessChan <= (14+23))
664	{
665	if(Radios_WirelessChan <= 14) {
666	radio_controller_setCenterFrequency(RC_BASEADDR, (ALL_RF_SEL), RC_24GHZ, Radios_WirelessChan);
667	} else {
668	radio_controller_setCenterFrequency(RC_BASEADDR, (ALL_RF_SEL), RC_5GHZ, (Radios_WirelessChan-14));
669	}
670	}
671
672	sendACK(packetNo, command);
673	break;
674
675	case TX_LPF_CORN_FREQ:
676	Radios_Tx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]);
677	radio_controller_setRadioParam(RC_BASEADDR, (ALL_RF_SEL), RC_PARAMID_TXLPF_BW, Radios_Tx_LPF_Corn_Freq&0x3);
678	sendACK(packetNo, command);
679	break;
680
681	case RX_LPF_CORN_FREQ:
682	Radios_Rx_LPF_Corn_Freq = ((unsigned int)receivePtr32[2]);
683	radio_controller_setRadioParam(RC_BASEADDR, (ALL_RF_SEL), RC_PARAMID_RXLPF_BW, Radios_Rx_LPF_Corn_Freq&0x3);
684	sendACK(packetNo, command);
685	break;
686
687
688	case RADIO1_TXGAINS:
689	//Extract the radio gain config options from the received Ethernet packet
690	Radio1_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
691	Radio1_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
692	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_BB, Radio1_TxGain_BB);
693	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_TXGAIN_RF, Radio1_TxGain_RF);
694	//radio_controller_setTxGainTarget(RC_BASEADDR, RC_RFA, Radio1_TxGain_RF);
695	sendACK(packetNo, command);
696	break;
697
698	case RADIO1_RXGAINS:
699	//Extract the radio gain config options from the received Ethernet packet
700	Radio1_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
701	Radio1_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
702	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_BB, Radio1_RxGain_BB);
703	radio_controller_setRadioParam(RC_BASEADDR, RC_RFA, RC_PARAMID_RXGAIN_RF, Radio1_RxGain_RF);
704	sendACK(packetNo, command);
705	break;
706
707	case RADIO2_TXGAINS:
708	//Extract the radio gain config options from the received Ethernet packet
709	Radio2_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
710	Radio2_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
711	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_TXGAIN_BB, Radio2_TxGain_BB);
712	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_TXGAIN_RF, Radio2_TxGain_RF);
713	sendACK(packetNo, command);
714	break;
715
716	case RADIO2_RXGAINS:
717	//Extract the radio gain config options from the received Ethernet packet
718	Radio2_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
719	Radio2_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
720	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_RXGAIN_BB, Radio2_RxGain_BB);
721	radio_controller_setRadioParam(RC_BASEADDR, RC_RFB, RC_PARAMID_RXGAIN_RF, Radio2_RxGain_RF);
722	sendACK(packetNo, command);
723	break;
724
725	#ifdef WARPLAB_CONFIG_4RF
726	case RADIO3_TXGAINS:
727	//Extract the radio gain config options from the received Ethernet packet
728	Radio3_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
729	Radio3_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
730	radio_controller_setRadioParam(RC_BASEADDR, RC_RFC, RC_PARAMID_TXGAIN_BB, Radio3_TxGain_BB);
731	radio_controller_setRadioParam(RC_BASEADDR, RC_RFC, RC_PARAMID_TXGAIN_RF, Radio3_TxGain_RF);
732	sendACK(packetNo, command);
733	break;
734
735	case RADIO3_RXGAINS:
736	//Extract the radio gain config options from the received Ethernet packet
737	Radio3_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
738	Radio3_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
739	radio_controller_setRadioParam(RC_BASEADDR, RC_RFC, RC_PARAMID_RXGAIN_BB, Radio3_RxGain_BB);
740	radio_controller_setRadioParam(RC_BASEADDR, RC_RFC, RC_PARAMID_RXGAIN_RF, Radio3_RxGain_RF);
741	sendACK(packetNo, command);
742	break;
743
744	case RADIO4_TXGAINS:
745	//Extract the radio gain config options from the received Ethernet packet
746	Radio4_TxGain_BB = (((unsigned int)receivePtr32[2])>>16)&0x3;
747	Radio4_TxGain_RF = ((unsigned int)receivePtr32[2])&0x3F;
748	radio_controller_setRadioParam(RC_BASEADDR, RC_RFD, RC_PARAMID_TXGAIN_BB, Radio4_TxGain_BB);
749	radio_controller_setRadioParam(RC_BASEADDR, RC_RFD, RC_PARAMID_TXGAIN_RF, Radio4_TxGain_RF);
750	sendACK(packetNo, command);
751	break;
752
753	case RADIO4_RXGAINS:
754	//Extract the radio gain config options from the received Ethernet packet
755	Radio4_RxGain_RF = (((unsigned int)receivePtr32[2])>>16)&0x3;
756	Radio4_RxGain_BB = ((unsigned int)receivePtr32[2])&0x3F;
757	radio_controller_setRadioParam(RC_BASEADDR, RC_RFD, RC_PARAMID_RXGAIN_BB, Radio4_RxGain_BB);
758	radio_controller_setRadioParam(RC_BASEADDR, RC_RFD, RC_PARAMID_RXGAIN_RF, Radio4_RxGain_RF);
759	sendACK(packetNo, command);
760	break;
761	#endif
762
763
764	case RADIO1_TXEN:
765	radio_controller_TxEnable(RC_BASEADDR, (RC_RFA));
766
767	if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Enabled\n");
768	sendACK(packetNo, command);
769	break;
770
771	case RADIO2_TXEN:
772	radio_controller_TxEnable(RC_BASEADDR, (RC_RFB));
773
774	if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Enabled\n");
775	sendACK(packetNo, command);
776	break;
777
778	#ifdef WARPLAB_CONFIG_4RF
779	case RADIO3_TXEN:
780	radio_controller_TxEnable(RC_BASEADDR, (RC_RFC));
781
782	if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Enabled\n");
783	sendACK(packetNo, command);
784	break;
785
786
787	case RADIO4_TXEN:
788	radio_controller_TxEnable(RC_BASEADDR, (RC_RFD));
789
790	if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Enabled\n");
791	sendACK(packetNo, command);
792	break;
793	#endif
794
795	case RADIO1_TXDIS:
796	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA));
797	if(DEBUG_LVL > 1) xil_printf("Radio 1 Tx Disabled\n");
798	sendACK(packetNo, command);
799	break;
800
801	case RADIO2_TXDIS:
802	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFB));
803	if(DEBUG_LVL > 1) xil_printf("Radio 2 Tx Disabled\n");
804	sendACK(packetNo, command);
805	break;
806
807	#ifdef WARPLAB_CONFIG_4RF
808	case RADIO3_TXDIS:
809	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFC));
810	if(DEBUG_LVL > 1) xil_printf("Radio 3 Tx Disabled\n");
811	sendACK(packetNo, command);
812	break;
813
814	case RADIO4_TXDIS:
815	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFD));
816	if(DEBUG_LVL > 1) xil_printf("Radio 4 Tx Disabled\n");
817	sendACK(packetNo, command);
818	break;
819	#endif
820
821	case RADIO1_RXEN:
822	/*************** Setup the radio board **********/
823	if(0 == MGC_AGC_Sel_Variable)
824	{
825	// Disable the Rx HP filter
826	// Only needed in Manual Gain Control (MGC) Mode
827	// In Automatic Gain Control (AGC) Mode, the RxHp
828	// is controlled by the AGC core
829	radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_OFF);
830	}
831
832	// usleep(10);
833
834	//Enable the receiver
835	radio_controller_RxEnable(RC_BASEADDR, (RC_RFA));
836
837	if(1 == MGC_AGC_Sel_Variable)
838	{
839	//Enable this radio's AGC if user has set AGC Mode
840	warplab_AGC_WriteReg_RADIO1_AGC_EN(1);
841	}
842
843	/*************** END Setup the radio board **********/
844
845	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n");
846	if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Enabled\n");
847	sendACK(packetNo, command);
848	break;
849
850	case RADIO2_RXEN:
851
852	/*************** Setup the radio board **********/
853	if(0 == MGC_AGC_Sel_Variable)
854	{
855	// Disable the Rx HP filter
856	// Only needed in Manual Gain Control (MGC) Mode
857	// In Automatic Gain Control (AGC) Mode, the RxHp
858	// is controlled by the AGC core
859	//WarpRadio_v1_RxHpDisable(radio2);
860	radio_controller_setRxHP(RC_BASEADDR, (RC_RFB), RC_RXHP_OFF);
861	}
862
863	// usleep(10);
864
865	//Enable the receiver
866	radio_controller_RxEnable(RC_BASEADDR, (RC_RFB));
867
868	if(1 == MGC_AGC_Sel_Variable)
869	{
870	//Enable this radio's AGC if user has set AGC Mode
871	warplab_AGC_WriteReg_RADIO2_AGC_EN(1);
872	}
873
874	/*************** END Setup the radio board **********/
875
876	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n");
877	if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Enabled\n");
878	sendACK(packetNo, command);
879	break;
880
881	#ifdef WARPLAB_CONFIG_4RF
882	case RADIO3_RXEN:
883
884	/*************** Setup the radio board **********/
885	if(0 == MGC_AGC_Sel_Variable)
886	{
887	// Disable the Rx HP filter
888	// Only needed in Manual Gain Control (MGC) Mode
889	// In Automatic Gain Control (AGC) Mode, the RxHp
890	// is controlled by the AGC core
891	//WarpRadio_v1_RxHpDisable(radio2);
892	radio_controller_setRxHP(RC_BASEADDR, (RC_RFC), RC_RXHP_OFF);
893	}
894
895	// usleep(10);
896
897	//Enable the receiver
898	radio_controller_RxEnable(RC_BASEADDR, (RC_RFC));
899
900	if(1 == MGC_AGC_Sel_Variable)
901	{
902	//Enable this radio's AGC if user has set AGC Mode
903	warplab_AGC_WriteReg_RADIO3_AGC_EN(1);
904	}
905
906	/*************** END Setup the radio board **********/
907
908	//if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Enabled\n");
909	if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Enabled\n");
910	sendACK(packetNo, command);
911	break;
912
913	case RADIO4_RXEN:
914
915	/*************** Setup the radio board **********/
916	if(0 == MGC_AGC_Sel_Variable)
917	{
918	// Disable the Rx HP filter
919	// Only needed in Manual Gain Control (MGC) Mode
920	// In Automatic Gain Control (AGC) Mode, the RxHp
921	// is controlled by the AGC core
922	//WarpRadio_v1_RxHpDisable(radio2);
923	radio_controller_setRxHP(RC_BASEADDR, (RC_RFD), RC_RXHP_OFF);
924	}
925
926	// usleep(10);
927
928	//Enable the receiver
929	radio_controller_RxEnable(RC_BASEADDR, (RC_RFD));
930
931	if(1 == MGC_AGC_Sel_Variable)
932	{
933	//Enable this radio's AGC if user has set AGC Mode
934	warplab_AGC_WriteReg_RADIO4_AGC_EN(1);
935	}
936
937	/*************** END Setup the radio board **********/
938
939	//if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Enabled\n");
940	if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Enabled\n");
941	sendACK(packetNo, command);
942	break;
943	#endif
944
945	case RADIO1_RXDIS:
946	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFA));
947
948	if(0 == MGC_AGC_Sel_Variable)
949	{
950	//Enable the Rx HP filter
951	// Only needed in Manual Gain Control (MGC) Mode
952	// In Automatic Gain Control (AGC) Mode, the RxHp
953	// is controlled by the AGC core
954	radio_controller_setRxHP(RC_BASEADDR, (RC_RFA), RC_RXHP_ON);
955	}
956
957	if(1 == MGC_AGC_Sel_Variable)
958	{
959	//Disable this radio's AGC if user has set AGC Mode
960	warplab_AGC_WriteReg_RADIO1_AGC_EN(0);
961	}
962
963	//if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n");
964	if(DEBUG_LVL > 1) xil_printf("Radio 1 Rx Disabled\n");
965	sendACK(packetNo, command);
966	break;
967
968	case RADIO2_RXDIS:
969	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFB));
970
971	if(0 == MGC_AGC_Sel_Variable)
972	{
973	//Enable the Rx HP filter
974	// Only needed in Manual Gain Control (MGC) Mode
975	// In Automatic Gain Control (AGC) Mode, the RxHp
976	// is controlled by the AGC core
977	radio_controller_setRxHP(RC_BASEADDR, (RC_RFB), RC_RXHP_ON);
978	}
979
980	if(1 == MGC_AGC_Sel_Variable)
981	{
982	//Disable this radio's AGC if user has set AGC Mode
983	warplab_AGC_WriteReg_RADIO2_AGC_EN(0);
984	}
985
986	//if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n");
987	if(DEBUG_LVL > 1) xil_printf("Radio 2 Rx Disabled\n");
988	sendACK(packetNo, command);
989	break;
990
991	#ifdef WARPLAB_CONFIG_4RF
992	case RADIO3_RXDIS:
993	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFC));
994
995	if(0 == MGC_AGC_Sel_Variable)
996	{
997	//Enable the Rx HP filter
998	// Only needed in Manual Gain Control (MGC) Mode
999	// In Automatic Gain Control (AGC) Mode, the RxHp
1000	// is controlled by the AGC core
1001	radio_controller_setRxHP(RC_BASEADDR, (RC_RFC), RC_RXHP_ON);
1002	}
1003
1004	if(1 == MGC_AGC_Sel_Variable)
1005	{
1006	//Disable this radio's AGC if user has set AGC Mode
1007	warplab_AGC_WriteReg_RADIO3_AGC_EN(0);
1008	}
1009
1010	//if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n");
1011	if(DEBUG_LVL > 1) xil_printf("Radio 3 Rx Disabled\n");
1012	sendACK(packetNo, command);
1013	break;
1014
1015	case RADIO4_RXDIS:
1016	radio_controller_TxRxDisable(RC_BASEADDR, (RC_RFD));
1017
1018	if(0 == MGC_AGC_Sel_Variable)
1019	{
1020	//Enable the Rx HP filter
1021	// Only needed in Manual Gain Control (MGC) Mode
1022	// In Automatic Gain Control (AGC) Mode, the RxHp
1023	// is controlled by the AGC core
1024	radio_controller_setRxHP(RC_BASEADDR, (RC_RFD), RC_RXHP_ON);
1025	}
1026
1027	if(1 == MGC_AGC_Sel_Variable)
1028	{
1029	//Disable this radio's AGC if user has set AGC Mode
1030	warplab_AGC_WriteReg_RADIO4_AGC_EN(0);
1031	}
1032
1033	//if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n");
1034	if(DEBUG_LVL > 1) xil_printf("Radio 4 Rx Disabled\n");
1035	sendACK(packetNo, command);
1036	break;
1037	#endif
1038
1039	case RADIO1_TXDATA:
1040	memcpy
1041	(
1042	(unsigned int )(WARPLAB_TXBUFF_RADIO1 + 4rxArg0),\
1043	(unsigned int *)(receivePtr32 + 3),\
1044	(bytesReceived-12)
1045	);
1046	sendACK(packetNo, command);
1047	break;
1048
1049	case RADIO2_TXDATA:
1050	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
1051	//if(DEBUG_LVL > 1) xil_printf("Sample bytes: %x %x %x %x\n", (unsigned int )(receivePtr32 + 3), (unsigned int )(receivePtr32 + 4), (unsigned int )(receivePtr32 + 5), (unsigned int )(receivePtr32 + 6));
1052
1053	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
1054
1055	//if(DEBUG_LVL > 1) xil_printf("Got some data for Radio 2 Tx (offset: %x)\n",rxArg0);
1056
1057	memcpy
1058	(
1059	(unsigned int )(WARPLAB_TXBUFF_RADIO2 + 4rxArg0),\
1060	(unsigned int *)(receivePtr32 + 3),\
1061	(bytesReceived-12)
1062	);
1063
1064	sendACK(packetNo, command);
1065	break;
1066
1067
1068	#ifdef WARPLAB_CONFIG_4RF
1069	case RADIO3_TXDATA:
1070	memcpy
1071	(
1072	(unsigned int )(WARPLAB_TXBUFF_RADIO3 + 4rxArg0),\
1073	(unsigned int *)(receivePtr32 + 3),\
1074	(bytesReceived-12)
1075	);
1076	sendACK(packetNo, command);
1077	break;
1078
1079	case RADIO4_TXDATA:
1080	memcpy
1081	(
1082	(unsigned int )(WARPLAB_TXBUFF_RADIO4 + 4rxArg0),\
1083	(unsigned int *)(receivePtr32 + 3),\
1084	(bytesReceived-12)
1085	);
1086	sendACK(packetNo, command);
1087	break;
1088	#endif
1089
1090
1091	case RADIO1_RXDATA:
1092	memcpy
1093	(
1094	(unsigned int *)(sendPtr32 + 4), \
1095	(unsigned int )(WARPLAB_RXBUFF_RADIO1 + 4rxArg0),\
1096	1024
1097	);
1098
1099	sendPtr32[0] = packetNo + 1;
1100	sendPtr32[1] = ACK;
1101	sendPtr32[2] = command;
1102	sendPtr32[3] = rxArg0;
1103	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1104	break;
1105
1106	case RADIO2_RXDATA:
1107	//while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {}
1108
1109	/*
1110	memcpy
1111	(
1112	(unsigned int *)(sendPtr32 + 4), \
1113	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + 4rxArg0),\
1114	1024
1115	);
1116	*/
1117	memcpy
1118	(
1119	(unsigned int *)(sendPtr32 + 4), \
1120	(unsigned int )(WARPLAB_RXBUFF_RADIO2 + 4rxArg0),\
1121	1024
1122	);
1123
1124	//if(DEBUG_LVL > 1) xil_printf("Read Rx data (offset: %x)\n",rxArg0);
1125	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RxBuff_Radio2_OFFSET + rxArg0));
1126
1127	sendPtr32[0] = packetNo + 1;
1128	sendPtr32[1] = ACK;
1129	sendPtr32[2] = command;
1130	sendPtr32[3] = rxArg0;
1131	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1132	break;
1133	#ifdef WARPLAB_CONFIG_4RF
1134	case RADIO3_RXDATA:
1135	memcpy
1136	(
1137	(unsigned int *)(sendPtr32 + 4), \
1138	(unsigned int )(WARPLAB_RXBUFF_RADIO3 + 4rxArg0),\
1139	1024
1140	);
1141
1142	sendPtr32[0] = packetNo + 1;
1143	sendPtr32[1] = ACK;
1144	sendPtr32[2] = command;
1145	sendPtr32[3] = rxArg0;
1146	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1147	break;
1148
1149	case RADIO4_RXDATA:
1150	memcpy
1151	(
1152	(unsigned int *)(sendPtr32 + 4), \
1153	(unsigned int )(WARPLAB_RXBUFF_RADIO4 + 4rxArg0),\
1154	1024
1155	);
1156
1157	sendPtr32[0] = packetNo + 1;
1158	sendPtr32[1] = ACK;
1159	sendPtr32[2] = command;
1160	sendPtr32[3] = rxArg0;
1161	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1162	break;
1163	#endif
1164
1165
1166	case RADIO1_RSSIDATA:
1167	memcpy
1168	(
1169	(unsigned int *)(sendPtr32 + 4), \
1170	(unsigned int )(WARPLAB_RSSIBUFF_RADIO1 + 4rxArg0),\
1171	1024
1172	);
1173	sendPtr32[0] = packetNo + 1;
1174	sendPtr32[1] = ACK;
1175	sendPtr32[2] = command;
1176	sendPtr32[3] = rxArg0;
1177	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1178	break;
1179
1180	case RADIO2_RSSIDATA:
1181	//while(warplab_mimo_2x2_ReadReg_CaptureDone(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR) == 0) {}
1182
1183	/*
1184	memcpy
1185	(
1186	(unsigned int *)(sendPtr32 + 4), \
1187	(unsigned int )(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4rxArg0),\
1188	1024
1189	);
1190	*/
1191	memcpy
1192	(
1193	(unsigned int *)(sendPtr32 + 4), \
1194	(unsigned int )(WARPLAB_RSSIBUFF_RADIO2 + 4rxArg0),\
1195	1024
1196	);
1197
1198
1199	//if(DEBUG_LVL > 1) xil_printf("Read RSSI data (offset: %x)\n",rxArg0);
1200	//if(DEBUG_LVL > 1) xil_printf("Copied 1024 bytes from %x\n",(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR + warplab_mimo_2x2_SMRO_RSSIBuff_Radio2_OFFSET + 4*rxArg0));
1201
1202	sendPtr32[0] = packetNo + 1;
1203	sendPtr32[1] = ACK;
1204	sendPtr32[2] = command;
1205	sendPtr32[3] = rxArg0;
1206	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1207	break;
1208
1209	#ifdef WARPLAB_CONFIG_4RF
1210	case RADIO3_RSSIDATA:
1211	memcpy
1212	(
1213	(unsigned int *)(sendPtr32 + 4), \
1214	(unsigned int )(WARPLAB_RSSIBUFF_RADIO3 + 4rxArg0),\
1215	1024
1216	);
1217	sendPtr32[0] = packetNo + 1;
1218	sendPtr32[1] = ACK;
1219	sendPtr32[2] = command;
1220	sendPtr32[3] = rxArg0;
1221	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1222	break;
1223
1224	case RADIO4_RSSIDATA:
1225	memcpy
1226	(
1227	(unsigned int *)(sendPtr32 + 4), \
1228	(unsigned int )(WARPLAB_RSSIBUFF_RADIO4 + 4rxArg0),\
1229	1024
1230	);
1231	sendPtr32[0] = packetNo + 1;
1232	sendPtr32[1] = ACK;
1233	sendPtr32[2] = command;
1234	sendPtr32[3] = rxArg0;
1235	xilsock_sendto(sock, sendBuffer, 16+1024, (struct sockaddr *)&addr, alen);
1236	break;
1237	#endif
1238
1239
1240	case RADIO1TXBUFF_TXEN:
1241	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(1);
1242
1243	sendACK(packetNo, command);
1244	break;
1245
1246	case RADIO2TXBUFF_TXEN:
1247	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(1);
1248
1249	sendACK(packetNo, command);
1250	break;
1251
1252	#ifdef WARPLAB_CONFIG_4RF
1253	case RADIO3TXBUFF_TXEN:
1254	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(1);
1255
1256	sendACK(packetNo, command);
1257	break;
1258
1259	case RADIO4TXBUFF_TXEN:
1260	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(1);
1261
1262	sendACK(packetNo, command);
1263	break;
1264	#endif
1265
1266	case RADIO1TXBUFF_TXDIS:
1267	warplab_buffers_WriteReg_RADIO1TXBUFF_TXEN(0);
1268
1269	sendACK(packetNo, command);
1270	break;
1271
1272	case RADIO2TXBUFF_TXDIS:
1273	warplab_buffers_WriteReg_RADIO2TXBUFF_TXEN(0);
1274
1275	sendACK(packetNo, command);
1276	break;
1277
1278	#ifdef WARPLAB_CONFIG_4RF
1279	case RADIO3TXBUFF_TXDIS:
1280	warplab_buffers_WriteReg_RADIO3TXBUFF_TXEN(0);
1281
1282	sendACK(packetNo, command);
1283	break;
1284
1285	case RADIO4TXBUFF_TXDIS:
1286	warplab_buffers_WriteReg_RADIO4TXBUFF_TXEN(0);
1287
1288	sendACK(packetNo, command);
1289	break;
1290	#endif
1291
1292	case RADIO1RXBUFF_RXEN:
1293	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(1);
1294
1295	sendACK(packetNo, command);
1296	break;
1297
1298	case RADIO2RXBUFF_RXEN:
1299	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(1);
1300
1301	sendACK(packetNo, command);
1302	break;
1303
1304	#ifdef WARPLAB_CONFIG_4RF
1305	case RADIO3RXBUFF_RXEN:
1306	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(1);
1307
1308	sendACK(packetNo, command);
1309	break;
1310
1311	case RADIO4RXBUFF_RXEN:
1312	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(1);
1313
1314	sendACK(packetNo, command);
1315	break;
1316	#endif
1317
1318	case RADIO1RXBUFF_RXDIS:
1319	warplab_buffers_WriteReg_RADIO1RXBUFF_RXEN(0);
1320
1321	sendACK(packetNo, command);
1322	break;
1323
1324	case RADIO2RXBUFF_RXDIS:
1325	warplab_buffers_WriteReg_RADIO2RXBUFF_RXEN(0);
1326
1327	sendACK(packetNo, command);
1328	break;
1329
1330	#ifdef WARPLAB_CONFIG_4RF
1331	case RADIO3RXBUFF_RXDIS:
1332	warplab_buffers_WriteReg_RADIO3RXBUFF_RXEN(0);
1333
1334	sendACK(packetNo, command);
1335	break;
1336
1337	case RADIO4RXBUFF_RXDIS:
1338	warplab_buffers_WriteReg_RADIO4RXBUFF_RXEN(0);
1339
1340	sendACK(packetNo, command);
1341	break;
1342	#endif
1343
1344	case RX_DONECHECK:
1345
1346	sendPtr32[0] = packetNo + 1;
1347	sendPtr32[1] = ACK;
1348	sendPtr32[2] = command;
1349
1350	if(warplab_mimo_ReadReg_CaptureDone(WARPLAB_BASEADDR) == 0)
1351	sendPtr32[3] = 0;
1352	else
1353	sendPtr32[3] = 1;
1354
1355	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1356	break;
1357
1358	case RX_DONEREADING:
1359	//warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 1);
1360	//warplab_mimo_2x2_WriteReg_DoneReading(XPAR_WARPLAB_MIMO_2X2_OPBW_0_BASEADDR, 0);
1361
1362	sendACK(packetNo, command);
1363	break;
1364
1365	case RX_START:
1366	//if(DEBUG_LVL > 1) xil_printf("Starting Rx\n");
1367	//if(DEBUG_LVL > 1) xil_printf("Starting Rx\n");
1368	sendACK(packetNo, command);
1369
1370	if(waitForSync() == 0)
1371	{
1372	warplab_buffers_WriteReg_StartCapture(1);
1373	warplab_AGC_Start();
1374	warplab_buffers_WriteReg_StartCapture(0);
1375
1376	//if(DEBUG_LVL > 1) xil_printf("Capture started\n");
1377	}
1378	else
1379	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Rx Capture\n");
1380	break;
1381
1382	case TX_START:
1383	//if(DEBUG_LVL > 1) xil_printf("Starting Tx\n");
1384	if(DEBUG_LVL > 1) xil_printf("Starting Tx\n");
1385	sendACK(packetNo, command);
1386
1387	if(waitForSync() == 0)
1388	{
1389	warplab_buffers_WriteReg_StartTx(1);
1390	warplab_buffers_WriteReg_StartTx(0);
1391	//if(DEBUG_LVL > 1) xil_printf("Transmit started\n");
1392	}
1393	else
1394	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling Tx\n");
1395	break;
1396
1397	case TX_STOP:
1398	sendACK(packetNo, command);
1399
1400	warplab_buffers_WriteReg_StopTx(1);
1401	warplab_buffers_WriteReg_StopTx(0);
1402
1403	break;
1404
1405	case TXRX_START:
1406	if(DEBUG_LVL > 1) xil_printf("Starting TxRX\n");
1407	sendACK(packetNo, command);
1408
1409	if(waitForSync() == 0)
1410	{
1411	warplab_buffers_WriteReg_StartTxRx(1);
1412	warplab_buffers_WriteReg_StartTxRx(0);
1413	}
1414	else
1415	if(DEBUG_LVL > 1) xil_printf("No MAGIC_SYNC received; canceling TxRx\n");
1416	break;
1417
1418	case READ_AGC_DONE_ADDR:
1419	sendPtr32[0] = packetNo + 1;
1420	sendPtr32[1] = ACK;
1421	sendPtr32[2] = command;
1422
1423	sendPtr32[3] = warplab_mimo_ReadReg_AGCDoneAddr(WARPLAB_BASEADDR);
1424
1425	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1426	break;
1427
1428	case READ_RADIO1AGCDONERSSI:
1429	sendPtr32[0] = packetNo + 1;
1430	sendPtr32[1] = ACK;
1431	sendPtr32[2] = command;
1432
1433	sendPtr32[3] = warplab_mimo_ReadReg_Radio1AGCDoneRSSI(WARPLAB_BASEADDR);
1434
1435	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1436	break;
1437
1438	case READ_RADIO2AGCDONERSSI:
1439	sendPtr32[0] = packetNo + 1;
1440	sendPtr32[1] = ACK;
1441	sendPtr32[2] = command;
1442
1443	sendPtr32[3] = warplab_mimo_ReadReg_Radio2AGCDoneRSSI(WARPLAB_BASEADDR);
1444
1445	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1446	break;
1447
1448	#ifdef WARPLAB_CONFIG_4RF
1449	case READ_RADIO3AGCDONERSSI:
1450	sendPtr32[0] = packetNo + 1;
1451	sendPtr32[1] = ACK;
1452	sendPtr32[2] = command;
1453
1454	sendPtr32[3] = warplab_mimo_ReadReg_Radio3AGCDoneRSSI(WARPLAB_BASEADDR);
1455
1456	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1457	break;
1458
1459	case READ_RADIO4AGCDONERSSI:
1460	sendPtr32[0] = packetNo + 1;
1461	sendPtr32[1] = ACK;
1462	sendPtr32[2] = command;
1463
1464	sendPtr32[3] = warplab_mimo_ReadReg_Radio4AGCDoneRSSI(WARPLAB_BASEADDR);
1465
1466	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1467	break;
1468	#endif
1469
1470	case AGC_RESET:
1471	warplab_AGC_Reset();
1472	sendACK(packetNo, command);
1473	break;
1474
1475	case READ_AGC_GAINS:
1476	sendPtr32[0] = packetNo + 1;
1477	sendPtr32[1] = ACK;
1478	sendPtr32[2] = command;
1479
1480	sendPtr32[3] = warplab_AGC_GetGains();
1481
1482	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1483	break;
1484
1485	case SET_AGC_TARGET_dBm:
1486	agctarget = (int)receivePtr32[2];
1487	warplab_AGC_SetTarget(agctarget);
1488	//xil_printf("agctarget = %d\n",agctarget);
1489	sendACK(packetNo, command);
1490	break;
1491
1492	case SET_AGC_DCO_EN_DIS:
1493	agc_dco_state = (unsigned int)receivePtr32[2];
1494	warplab_AGC_SetDCO(agc_dco_state);
1495	warplab_buffers_WriteReg_DCO_EN_SEL(agc_dco_state);
1496	//xil_printf("agc_dco_state = %d\n",agc_dco_state);
1497	sendACK(packetNo, command);
1498	break;
1499
1500	case SET_AGC_NOISEEST_dBm:
1501	agcnoiseEst = (int)receivePtr32[2];
1502	warplab_AGC_setNoiseEstimate(agcnoiseEst);
1503	//xil_printf("agctarget = %d\n",agctarget);
1504	sendACK(packetNo, command);
1505	break;
1506
1507	case SET_AGC_THRESHOLDS:
1508	warplab_AGC_WriteReg_Thresholds((unsigned int)receivePtr32[2]);
1509	sendACK(packetNo, command);
1510	break;
1511
1512	case SET_AGC_TRIG_DELAY:
1513	warplab_AGC_WriteReg_AGC_TRIGGER_DELAY((unsigned int)receivePtr32[2]);
1514	sendACK(packetNo, command);
1515	break;
1516
1517	case READ_AGC_THRESHOLDS:
1518	sendPtr32[0] = packetNo + 1;
1519	sendPtr32[1] = ACK;
1520	sendPtr32[2] = command;
1521
1522	sendPtr32[3] = warplab_AGC_ReadReg_Thresholds(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1523
1524	xilsock_sendto(sock, sendBuffer, 16, (struct sockaddr *)&addr, alen);
1525	break;
1526
1527	case CLOSE:
1528	if(DEBUG_LVL > 1) xil_printf("Closing sockets.\n");
1529	sendACK(packetNo, command);
1530	done = 1;
1531
1532	break;
1533
1534	case TX_TEST:
1535	if(DEBUG_LVL > 1) xil_printf("Starting Tx Test\n");
1536	sendACK(packetNo, command);
1537
1538	break;
1539
1540	default:
1541	if(DEBUG_LVL > 1) {}
1542	xil_printf("Received command (%d) is not recognized. Please retry transmission.\n", command);
1543
1544	sendPtr32[0] = packetNo + 1;
1545	sendPtr32[1] = NOACK;
1546	bytesSend = 8;
1547	xilsock_sendto(sock, sendBuffer, bytesSend, (struct sockaddr *)&addr, alen);
1548	}
1549	}
1550	}
1551
1552	shut_socket();
1553
1554	return 0;
1555	}
1556
1557	void sendACK(unsigned int packetNo, unsigned int commandToACK)
1558	{
1559	sendPtr32[0] = packetNo + 1;
1560	sendPtr32[1] = ACK;
1561	sendPtr32[2] = commandToACK;
1562	xilsock_sendto(sock, sendBuffer, 12, (struct sockaddr *)&addr, alen);
1563	return;
1564	}
1565
1566	unsigned char sevenSegmentMap(unsigned char x)
1567	{
1568	switch(x)
1569	{
1570	case(0x0) : return 0x007E;
1571	case(0x1) : return 0x0030;
1572	case(0x2) : return 0x006D;
1573	case(0x3) : return 0x0079;
1574	case(0x4) : return 0x0033;
1575	case(0x5) : return 0x005B;
1576	case(0x6) : return 0x005F;
1577	case(0x7) : return 0x0070;
1578	case(0x8) : return 0x007F;
1579	case(0x9) : return 0x007B;
1580
1581	case(0xA) : return 0x0077;
1582	case(0xB) : return 0x007F;
1583	case(0xC) : return 0x004E;
1584	case(0xD) : return 0x007E;
1585	case(0xE) : return 0x004F;
1586	case(0xF) : return 0x0047;
1587	default : return 0x0000;
1588	}
1589	}
1590
1591	#define XPAR_EEPROM_CONTROLLER_BASEADDR XPAR_EEPROM_CONTROLLER_MEM0_BASEADDR
1592	//New TxDCO calibration code
1593	int warpphy_applyTxDCOCalibration(unsigned int radioSelection)
1594	{
1595	#if 0
1596	int eepromStatus = 0;
1597	short calReadback = 0;
1598	signed short best_I, best_Q;
1599	unsigned char radioNum;
1600	Xuint8 memory[8], version, revision, valid, i;
1601	Xuint16 serial;
1602
1603	//Radio selection will be 0x11111111, 0x22222222, 0x44444444 or 0x88888888
1604	// corresponding to radios in slots 1, 2, 3 or 4
1605	// We need the slot number to initialize the EEPROM
1606	radioNum = (radioSelection & 0xF) == 1 ? 1 : ( (radioSelection & 0xF) == 2 ? 2 : ( (radioSelection & 0xF) == 4 ? 3 : 4 ) );
1607	if(DEBUG_LVL>2) xil_printf("Applying TxDCO correction for radio %d\n", radioNum);
1608
1609	//Mimic the radio test code, in hopes of a more stable EEPROM read...
1610	//Choose the EEPROM on the selected radio board; second arg is [0,1,2,3,4] for [FPGA, radio1, radio2, radio3, radio4]
1611	eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR, 0);
1612	if(eepromStatus != 0)
1613	{
1614	if(DEBUG_LVL>2) xil_printf("EEPROM Select Failed!\n");
1615	return -1;
1616	}
1617
1618	//Initialize the EEPROM controller
1619	eepromStatus = WarpEEPROM_Initialize((unsigned int *)XPAR_EEPROM_CONTROLLER_BASEADDR);
1620	if(eepromStatus != 0)
1621	{
1622	if(DEBUG_LVL>2) xil_printf("EEPROM Init Returned %x\n", eepromStatus);
1623	if(DEBUG_LVL>2) xil_printf("EEPROM Init Failed!\n");
1624	return -1;
1625	}
1626
1627	//Select the EEPROM on the current radio board
1628	eepromStatus = WarpEEPROM_EEPROMSelect((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, radioNum);
1629
1630	if(eepromStatus != 0)
1631	{
1632	if(DEBUG_LVL>2) xil_printf("TxDCO: EEPROM error\n");
1633	return -1;
1634	}
1635
1636	//Read the first page from the EERPOM
1637	WarpEEPROM_ReadMem((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 0, 0, memory);
1638	version = (memory[0] & 0xE0) >> 5;
1639	revision = (memory[1] & 0xE0) >> 5;
1640	valid = memory[1] & 0x1F;
1641
1642	if(DEBUG_LVL>2) xil_printf("\n\nEEPROM Values for Radio Board in Slot %d\n", radioNum);
1643
1644	if(DEBUG_LVL>2) xil_printf(" WARP Radio Board Version %d.%d\n", version, revision);
1645
1646	serial = WarpEEPROM_ReadWARPSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR);
1647
1648	if(DEBUG_LVL>2) xil_printf(" Serial Number (WARP): WR-a-%05d\n", serial);
1649
1650	WarpEEPROM_ReadDSSerial((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, memory);
1651	if(DEBUG_LVL>2) print(" EEPROM Hard-wired Serial Number: ");
1652	if(DEBUG_LVL>2){
1653	for(i=1;i<7;i++)
1654	xil_printf(" %x",memory[7-i]);
1655	xil_printf("\n\n");
1656	}
1657	//Read the Tx DCO values
1658	calReadback = WarpEEPROM_ReadRadioCal((unsigned int*)XPAR_EEPROM_CONTROLLER_BASEADDR, 2, 1);
1659
1660	//Scale the stored values
1661	best_I = (signed short)(((signed char)(calReadback & 0xFF))<<1);
1662	best_Q = (signed short)(((signed char)((calReadback>>8) & 0xFF))<<1);
1663
1664	if(DEBUG_LVL>2) xil_printf("TxDCO: Applied values to radio %d - I: %d\tQ: %d\n", radioNum, best_I, best_Q);
1665
1666	//Finally, write the Tx DCO values to the DAC
1667	WarpRadio_v1_DACOffsetAdj(ICHAN, best_I, radioSelection);
1668	WarpRadio_v1_DACOffsetAdj(QCHAN, best_Q, radioSelection);
1669	#endif
1670	return 0;
1671	}
1672
1673
1674	void warplab_AGC_Reset()
1675	{
1676	// Cycle the agc's software reset port
1677
1678	warplab_AGC_WriteReg_SRESET_IN(1);
1679	usleep(10);
1680	warplab_AGC_WriteReg_SRESET_IN(0);
1681	usleep(100);
1682
1683	return;
1684	}
1685
1686	void warplab_AGC_MasterReset()
1687	{
1688	// Cycle the master reset register in the AGC and enable it
1689
1690	warplab_AGC_WriteReg_AGC_EN(0);
1691	usleep(10);
1692	warplab_AGC_WriteReg_MRESET_IN(0);
1693	usleep(10);
1694	warplab_AGC_WriteReg_MRESET_IN(1);
1695	usleep(10);
1696	warplab_AGC_WriteReg_MRESET_IN(0);
1697	usleep(10);
1698	warplab_AGC_WriteReg_AGC_EN(1);
1699
1700	return;
1701	}
1702
1703	void warplab_AGC_Start()
1704	{
1705	// Cycle the agc's packet in port
1706	warplab_AGC_WriteReg_PACKET_IN(1);
1707	usleep(10);
1708	warplab_AGC_WriteReg_PACKET_IN(0);
1709	usleep(100);
1710
1711	return;
1712	}
1713
1714	void warplab_AGC_Initialize(int noise_estimate)
1715	{
1716	int g_bbset = 0;
1717
1718	// First set all standard parameters
1719
1720	// Turn off both resets and the master enable
1721	warplab_AGC_WriteReg_AGC_EN(0);
1722	warplab_AGC_WriteReg_SRESET_IN(0);
1723	warplab_AGC_WriteReg_MRESET_IN(0);
1724
1725	// An adjustment parameter
1726	warplab_AGC_WriteReg_ADJ(8);
1727
1728	// Timing for the DC-offset correction
1729	warplab_AGC_WriteReg_DCO_Timing(0x12001000);
1730
1731	// Initial baseband gain setting
1732	warplab_AGC_WriteReg_GBB_init(52);
1733
1734	// RF gain AGCstate thresholds
1735	warplab_AGC_WriteReg_Thresholds(0xD5CBA6);
1736
1737	// Overall AGC timing
1738	warplab_AGC_WriteReg_Timing(0x9A962A28);//0x826E3C0A;
1739
1740	// vIQ and RSSI average lengths
1741	warplab_AGC_WriteReg_AVG_LEN(0x10F); //103
1742
1743	// Disable DCO, disable DCO subtraction
1744	warplab_AGC_WriteReg_Bits(0x0);
1745
1746	// Compute and set the initial g_BB gain value from the noise estimate
1747	// The initial g_bb sets noise to -19 db, assuming 32 db RF gain
1748
1749	g_bbset = -19 - 32 - noise_estimate;
1750	warplab_AGC_WriteReg_GBB_init(g_bbset);
1751
1752	// Perform a master reset
1753	warplab_AGC_MasterReset();
1754
1755	// Agc is now reset and enabled, ready to go!
1756	return;
1757	}
1758
1759	void warplab_AGC_setNoiseEstimate(int noise_estimate)
1760	{
1761	int g_bbset;
1762
1763	g_bbset = -19 - 32 - noise_estimate;
1764
1765	warplab_AGC_WriteReg_GBB_init(g_bbset);
1766
1767	return;
1768	}
1769
1770	unsigned int warplab_AGC_GetGains(void)
1771	{
1772	unsigned int gBB_A, gRF_A, gBB_B, gRF_B, gBB_C, gRF_C, gBB_D, gRF_D, gains;
1773
1774	// Get the gains from the registers
1775	gBB_A = warplab_AGC_ReadReg_GBB_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1776	gRF_A = warplab_AGC_ReadReg_GRF_A(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1777
1778	gBB_B = warplab_AGC_ReadReg_GBB_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1779	gRF_B = warplab_AGC_ReadReg_GRF_B(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1780
1781	gBB_C = warplab_AGC_ReadReg_GBB_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1782	gRF_C = warplab_AGC_ReadReg_GRF_C(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1783
1784	gBB_D = warplab_AGC_ReadReg_GBB_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1785	gRF_D = warplab_AGC_ReadReg_GRF_D(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1786
1787	// First concatenate the two radios together, into the gRF register
1788	// 2 lowest bits are RF, 5 higher bits are BB, last bit is unused
1789	// Multiply by 2^2, shift gBB right by 2 bits
1790
1791	gRF_A = gRF_A + (gBB_A * 4);
1792	gRF_B = gRF_B + (gBB_B * 4);
1793	gRF_C = gRF_C + (gBB_C * 4);
1794	gRF_D = gRF_D + (gBB_D * 4);
1795
1796	// Multiply by 2^8 shift gRF right by 8 bits
1797
1798	gains = gRF_A + (gRF_B * 256) + (gRF_C * 65536) + (gRF_D * 16777216);
1799
1800	return gains;
1801	}
1802
1803	void warplab_AGC_SetTarget(unsigned int target)
1804	{
1805	warplab_AGC_WriteReg_T_dB(target);
1806	return;
1807	}
1808
1809	void warplab_AGC_SetDCO(unsigned int AGCstate)
1810	{
1811	// Enables DCO and DCO subtraction (correction scheme and butterworth hipass are active)
1812
1813	unsigned int bits;
1814
1815	bits = warplab_AGC_ReadReg_Bits(XPAR_WARPLAB_MIMO_4X4_AGC_PLBW_0_BASEADDR);
1816
1817	if(AGCstate)
1818	bits = bits \| 0x6;
1819	else
1820	bits = bits & 0x1;
1821
1822	warplab_AGC_WriteReg_Bits(bits);
1823
1824	return;
1825	}

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source: ResearchApps/PHY/WARPLAB/WARPLab_v6p4/C_Code_Reference/warp_v3/warplab.c

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