1 |
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2 | # ##############################################################################
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3 | # Template Project for WARP v3 Rev 1.1
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4 | # Family: virtex6
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5 | # Device: xc6vlx240t
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6 | # Package: ff1156
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7 | # Speed Grade: -2
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8 | # Processor number: 1
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9 | # Processor 1: microblaze_0
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10 | # Processor and primary bus clock frequency: 160.0 MHz
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11 | # Secondary bus clock frequency: 80.0 MHz
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12 | # ##############################################################################
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13 | PARAMETER VERSION = 2.1.0
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14 |
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15 |
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16 | # User IO (LEDs, buttons, etc.) pins
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17 | PORT USERIO_hexdisp_left_pin = USERIO_hexdisp_left_pin, DIR = O, VEC = [0:6]
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18 | PORT USERIO_hexdisp_right_pin = USERIO_hexdisp_right_pin, DIR = O, VEC = [0:6]
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19 | PORT USERIO_hexdisp_left_dp_pin = USERIO_hexdisp_left_dp_pin, DIR = O
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20 | PORT USERIO_hexdisp_right_dp_pin = USERIO_hexdisp_right_dp_pin, DIR = O
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21 | PORT USERIO_leds_red_pin = USERIO_leds_red_pin, DIR = O, VEC = [0:3]
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22 | PORT USERIO_leds_green_pin = USERIO_leds_green_pin, DIR = O, VEC = [0:3]
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23 | PORT USERIO_rfa_led_red_pin = USERIO_rfa_led_red_pin, DIR = O
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24 | PORT USERIO_rfa_led_green_pin = USERIO_rfa_led_green_pin, DIR = O
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25 | PORT USERIO_rfb_led_red_pin = USERIO_rfb_led_red_pin, DIR = O
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26 | PORT USERIO_rfb_led_green_pin = USERIO_rfb_led_green_pin, DIR = O
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27 | PORT USERIO_dipsw_pin = USERIO_dipsw_pin, DIR = I, VEC = [0:3]
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28 | PORT USERIO_pb_u_pin = USERIO_pb_u_pin, DIR = I
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29 | PORT USERIO_pb_m_pin = USERIO_pb_m_pin, DIR = I
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30 | PORT USERIO_pb_d_pin = USERIO_pb_d_pin, DIR = I
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31 | # USB UART transceiver pins
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32 | PORT UART_USB_RX_pin = UART_USB_RX_pin, DIR = I
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33 | PORT UART_USB_TX_pin = UART_USB_TX_pin, DIR = O
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34 | # IIC EEPROM pins
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35 | PORT IIC_EEPROM_iic_scl_pin = IIC_EEPROM_iic_scl_pin, DIR = IO
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36 | PORT IIC_EEPROM_iic_sda_pin = IIC_EEPROM_iic_sda_pin, DIR = IO
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37 | PORT FMC_IIC_EEPROM_scl_pin = FMC_IIC_EEPROM_scl_pin, DIR = IO
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38 | PORT FMC_IIC_EEPROM_sda_pin = FMC_IIC_EEPROM_sda_pin, DIR = IO
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39 | # Eth A RGMII pins
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40 | PORT ETH_A_TemacPhy_RST_n_pin = ETH_A_TemacPhy_RST_n_pin, DIR = O
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41 | PORT ETH_A_RGMII_TXD_0_pin = ETH_A_RGMII_TXD_0_pin, DIR = O, VEC = [3:0]
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42 | PORT ETH_A_RGMII_TX_CTL_0_pin = ETH_A_RGMII_TX_CTL_0_pin, DIR = O
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43 | PORT ETH_A_RGMII_TXC_0_pin = ETH_A_RGMII_TXC_0_pin, DIR = O
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44 | PORT ETH_A_RGMII_RXD_0_pin = ETH_A_RGMII_RXD_0_pin, DIR = I, VEC = [3:0]
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45 | PORT ETH_A_RGMII_RX_CTL_0_pin = ETH_A_RGMII_RX_CTL_0_pin, DIR = I
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46 | PORT ETH_A_RGMII_RXC_0_pin = ETH_A_RGMII_RXC_0_pin, DIR = I
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47 | PORT ETH_A_MDC_0_pin = ETH_A_MDC_0_pin, DIR = O
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48 | PORT ETH_A_MDIO_0_pin = ETH_A_MDIO_0_pin, DIR = IO
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49 | # Eth A RGMII pins
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50 | PORT ETH_B_RGMII_TXD_0_pin = ETH_B_RGMII_TXD_0_pin, DIR = O, VEC = [3:0]
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51 | PORT ETH_B_RGMII_TX_CTL_0_pin = ETH_B_RGMII_TX_CTL_0_pin, DIR = O
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52 | PORT ETH_B_RGMII_TXC_0_pin = ETH_B_RGMII_TXC_0_pin, DIR = O
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53 | PORT ETH_B_RGMII_RXD_0_pin = ETH_B_RGMII_RXD_0_pin, DIR = I, VEC = [3:0]
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54 | PORT ETH_B_RGMII_RX_CTL_0_pin = ETH_B_RGMII_RX_CTL_0_pin, DIR = I
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55 | PORT ETH_B_RGMII_RXC_0_pin = ETH_B_RGMII_RXC_0_pin, DIR = I
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56 | PORT ETH_B_MDC_0_pin = ETH_B_MDC_0_pin, DIR = O
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57 | PORT ETH_B_MDIO_0_pin = ETH_B_MDIO_0_pin, DIR = IO
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58 | # DDR3 SO-DIMM slot pins
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59 | PORT DDR3_2GB_SODIMM_Clk_pin = DDR3_2GB_SODIMM_Clk_pin, DIR = O
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60 | PORT DDR3_2GB_SODIMM_Clk_n_pin = DDR3_2GB_SODIMM_Clk_n_pin, DIR = O
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61 | PORT DDR3_2GB_SODIMM_CE_pin = DDR3_2GB_SODIMM_CE_pin, DIR = O
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62 | PORT DDR3_2GB_SODIMM_CS_n_pin = DDR3_2GB_SODIMM_CS_n_pin, DIR = O
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63 | PORT DDR3_2GB_SODIMM_ODT_pin = DDR3_2GB_SODIMM_ODT_pin, DIR = O
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64 | PORT DDR3_2GB_SODIMM_RAS_n_pin = DDR3_2GB_SODIMM_RAS_n_pin, DIR = O
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65 | PORT DDR3_2GB_SODIMM_CAS_n_pin = DDR3_2GB_SODIMM_CAS_n_pin, DIR = O
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66 | PORT DDR3_2GB_SODIMM_WE_n_pin = DDR3_2GB_SODIMM_WE_n_pin, DIR = O
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67 | PORT DDR3_2GB_SODIMM_BankAddr_pin = DDR3_2GB_SODIMM_BankAddr_pin, DIR = O, VEC = [2:0]
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68 | PORT DDR3_2GB_SODIMM_Addr_pin = DDR3_2GB_SODIMM_Addr_pin, DIR = O, VEC = [14:0]
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69 | PORT DDR3_2GB_SODIMM_DQ_pin = DDR3_2GB_SODIMM_DQ_pin, DIR = IO, VEC = [31:0]
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70 | PORT DDR3_2GB_SODIMM_DM_pin = DDR3_2GB_SODIMM_DM_pin, DIR = O, VEC = [3:0]
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71 | PORT DDR3_2GB_SODIMM_Reset_n_pin = DDR3_2GB_SODIMM_Reset_n_pin, DIR = O
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72 | PORT DDR3_2GB_SODIMM_DQS_pin = DDR3_2GB_SODIMM_DQS_pin, DIR = IO, VEC = [3:0]
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73 | PORT DDR3_2GB_SODIMM_DQS_n_pin = DDR3_2GB_SODIMM_DQS_n_pin, DIR = IO, VEC = [3:0]
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74 | # RFA transceiver and front-end
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75 | PORT RFA_TxEn_pin = RFA_TxEn, DIR = O
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76 | PORT RFA_RxEn_pin = RFA_RxEn, DIR = O
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77 | PORT RFA_RxHP_pin = RFA_RxHP, DIR = O
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78 | PORT RFA_SHDN_pin = RFA_SHDN, DIR = O
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79 | PORT RFA_SPI_SCLK_pin = RFA_SPI_SCLK, DIR = O
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80 | PORT RFA_SPI_MOSI_pin = RFA_SPI_MOSI, DIR = O
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81 | PORT RFA_SPI_CSn_pin = RFA_SPI_CSn, DIR = O
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82 | PORT RFA_B_pin = RFA_B, DIR = O, VEC = [0:6]
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83 | PORT RFA_LD_pin = RFA_LD, DIR = I
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84 | PORT RFA_PAEn_24_pin = RFA_PAEn_24, DIR = O
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85 | PORT RFA_PAEn_5_pin = RFA_PAEn_5, DIR = O
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86 | PORT RFA_AntSw_pin = RFA_AntSw, DIR = O, VEC = [0:1]
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87 | # RFB transceiver and front-end
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88 | PORT RFB_TxEn_pin = RFB_TxEn, DIR = O
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89 | PORT RFB_RxEn_pin = RFB_RxEn, DIR = O
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90 | PORT RFB_RxHP_pin = RFB_RxHP, DIR = O
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91 | PORT RFB_SHDN_pin = RFB_SHDN, DIR = O
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92 | PORT RFB_SPI_SCLK_pin = RFB_SPI_SCLK, DIR = O
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93 | PORT RFB_SPI_MOSI_pin = RFB_SPI_MOSI, DIR = O
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94 | PORT RFB_SPI_CSn_pin = RFB_SPI_CSn, DIR = O
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95 | PORT RFB_B_pin = RFB_B, DIR = O, VEC = [0:6]
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96 | PORT RFB_LD_pin = RFB_LD, DIR = I
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97 | PORT RFB_PAEn_24_pin = RFB_PAEn_24, DIR = O
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98 | PORT RFB_PAEn_5_pin = RFB_PAEn_5, DIR = O
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99 | PORT RFB_AntSw_pin = RFB_AntSw, DIR = O, VEC = [0:1]
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100 | # RFC transceiver and front-end (FMC RFA)
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101 | PORT RFC_TxEn_pin = RFC_TxEn, DIR = O
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102 | PORT RFC_RxEn_pin = RFC_RxEn, DIR = O
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103 | PORT RFC_RxHP_pin = RFC_RxHP, DIR = O
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104 | PORT RFC_SHDN_pin = RFC_SHDN, DIR = O
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105 | PORT RFC_SPI_SCLK_pin = RFC_SPI_SCLK, DIR = O
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106 | PORT RFC_SPI_MOSI_pin = RFC_SPI_MOSI, DIR = O
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107 | PORT RFC_SPI_CSn_pin = RFC_SPI_CSn, DIR = O
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108 | PORT RFC_B_pin = RFC_B, DIR = O, VEC = [0:6]
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109 | PORT RFC_LD_pin = RFC_LD, DIR = I
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110 | PORT RFC_PAEn_24_pin = RFC_PAEn_24, DIR = O
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111 | PORT RFC_PAEn_5_pin = RFC_PAEn_5, DIR = O
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112 | PORT RFC_AntSw_pin = RFC_AntSw, DIR = O, VEC = [0:1]
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113 | # RFD transceiver and front-end (FMC RFB)
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114 | PORT RFD_TxEn_pin = RFD_TxEn, DIR = O
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115 | PORT RFD_RxEn_pin = RFD_RxEn, DIR = O
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116 | PORT RFD_RxHP_pin = RFD_RxHP, DIR = O
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117 | PORT RFD_SHDN_pin = RFD_SHDN, DIR = O
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118 | PORT RFD_SPI_SCLK_pin = RFD_SPI_SCLK, DIR = O
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119 | PORT RFD_SPI_MOSI_pin = RFD_SPI_MOSI, DIR = O
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120 | PORT RFD_SPI_CSn_pin = RFD_SPI_CSn, DIR = O
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121 | PORT RFD_B_pin = RFD_B, DIR = O, VEC = [0:6]
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122 | PORT RFD_LD_pin = RFD_LD, DIR = I
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123 | PORT RFD_PAEn_24_pin = RFD_PAEn_24, DIR = O
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124 | PORT RFD_PAEn_5_pin = RFD_PAEn_5, DIR = O
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125 | PORT RFD_AntSw_pin = RFD_AntSw, DIR = O, VEC = [0:1]
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126 | # RFA AD pins
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127 | PORT RFA_AD_TRXD = rfa_trxd, DIR = I, VEC = [11:0]
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128 | PORT RFA_AD_TRXCLK = rfa_trxclk, DIR = I
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129 | PORT RFA_AD_TRXIQ = rfa_trxiq, DIR = I
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130 | PORT RFA_AD_TXD = rfa_txd, DIR = O, VEC = [11:0]
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131 | PORT RFA_AD_TXIQ = rfa_txiq, DIR = O
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132 | PORT RFA_AD_TXCLK = rfa_txclk, DIR = O
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133 | # RFB AD pins
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134 | PORT RFB_AD_TRXD = rfb_trxd, DIR = I, VEC = [11:0]
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135 | PORT RFB_AD_TRXCLK = rfb_trxclk, DIR = I
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136 | PORT RFB_AD_TRXIQ = rfb_trxiq, DIR = I
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137 | PORT RFB_AD_TXD = rfb_txd, DIR = O, VEC = [11:0]
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138 | PORT RFB_AD_TXIQ = rfb_txiq, DIR = O
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139 | PORT RFB_AD_TXCLK = rfb_txclk, DIR = O
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140 | # RFC AD pins (FMC RFA)
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141 | PORT RFC_AD_TRXD = RFC_trxd, DIR = I, VEC = [11:0]
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142 | PORT RFC_AD_TRXCLK = RFC_trxclk, DIR = I
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143 | PORT RFC_AD_TRXIQ = RFC_trxiq, DIR = I
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144 | PORT RFC_AD_TXD = RFC_txd, DIR = O, VEC = [11:0]
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145 | PORT RFC_AD_TXIQ = RFC_txiq, DIR = O
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146 | PORT RFC_AD_TXCLK = RFC_txclk, DIR = O
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147 | # RFD AD pins (FMC RFB)
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148 | PORT RFD_AD_TRXD = RFD_trxd, DIR = I, VEC = [11:0]
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149 | PORT RFD_AD_TRXCLK = RFD_trxclk, DIR = I
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150 | PORT RFD_AD_TRXIQ = RFD_trxiq, DIR = I
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151 | PORT RFD_AD_TXD = RFD_txd, DIR = O, VEC = [11:0]
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152 | PORT RFD_AD_TXIQ = RFD_txiq, DIR = O
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153 | PORT RFD_AD_TXCLK = RFD_txclk, DIR = O
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154 | # On-board RSSI ADC pins
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155 | PORT RFA_RSSI_D = warplab_radio1_rssi_D, DIR = I, VEC = [9:0]
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156 | PORT RFB_RSSI_D = warplab_radio2_rssi_D, DIR = I, VEC = [9:0]
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157 | PORT RF_RSSI_CLK = warplab_rssi_clk, DIR = O
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158 | PORT RF_RSSI_PD = net_gnd, DIR = O
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159 | # FMC RSSI ADC pins
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160 | PORT RFC_RSSI_D = warplab_radio3_rssi_D, DIR = I, VEC = [9:0]
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161 | PORT RFD_RSSI_D = warplab_radio4_rssi_D, DIR = I, VEC = [9:0]
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162 | PORT FMC_RF_RSSI_CLK = warplab_rssi_clk, DIR = O
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163 | PORT FMC_RF_RSSI_PD = net_gnd, DIR = O
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164 | # AD9963 ADC/DAC control pins (RFA & RFB)
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165 | PORT RFA_AD_spi_cs_n_pin = RFA_AD_spi_cs_n, DIR = O
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166 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio, DIR = IO
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167 | PORT RFA_AD_spi_sclk_pin = RFA_AD_spi_sclk, DIR = O
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168 | PORT RFA_AD_reset_n_pin = RFA_AD_reset_n, DIR = O
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169 | PORT RFB_AD_spi_cs_n_pin = RFB_AD_spi_cs_n, DIR = O
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170 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio, DIR = IO
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171 | PORT RFB_AD_spi_sclk_pin = RFB_AD_spi_sclk, DIR = O
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172 | PORT RFB_AD_reset_n_pin = RFB_AD_reset_n, DIR = O
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173 | # AD9963 ADC/DAC control pins (RFC & RFD = FMC RFA & RFB))
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174 | PORT RFC_AD_spi_cs_n_pin = RFC_AD_spi_cs_n, DIR = O
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175 | PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio, DIR = IO
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176 | PORT RFC_AD_spi_sclk_pin = RFC_AD_spi_sclk, DIR = O
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177 | PORT RFC_AD_reset_n_pin = RFC_AD_reset_n, DIR = O
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178 | PORT RFD_AD_spi_cs_n_pin = RFD_AD_spi_cs_n, DIR = O
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179 | PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio, DIR = IO
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180 | PORT RFD_AD_spi_sclk_pin = RFD_AD_spi_sclk, DIR = O
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181 | PORT RFD_AD_reset_n_pin = RFD_AD_reset_n, DIR = O
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182 | # FMC user LEDs (tied directly to radio_controller, not w3_uesrio)
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183 | PORT RFC_led_g = RFC_led_g, DIR = O
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184 | PORT RFC_led_r = RFC_led_r, DIR = O
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185 | PORT RFD_led_g = RFD_led_g, DIR = O
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186 | PORT RFD_led_r = RFD_led_r, DIR = O
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187 | # AD9512 clock buffer control pins (RF reference & sampling clocks)
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188 | PORT clk_rfref_spi_cs_n_pin = clk_rfref_spi_cs_n, DIR = O
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189 | PORT clk_rfref_spi_mosi_pin = clk_rfref_spi_mosi, DIR = O
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190 | PORT clk_rfref_spi_sclk_pin = clk_rfref_spi_sclk, DIR = O
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191 | PORT clk_rfref_spi_miso_pin = clk_rfref_spi_miso, DIR = I
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192 | PORT clk_rfref_func_pin = net_vcc, DIR = O
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193 | PORT clk_samp_spi_cs_n_pin = clk_samp_spi_cs_n, DIR = O
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194 | PORT clk_samp_spi_mosi_pin = clk_samp_spi_mosi, DIR = O
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195 | PORT clk_samp_spi_sclk_pin = clk_samp_spi_sclk, DIR = O
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196 | PORT clk_samp_spi_miso_pin = clk_samp_spi_miso, DIR = I
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197 | PORT clk_samp_func_pin = net_vcc, DIR = O
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198 | # 80MHz sampling clock from AD9512
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199 | PORT samp_clk_p_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 80000000
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200 | PORT samp_clk_n_pin = ad_refclk_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 80000000
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201 | # 200MHz LVDS oscillator input
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202 | PORT osc200_p_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = P, SIGIS = CLK, CLK_FREQ = 200000000
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203 | PORT osc200_n_pin = osc200_in, DIR = I, DIFFERENTIAL_POLARITY = N, SIGIS = CLK, CLK_FREQ = 200000000
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204 | # System reset, tied to RESET push button
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205 | PORT rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
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206 | PORT debug_status = warplab_mimo_4x4_plbw_0_debug_capturing & warplab_mimo_4x4_plbw_0_debug_transmitting, DIR = O, VEC = [1:0]
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207 | # Switches on CM-MMCX for clock src selection (ok if CM-MMCX is not installed)
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208 | PORT cm_mmcx_sw = cm_mmcx_sw, DIR = I, VEC = [0:1]
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209 | PORT debug_sw_gpio = debug_sw_gpio, DIR = O, VEC = [5:0]
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210 |
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211 |
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212 | BEGIN microblaze
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213 | PARAMETER INSTANCE = microblaze_0
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214 | PARAMETER C_USE_BARREL = 1
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215 | PARAMETER C_DEBUG_ENABLED = 1
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216 | PARAMETER HW_VER = 8.20.b
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217 | PARAMETER C_UNALIGNED_EXCEPTIONS = 1
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218 | BUS_INTERFACE DPLB = plb_primary
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219 | BUS_INTERFACE IPLB = plb_primary
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220 | BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
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221 | BUS_INTERFACE DLMB = dlmb
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222 | BUS_INTERFACE ILMB = ilmb
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223 | PORT MB_RESET = mb_reset
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224 | END
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225 |
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226 | BEGIN plb_v46
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227 | PARAMETER INSTANCE = plb_primary
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228 | PARAMETER HW_VER = 1.05.a
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229 | PORT PLB_Clk = clk_160MHz
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230 | PORT SYS_Rst = sys_bus_reset
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231 | END
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232 |
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233 | BEGIN lmb_v10
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234 | PARAMETER INSTANCE = ilmb
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235 | PARAMETER HW_VER = 2.00.b
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236 | PORT LMB_Clk = clk_160MHz
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237 | PORT SYS_Rst = sys_bus_reset
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238 | END
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239 |
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240 | BEGIN lmb_v10
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241 | PARAMETER INSTANCE = dlmb
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242 | PARAMETER HW_VER = 2.00.b
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243 | PORT LMB_Clk = clk_160MHz
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244 | PORT SYS_Rst = sys_bus_reset
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245 | END
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246 |
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247 | BEGIN lmb_bram_if_cntlr
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248 | PARAMETER INSTANCE = dlmb_cntlr
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249 | PARAMETER HW_VER = 3.00.b
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250 | PARAMETER C_BASEADDR = 0x00000000
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251 | PARAMETER C_HIGHADDR = 0x0000ffff
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252 | BUS_INTERFACE SLMB = dlmb
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253 | BUS_INTERFACE BRAM_PORT = dlmb_port
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254 | END
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255 |
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256 | BEGIN lmb_bram_if_cntlr
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257 | PARAMETER INSTANCE = ilmb_cntlr
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258 | PARAMETER HW_VER = 3.00.b
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259 | PARAMETER C_BASEADDR = 0x00000000
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260 | PARAMETER C_HIGHADDR = 0x0000ffff
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261 | BUS_INTERFACE SLMB = ilmb
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262 | BUS_INTERFACE BRAM_PORT = ilmb_port
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263 | END
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264 |
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265 | BEGIN bram_block
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---|
266 | PARAMETER INSTANCE = lmb_bram
|
---|
267 | PARAMETER HW_VER = 1.00.a
|
---|
268 | BUS_INTERFACE PORTA = ilmb_port
|
---|
269 | BUS_INTERFACE PORTB = dlmb_port
|
---|
270 | END
|
---|
271 |
|
---|
272 | BEGIN w3_userio
|
---|
273 | PARAMETER INSTANCE = w3_userio_0
|
---|
274 | PARAMETER HW_VER = 1.00.a
|
---|
275 | PARAMETER C_BASEADDR = 0xc09c0000
|
---|
276 | PARAMETER C_HIGHADDR = 0xc09cffff
|
---|
277 | BUS_INTERFACE SPLB = plb_primary
|
---|
278 | PORT hexdisp_left = USERIO_hexdisp_left_pin
|
---|
279 | PORT hexdisp_right = USERIO_hexdisp_right_pin
|
---|
280 | PORT hexdisp_left_dp = USERIO_hexdisp_left_dp_pin
|
---|
281 | PORT hexdisp_right_dp = USERIO_hexdisp_right_dp_pin
|
---|
282 | PORT leds_red = USERIO_leds_red_pin
|
---|
283 | PORT leds_green = USERIO_leds_green_pin
|
---|
284 | PORT rfa_led_red = USERIO_rfa_led_red_pin
|
---|
285 | PORT rfa_led_green = USERIO_rfa_led_green_pin
|
---|
286 | PORT rfb_led_red = USERIO_rfb_led_red_pin
|
---|
287 | PORT rfb_led_green = USERIO_rfb_led_green_pin
|
---|
288 | PORT dipsw = USERIO_dipsw_pin
|
---|
289 | PORT pb_u = USERIO_pb_u_pin
|
---|
290 | PORT pb_m = USERIO_pb_m_pin
|
---|
291 | PORT pb_d = USERIO_pb_d_pin
|
---|
292 | PORT usr_rfa_led_red = RFA_statLED_Rx
|
---|
293 | PORT usr_rfa_led_green = RFA_statLED_Tx
|
---|
294 | PORT usr_rfb_led_red = RFB_statLED_Rx
|
---|
295 | PORT usr_rfb_led_green = RFB_statLED_Tx
|
---|
296 | PORT DNA_Port_Clk = clk_40MHz
|
---|
297 | END
|
---|
298 |
|
---|
299 | BEGIN w3_iic_eeprom
|
---|
300 | PARAMETER INSTANCE = w3_iic_eeprom_onBoard
|
---|
301 | PARAMETER HW_VER = 1.00.b
|
---|
302 | PARAMETER C_BASEADDR = 0xc08d0000
|
---|
303 | PARAMETER C_HIGHADDR = 0xc08dffff
|
---|
304 | BUS_INTERFACE SPLB = plb_primary
|
---|
305 | PORT iic_scl = IIC_EEPROM_iic_scl_pin
|
---|
306 | PORT iic_sda = IIC_EEPROM_iic_sda_pin
|
---|
307 | END
|
---|
308 |
|
---|
309 | BEGIN w3_iic_eeprom
|
---|
310 | PARAMETER INSTANCE = w3_iic_eeprom_FMC
|
---|
311 | PARAMETER HW_VER = 1.00.b
|
---|
312 | PARAMETER C_BASEADDR = 0xc0ab0000
|
---|
313 | PARAMETER C_HIGHADDR = 0xc0abffff
|
---|
314 | BUS_INTERFACE SPLB = plb_primary
|
---|
315 | PORT iic_scl = FMC_IIC_EEPROM_scl_pin
|
---|
316 | PORT iic_sda = FMC_IIC_EEPROM_sda_pin
|
---|
317 | END
|
---|
318 |
|
---|
319 | BEGIN xps_uartlite
|
---|
320 | PARAMETER INSTANCE = UART_USB
|
---|
321 | PARAMETER C_BAUDRATE = 57600
|
---|
322 | PARAMETER C_DATA_BITS = 8
|
---|
323 | PARAMETER C_USE_PARITY = 0
|
---|
324 | PARAMETER C_ODD_PARITY = 0
|
---|
325 | PARAMETER HW_VER = 1.02.a
|
---|
326 | PARAMETER C_BASEADDR = 0xc0be0000
|
---|
327 | PARAMETER C_HIGHADDR = 0xc0beffff
|
---|
328 | BUS_INTERFACE SPLB = plb_primary
|
---|
329 | PORT RX = UART_USB_RX_pin
|
---|
330 | PORT TX = UART_USB_TX_pin
|
---|
331 | END
|
---|
332 |
|
---|
333 | BEGIN xps_ll_temac
|
---|
334 | PARAMETER INSTANCE = ETH_A
|
---|
335 | PARAMETER C_NUM_IDELAYCTRL = 1
|
---|
336 | PARAMETER C_IDELAYCTRL_LOC = IDELAYCTRL_X2Y2
|
---|
337 | PARAMETER C_PHY_TYPE = 3
|
---|
338 | PARAMETER C_TEMAC1_ENABLED = 0
|
---|
339 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
340 | PARAMETER C_TEMAC_TYPE = 3
|
---|
341 | PARAMETER C_TEMAC0_PHYADDR = 0b00001
|
---|
342 | PARAMETER HW_VER = 2.03.a
|
---|
343 | PARAMETER C_BASEADDR = 0xc0a00000
|
---|
344 | PARAMETER C_HIGHADDR = 0xc0a7ffff
|
---|
345 | BUS_INTERFACE SPLB = plb_primary
|
---|
346 | BUS_INTERFACE LLINK0 = ETH_A_llink0
|
---|
347 | PORT TemacPhy_RST_n = ETH_A_TemacPhy_RST_n_pin
|
---|
348 | PORT GTX_CLK_0 = clk_125MHz
|
---|
349 | PORT REFCLK = clk_200MHz
|
---|
350 | PORT LlinkTemac0_CLK = clk_160MHz
|
---|
351 | PORT RGMII_TXD_0 = ETH_A_RGMII_TXD_0_pin
|
---|
352 | PORT RGMII_TX_CTL_0 = ETH_A_RGMII_TX_CTL_0_pin
|
---|
353 | PORT RGMII_TXC_0 = ETH_A_RGMII_TXC_0_pin
|
---|
354 | PORT RGMII_RXD_0 = ETH_A_RGMII_RXD_0_pin
|
---|
355 | PORT RGMII_RX_CTL_0 = ETH_A_RGMII_RX_CTL_0_pin
|
---|
356 | PORT RGMII_RXC_0 = ETH_A_RGMII_RXC_0_pin
|
---|
357 | PORT MDC_0 = ETH_A_MDC_0_pin
|
---|
358 | PORT MDIO_0 = ETH_A_MDIO_0_pin
|
---|
359 | END
|
---|
360 |
|
---|
361 | BEGIN xps_ll_temac
|
---|
362 | PARAMETER INSTANCE = ETH_B
|
---|
363 | PARAMETER C_NUM_IDELAYCTRL = 0
|
---|
364 | PARAMETER C_PHY_TYPE = 3
|
---|
365 | PARAMETER C_TEMAC1_ENABLED = 0
|
---|
366 | PARAMETER C_BUS2CORE_CLK_RATIO = 1
|
---|
367 | PARAMETER C_TEMAC_TYPE = 3
|
---|
368 | PARAMETER C_TEMAC0_PHYADDR = 0b00001
|
---|
369 | PARAMETER HW_VER = 2.03.a
|
---|
370 | PARAMETER C_BASEADDR = 0xc0900000
|
---|
371 | PARAMETER C_HIGHADDR = 0xc097ffff
|
---|
372 | BUS_INTERFACE SPLB = plb_primary
|
---|
373 | BUS_INTERFACE LLINK0 = ETH_B_llink0
|
---|
374 | PORT GTX_CLK_0 = clk_125MHz
|
---|
375 | PORT REFCLK = clk_200MHz
|
---|
376 | PORT LlinkTemac0_CLK = clk_160MHz
|
---|
377 | PORT RGMII_TXD_0 = ETH_B_RGMII_TXD_0_pin
|
---|
378 | PORT RGMII_TX_CTL_0 = ETH_B_RGMII_TX_CTL_0_pin
|
---|
379 | PORT RGMII_TXC_0 = ETH_B_RGMII_TXC_0_pin
|
---|
380 | PORT RGMII_RXD_0 = ETH_B_RGMII_RXD_0_pin
|
---|
381 | PORT RGMII_RX_CTL_0 = ETH_B_RGMII_RX_CTL_0_pin
|
---|
382 | PORT RGMII_RXC_0 = ETH_B_RGMII_RXC_0_pin
|
---|
383 | PORT MDC_0 = ETH_B_MDC_0_pin
|
---|
384 | PORT MDIO_0 = ETH_B_MDIO_0_pin
|
---|
385 | END
|
---|
386 |
|
---|
387 | BEGIN mpmc
|
---|
388 | PARAMETER INSTANCE = DDR3_2GB_SODIMM
|
---|
389 | PARAMETER C_NUM_PORTS = 1
|
---|
390 | PARAMETER C_MEM_TYPE = DDR3
|
---|
391 | PARAMETER C_MEM_PARTNO = MT8JSF25664HZ-1G4
|
---|
392 | PARAMETER C_MEM_ODT_TYPE = 1
|
---|
393 | PARAMETER C_MEM_REG_DIMM = 0
|
---|
394 | PARAMETER C_MEM_CLK_WIDTH = 1
|
---|
395 | PARAMETER C_MEM_ODT_WIDTH = 1
|
---|
396 | PARAMETER C_MEM_CE_WIDTH = 1
|
---|
397 | PARAMETER C_MEM_CS_N_WIDTH = 1
|
---|
398 | PARAMETER C_MEM_DATA_WIDTH = 32
|
---|
399 | PARAMETER C_MEM_NDQS_COL0 = 4
|
---|
400 | PARAMETER C_MEM_DQS_LOC_COL0 = 0x000000000000000000000000000003020100
|
---|
401 | PARAMETER C_PIM0_BASETYPE = 2
|
---|
402 | PARAMETER HW_VER = 6.05.a
|
---|
403 | PARAMETER C_FAMILY = virtex6
|
---|
404 | PARAMETER C_MPMC_BASEADDR = 0x40000000
|
---|
405 | PARAMETER C_MPMC_HIGHADDR = 0x7fffffff
|
---|
406 | BUS_INTERFACE SPLB0 = plb_primary
|
---|
407 | PORT MPMC_Clk0 = clk_160MHz
|
---|
408 | PORT MPMC_Clk_200MHz = clk_200MHz
|
---|
409 | PORT MPMC_Rst = sys_periph_reset
|
---|
410 | PORT MPMC_Clk_Mem = clk_320MHz
|
---|
411 | PORT MPMC_Clk_Rd_Base = clk_320MHz_nobuf_varphase
|
---|
412 | PORT MPMC_DCM_PSEN = MPMC_DCM_PSEN
|
---|
413 | PORT MPMC_DCM_PSINCDEC = MPMC_DCM_PSINCDEC
|
---|
414 | PORT MPMC_DCM_PSDONE = MPMC_DCM_PSDONE
|
---|
415 | PORT DDR3_Clk = DDR3_2GB_SODIMM_Clk_pin
|
---|
416 | PORT DDR3_Clk_n = DDR3_2GB_SODIMM_Clk_n_pin
|
---|
417 | PORT DDR3_CE = DDR3_2GB_SODIMM_CE_pin
|
---|
418 | PORT DDR3_CS_n = DDR3_2GB_SODIMM_CS_n_pin
|
---|
419 | PORT DDR3_ODT = DDR3_2GB_SODIMM_ODT_pin
|
---|
420 | PORT DDR3_RAS_n = DDR3_2GB_SODIMM_RAS_n_pin
|
---|
421 | PORT DDR3_CAS_n = DDR3_2GB_SODIMM_CAS_n_pin
|
---|
422 | PORT DDR3_WE_n = DDR3_2GB_SODIMM_WE_n_pin
|
---|
423 | PORT DDR3_BankAddr = DDR3_2GB_SODIMM_BankAddr_pin
|
---|
424 | PORT DDR3_Addr = DDR3_2GB_SODIMM_Addr_pin
|
---|
425 | PORT DDR3_DQ = DDR3_2GB_SODIMM_DQ_pin
|
---|
426 | PORT DDR3_DM = DDR3_2GB_SODIMM_DM_pin
|
---|
427 | PORT DDR3_Reset_n = DDR3_2GB_SODIMM_Reset_n_pin
|
---|
428 | PORT DDR3_DQS = DDR3_2GB_SODIMM_DQS_pin
|
---|
429 | PORT DDR3_DQS_n = DDR3_2GB_SODIMM_DQS_n_pin
|
---|
430 | END
|
---|
431 |
|
---|
432 | BEGIN xps_ll_fifo
|
---|
433 | PARAMETER INSTANCE = ETH_A_fifo
|
---|
434 | PARAMETER HW_VER = 1.02.a
|
---|
435 | PARAMETER C_BASEADDR = 0xc0870000
|
---|
436 | PARAMETER C_HIGHADDR = 0xc087ffff
|
---|
437 | BUS_INTERFACE SPLB = plb_primary
|
---|
438 | BUS_INTERFACE LLINK = ETH_A_llink0
|
---|
439 | END
|
---|
440 |
|
---|
441 | BEGIN xps_ll_fifo
|
---|
442 | PARAMETER INSTANCE = ETH_B_fifo
|
---|
443 | PARAMETER HW_VER = 1.02.a
|
---|
444 | PARAMETER C_BASEADDR = 0xc0b80000
|
---|
445 | PARAMETER C_HIGHADDR = 0xc0b8ffff
|
---|
446 | BUS_INTERFACE SPLB = plb_primary
|
---|
447 | BUS_INTERFACE LLINK = ETH_B_llink0
|
---|
448 | END
|
---|
449 |
|
---|
450 | BEGIN clock_generator
|
---|
451 | PARAMETER INSTANCE = clock_generator_ProcBusSamp_Clocks
|
---|
452 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
453 | PARAMETER HW_VER = 4.03.a
|
---|
454 | # 80MHz clock input (driven by AD9512 for sampling clock)
|
---|
455 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
456 | # 2x Sampling clock 0 deg phase
|
---|
457 | PARAMETER C_CLKOUT0_FREQ = 80000000
|
---|
458 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
459 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
460 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
461 | # MB and primary PLB
|
---|
462 | PARAMETER C_CLKOUT1_FREQ = 160000000
|
---|
463 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
464 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
465 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
466 | # Sampling clock 0 deg phase
|
---|
467 | PARAMETER C_CLKOUT2_FREQ = 40000000
|
---|
468 | PARAMETER C_CLKOUT2_PHASE = 0
|
---|
469 | PARAMETER C_CLKOUT2_GROUP = MMCM0
|
---|
470 | PARAMETER C_CLKOUT2_BUF = TRUE
|
---|
471 | # Sampling clock 90 deg phase
|
---|
472 | PARAMETER C_CLKOUT3_FREQ = 40000000
|
---|
473 | PARAMETER C_CLKOUT3_PHASE = 90
|
---|
474 | PARAMETER C_CLKOUT3_BUF = TRUE
|
---|
475 | PARAMETER C_CLKOUT3_GROUP = MMCM0
|
---|
476 | PORT CLKIN = ad_refclk_in
|
---|
477 | PORT CLKOUT0 = clk_80MHz
|
---|
478 | PORT CLKOUT1 = clk_160MHz
|
---|
479 | PORT CLKOUT2 = clk_40MHz
|
---|
480 | PORT CLKOUT3 = clk_40MHz_90degphase
|
---|
481 | PORT RST = mmcm_inputs_invalid
|
---|
482 | PORT LOCKED = clk_gen_0_locked
|
---|
483 | END
|
---|
484 |
|
---|
485 | BEGIN clock_generator
|
---|
486 | PARAMETER INSTANCE = clock_generator_asyncClks
|
---|
487 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
488 | PARAMETER HW_VER = 4.03.a
|
---|
489 | # 200MHz clock input (driven by 200MHz LVDS oscillator)
|
---|
490 | PARAMETER C_CLKIN_FREQ = 200000000
|
---|
491 | # TEMAC TxClk
|
---|
492 | PARAMETER C_CLKOUT0_FREQ = 125000000
|
---|
493 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
494 | PARAMETER C_CLKOUT0_GROUP = NONE
|
---|
495 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
496 | # IDELAYCTRL refclk
|
---|
497 | PARAMETER C_CLKOUT1_FREQ = 200000000
|
---|
498 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
499 | PARAMETER C_CLKOUT1_GROUP = NONE
|
---|
500 | PARAMETER C_CLKOUT1_BUF = TRUE
|
---|
501 | PORT CLKIN = osc200_in
|
---|
502 | PORT CLKOUT0 = clk_125MHz
|
---|
503 | PORT CLKOUT1 = clk_200MHz
|
---|
504 | PORT RST = sys_rst_s
|
---|
505 | PORT LOCKED = clk_gen_1_locked
|
---|
506 | END
|
---|
507 |
|
---|
508 | BEGIN clock_generator
|
---|
509 | PARAMETER INSTANCE = clock_generator_MPMC_Clocks
|
---|
510 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
511 | PARAMETER HW_VER = 4.03.a
|
---|
512 | # 80MHz clock input (driven by other clock generator)
|
---|
513 | PARAMETER C_CLKIN_FREQ = 80000000
|
---|
514 | # MPMC DRAM clock (2x bus)
|
---|
515 | PARAMETER C_CLKOUT0_FREQ = 320000000
|
---|
516 | PARAMETER C_CLKOUT0_PHASE = 0
|
---|
517 | PARAMETER C_CLKOUT0_GROUP = MMCM0
|
---|
518 | PARAMETER C_CLKOUT0_BUF = TRUE
|
---|
519 | # MPMC DRAM clock (2x bus, variable phase)
|
---|
520 | PARAMETER C_CLKOUT1_FREQ = 320000000
|
---|
521 | PARAMETER C_CLKOUT1_PHASE = 0
|
---|
522 | PARAMETER C_CLKOUT1_GROUP = MMCM0
|
---|
523 | PARAMETER C_CLKOUT1_BUF = FALSE
|
---|
524 | PARAMETER C_CLKOUT1_VARIABLE_PHASE = TRUE
|
---|
525 | PARAMETER C_PSDONE_GROUP = MMCM0
|
---|
526 | PORT CLKIN = clk_80MHz
|
---|
527 | PORT CLKOUT0 = clk_320MHz
|
---|
528 | PORT CLKOUT1 = clk_320MHz_nobuf_varphase
|
---|
529 | PORT PSCLK = clk_80MHz
|
---|
530 | PORT PSEN = MPMC_DCM_PSEN
|
---|
531 | PORT PSINCDEC = MPMC_DCM_PSINCDEC
|
---|
532 | PORT PSDONE = MPMC_DCM_PSDONE
|
---|
533 | PORT RST = mmcm_inputs_invalid
|
---|
534 | PORT LOCKED = clk_gen_2_locked
|
---|
535 | END
|
---|
536 |
|
---|
537 | BEGIN mdm
|
---|
538 | PARAMETER INSTANCE = mdm_0
|
---|
539 | PARAMETER C_MB_DBG_PORTS = 1
|
---|
540 | PARAMETER C_USE_UART = 1
|
---|
541 | PARAMETER HW_VER = 2.00.b
|
---|
542 | PARAMETER C_BASEADDR = 0xc09a0000
|
---|
543 | PARAMETER C_HIGHADDR = 0xc09affff
|
---|
544 | BUS_INTERFACE SPLB = plb_primary
|
---|
545 | BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
|
---|
546 | PORT Debug_SYS_Rst = Debug_SYS_Rst
|
---|
547 | END
|
---|
548 |
|
---|
549 | BEGIN proc_sys_reset
|
---|
550 | PARAMETER INSTANCE = proc_sys_reset_0
|
---|
551 | PARAMETER C_EXT_RESET_HIGH = 1
|
---|
552 | PARAMETER HW_VER = 3.00.a
|
---|
553 | PORT Slowest_sync_clk = clk_40MHz
|
---|
554 | PORT Ext_Reset_In = sys_rst_s
|
---|
555 | PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
|
---|
556 | PORT Dcm_locked = clk_gen_all_locked
|
---|
557 | PORT MB_Reset = mb_reset
|
---|
558 | PORT Bus_Struct_Reset = sys_bus_reset
|
---|
559 | PORT Peripheral_Reset = sys_periph_reset
|
---|
560 | END
|
---|
561 |
|
---|
562 | BEGIN util_reduced_logic
|
---|
563 | PARAMETER INSTANCE = clk_gen_locked_AND
|
---|
564 | PARAMETER HW_VER = 1.00.a
|
---|
565 | PARAMETER C_OPERATION = AND
|
---|
566 | PARAMETER C_SIZE = 3
|
---|
567 | PORT Op1 = clk_gen_0_locked & clk_gen_1_locked & clk_gen_2_locked
|
---|
568 | PORT Res = clk_gen_all_locked
|
---|
569 | END
|
---|
570 |
|
---|
571 | BEGIN bram_block
|
---|
572 | PARAMETER INSTANCE = bram_block_0
|
---|
573 | PARAMETER HW_VER = 1.00.a
|
---|
574 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
|
---|
575 | END
|
---|
576 |
|
---|
577 | BEGIN xps_bram_if_cntlr
|
---|
578 | PARAMETER INSTANCE = xps_bram_if_cntlr_0
|
---|
579 | PARAMETER HW_VER = 1.00.b
|
---|
580 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32
|
---|
581 | PARAMETER C_BASEADDR = 0xc0b40000
|
---|
582 | PARAMETER C_HIGHADDR = 0xc0b5ffff
|
---|
583 | BUS_INTERFACE SPLB = plb_primary
|
---|
584 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
|
---|
585 | END
|
---|
586 |
|
---|
587 | BEGIN bram_block
|
---|
588 | PARAMETER INSTANCE = bram_block_1
|
---|
589 | PARAMETER HW_VER = 1.00.a
|
---|
590 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
|
---|
591 | END
|
---|
592 |
|
---|
593 | BEGIN xps_bram_if_cntlr
|
---|
594 | PARAMETER INSTANCE = xps_bram_if_cntlr_1
|
---|
595 | PARAMETER HW_VER = 1.00.b
|
---|
596 | PARAMETER C_SPLB_NATIVE_DWIDTH = 32
|
---|
597 | PARAMETER C_BASEADDR = 0xc0840000
|
---|
598 | PARAMETER C_HIGHADDR = 0xc084ffff
|
---|
599 | BUS_INTERFACE SPLB = plb_primary
|
---|
600 | BUS_INTERFACE PORTA = xps_bram_if_cntlr_1_PORTA
|
---|
601 | END
|
---|
602 |
|
---|
603 | BEGIN xps_timer
|
---|
604 | PARAMETER INSTANCE = xps_timer_0
|
---|
605 | PARAMETER HW_VER = 1.02.a
|
---|
606 | PARAMETER C_BASEADDR = 0x80a00000
|
---|
607 | PARAMETER C_HIGHADDR = 0x80a0ffff
|
---|
608 | BUS_INTERFACE SPLB = plb_secondary_80MHz
|
---|
609 | END
|
---|
610 |
|
---|
611 | # ###############
|
---|
612 | # WARP pcores
|
---|
613 | # ###############
|
---|
614 | BEGIN w3_clock_controller |
---|
615 | PARAMETER INSTANCE = w3_clock_controller_0 |
---|
616 | PARAMETER HW_VER = 3.01.b |
---|
617 | PARAMETER C_BASEADDR = 0xc0400000 |
---|
618 | PARAMETER C_HIGHADDR = 0xc040ffff |
---|
619 | BUS_INTERFACE SPLB = plb_primary |
---|
620 | PORT rfref_spi_cs_n = clk_rfref_spi_cs_n |
---|
621 | PORT samp_spi_cs_n = clk_samp_spi_cs_n |
---|
622 | PORT samp_spi_mosi = clk_samp_spi_mosi |
---|
623 | PORT rfref_spi_mosi = clk_rfref_spi_mosi |
---|
624 | PORT samp_spi_sclk = clk_samp_spi_sclk |
---|
625 | PORT rfref_spi_sclk = clk_rfref_spi_sclk |
---|
626 | PORT samp_spi_miso = clk_samp_spi_miso |
---|
627 | PORT rfref_spi_miso = clk_rfref_spi_miso |
---|
628 | PORT usr_status = net_gnd |
---|
629 | PORT at_boot_clk_in = clk_200MHz |
---|
630 | PORT at_boot_clk_in_valid = clk_gen_1_locked |
---|
631 | PORT at_boot_config_sw = cm_mmcx_sw |
---|
632 | PORT at_boot_clkbuf_clocks_invalid = mmcm_inputs_invalid |
---|
633 | END
|
---|
634 |
|
---|
635 | BEGIN w3_ad_controller
|
---|
636 | PARAMETER INSTANCE = w3_ad_controller_0
|
---|
637 | PARAMETER HW_VER = 3.01.a
|
---|
638 | PARAMETER C_BASEADDR = 0xc0b90000
|
---|
639 | PARAMETER C_HIGHADDR = 0xc0b9ffff
|
---|
640 | BUS_INTERFACE SPLB = plb_primary
|
---|
641 | PORT RFA_AD_spi_sdio = RFA_AD_spi_sdio
|
---|
642 | PORT RFA_AD_spi_sclk = RFA_AD_spi_sclk
|
---|
643 | PORT RFA_AD_spi_cs_n = RFA_AD_spi_cs_n
|
---|
644 | PORT RFA_AD_reset_n = RFA_AD_reset_n
|
---|
645 | PORT RFB_AD_spi_sdio = RFB_AD_spi_sdio
|
---|
646 | PORT RFB_AD_spi_sclk = RFB_AD_spi_sclk
|
---|
647 | PORT RFB_AD_spi_cs_n = RFB_AD_spi_cs_n
|
---|
648 | PORT RFB_AD_reset_n = RFB_AD_reset_n
|
---|
649 | PORT RFC_AD_spi_sdio = RFC_AD_spi_sdio
|
---|
650 | PORT RFC_AD_spi_sclk = RFC_AD_spi_sclk
|
---|
651 | PORT RFC_AD_spi_cs_n = RFC_AD_spi_cs_n
|
---|
652 | PORT RFC_AD_reset_n = RFC_AD_reset_n
|
---|
653 | PORT RFD_AD_spi_sdio = RFD_AD_spi_sdio
|
---|
654 | PORT RFD_AD_spi_sclk = RFD_AD_spi_sclk
|
---|
655 | PORT RFD_AD_spi_cs_n = RFD_AD_spi_cs_n
|
---|
656 | PORT RFD_AD_reset_n = RFD_AD_reset_n
|
---|
657 | END
|
---|
658 |
|
---|
659 | BEGIN radio_controller
|
---|
660 | PARAMETER INSTANCE = radio_controller_0
|
---|
661 | PARAMETER HW_VER = 3.00.c
|
---|
662 | PARAMETER C_BASEADDR = 0xc0820000
|
---|
663 | PARAMETER C_HIGHADDR = 0xc082ffff
|
---|
664 | BUS_INTERFACE SPLB = plb_primary
|
---|
665 | PORT RFA_TxEn = RFA_TxEn
|
---|
666 | PORT RFA_RxEn = RFA_RxEn
|
---|
667 | PORT RFA_RxHP = RFA_RxHP
|
---|
668 | PORT RFA_SHDN = RFA_SHDN
|
---|
669 | PORT RFA_SPI_SCLK = RFA_SPI_SCLK
|
---|
670 | PORT RFA_SPI_MOSI = RFA_SPI_MOSI
|
---|
671 | PORT RFA_SPI_CSn = RFA_SPI_CSn
|
---|
672 | PORT RFA_B = RFA_B
|
---|
673 | PORT RFA_LD = RFA_LD
|
---|
674 | PORT RFA_PAEn_24 = RFA_PAEn_24
|
---|
675 | PORT RFA_PAEn_5 = RFA_PAEn_5
|
---|
676 | PORT RFA_AntSw = RFA_AntSw
|
---|
677 | PORT RFB_TxEn = RFB_TxEn
|
---|
678 | PORT RFB_RxEn = RFB_RxEn
|
---|
679 | PORT RFB_RxHP = RFB_RxHP
|
---|
680 | PORT RFB_SHDN = RFB_SHDN
|
---|
681 | PORT RFB_SPI_SCLK = RFB_SPI_SCLK
|
---|
682 | PORT RFB_SPI_MOSI = RFB_SPI_MOSI
|
---|
683 | PORT RFB_SPI_CSn = RFB_SPI_CSn
|
---|
684 | PORT RFB_B = RFB_B
|
---|
685 | PORT RFB_LD = RFB_LD
|
---|
686 | PORT RFB_PAEn_24 = RFB_PAEn_24
|
---|
687 | PORT RFB_PAEn_5 = RFB_PAEn_5
|
---|
688 | PORT RFB_AntSw = RFB_AntSw
|
---|
689 | PORT RFC_TxEn = RFC_TxEn
|
---|
690 | PORT RFC_RxEn = RFC_RxEn
|
---|
691 | PORT RFC_RxHP = RFC_RxHP
|
---|
692 | PORT RFC_SHDN = RFC_SHDN
|
---|
693 | PORT RFC_SPI_SCLK = RFC_SPI_SCLK
|
---|
694 | PORT RFC_SPI_MOSI = RFC_SPI_MOSI
|
---|
695 | PORT RFC_SPI_CSn = RFC_SPI_CSn
|
---|
696 | PORT RFC_B = RFC_B
|
---|
697 | PORT RFC_LD = RFC_LD
|
---|
698 | PORT RFC_PAEn_24 = RFC_PAEn_24
|
---|
699 | PORT RFC_PAEn_5 = RFC_PAEn_5
|
---|
700 | PORT RFC_AntSw = RFC_AntSw
|
---|
701 | PORT RFD_TxEn = RFD_TxEn
|
---|
702 | PORT RFD_RxEn = RFD_RxEn
|
---|
703 | PORT RFD_RxHP = RFD_RxHP
|
---|
704 | PORT RFD_SHDN = RFD_SHDN
|
---|
705 | PORT RFD_SPI_SCLK = RFD_SPI_SCLK
|
---|
706 | PORT RFD_SPI_MOSI = RFD_SPI_MOSI
|
---|
707 | PORT RFD_SPI_CSn = RFD_SPI_CSn
|
---|
708 | PORT RFD_B = RFD_B
|
---|
709 | PORT RFD_LD = RFD_LD
|
---|
710 | PORT RFD_PAEn_24 = RFD_PAEn_24
|
---|
711 | PORT RFD_PAEn_5 = RFD_PAEn_5
|
---|
712 | PORT RFD_AntSw = RFD_AntSw
|
---|
713 | PORT usr_RFA_statLED_Tx = RFA_statLED_Tx
|
---|
714 | PORT usr_RFA_statLED_Rx = RFA_statLED_Rx
|
---|
715 | PORT usr_RFB_statLED_Tx = RFB_statLED_Tx
|
---|
716 | PORT usr_RFB_statLED_Rx = RFB_statLED_Rx
|
---|
717 | PORT usr_RFC_statLED_Tx = RFC_led_g
|
---|
718 | PORT usr_RFC_statLED_Rx = RFC_led_r
|
---|
719 | PORT usr_RFD_statLED_Tx = RFD_led_g
|
---|
720 | PORT usr_RFD_statLED_Rx = RFD_led_r
|
---|
721 | PORT usr_RFA_RxHP = agc_rxhp_a
|
---|
722 | PORT usr_RFB_RxHP = agc_rxhp_b
|
---|
723 | PORT usr_RFC_RxHP = agc_rxhp_c
|
---|
724 | PORT usr_RFD_RxHP = agc_rxhp_d
|
---|
725 | PORT usr_RFA_RxGainRF = agc_g_rf_a
|
---|
726 | PORT usr_RFB_RxGainRF = agc_g_rf_b
|
---|
727 | PORT usr_RFC_RxGainRF = agc_g_rf_c
|
---|
728 | PORT usr_RFD_RxGainRF = agc_g_rf_d
|
---|
729 | PORT usr_RFA_RxGainBB = agc_g_bb_a
|
---|
730 | PORT usr_RFB_RxGainBB = agc_g_bb_b
|
---|
731 | PORT usr_RFC_RxGainBB = agc_g_bb_c
|
---|
732 | PORT usr_RFD_RxGainBB = agc_g_bb_d
|
---|
733 | END
|
---|
734 |
|
---|
735 | # First instance of ad_bridge, to connect to on-board RF interfaces
|
---|
736 | # Bridge RFA = FMC RFA = user RFA
|
---|
737 | # Bridge RFB = FMC RFB = user RFB
|
---|
738 | BEGIN w3_ad_bridge
|
---|
739 | PARAMETER INSTANCE = w3_ad_bridge_onBoard
|
---|
740 | # exclude IDELAYCTRL, since TEMACs include them
|
---|
741 | PARAMETER INCLUDE_IDELAYCTRL = 0
|
---|
742 | PARAMETER HW_VER = 3.01.b
|
---|
743 | PARAMETER TRXCLK_IDELAY_RFA = 31
|
---|
744 | PARAMETER TRXCLK_IDELAY_RFB = 31
|
---|
745 | # Clock ports (inputs to w3_ad_bridge)
|
---|
746 | PORT clk200 = net_gnd
|
---|
747 | PORT sys_samp_clk_Tx = clk_40MHz
|
---|
748 | PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
|
---|
749 | PORT sys_samp_clk_Rx = clk_40MHz
|
---|
750 | # Top-level AD9963 ports
|
---|
751 | PORT ad_RFA_TXD = rfa_txd
|
---|
752 | PORT ad_RFA_TXCLK = rfa_txclk
|
---|
753 | PORT ad_RFA_TXIQ = rfa_txiq
|
---|
754 | PORT ad_RFA_TRXD = rfa_trxd
|
---|
755 | PORT ad_RFA_TRXCLK = rfa_trxclk
|
---|
756 | PORT ad_RFA_TRXIQ = rfa_trxiq
|
---|
757 | PORT ad_RFB_TXD = rfb_txd
|
---|
758 | PORT ad_RFB_TXCLK = rfb_txclk
|
---|
759 | PORT ad_RFB_TXIQ = rfb_txiq
|
---|
760 | PORT ad_RFB_TRXD = rfb_trxd
|
---|
761 | PORT ad_RFB_TRXCLK = rfb_trxclk
|
---|
762 | PORT ad_RFB_TRXIQ = rfb_trxiq
|
---|
763 | # ####
|
---|
764 | # User ports - connect these to custom logic
|
---|
765 | # Each port is Fix12_11
|
---|
766 | PORT user_RFA_TXD_I = warplab_radio1_Tx_I
|
---|
767 | PORT user_RFA_TXD_Q = warplab_radio1_Tx_Q
|
---|
768 | PORT user_RFA_RXD_I = warplab_radio1_Rx_I
|
---|
769 | PORT user_RFA_RXD_Q = warplab_radio1_Rx_Q
|
---|
770 | PORT user_RFB_TXD_I = warplab_radio2_Tx_I
|
---|
771 | PORT user_RFB_TXD_Q = warplab_radio2_Tx_Q
|
---|
772 | PORT user_RFB_RXD_I = warplab_radio2_Rx_I
|
---|
773 | PORT user_RFB_RXD_Q = warplab_radio2_Rx_Q
|
---|
774 | END
|
---|
775 |
|
---|
776 | # Second instance of ad_bridge, to connect to FMC RF interfaces
|
---|
777 | # Bridge RFA = FMC RFA = user RFC
|
---|
778 | # Bridge RFB = FMC RFB = user RFD
|
---|
779 | BEGIN w3_ad_bridge
|
---|
780 | PARAMETER INSTANCE = w3_ad_bridge_FMC
|
---|
781 | # exclude IDELAYCTRL, since TEMACs include them
|
---|
782 | PARAMETER INCLUDE_IDELAYCTRL = 0
|
---|
783 | PARAMETER HW_VER = 3.01.b
|
---|
784 | PARAMETER TRXCLK_IDELAY_RFA = 0
|
---|
785 | PARAMETER TRXCLK_IDELAY_RFB = 0
|
---|
786 | # Clock ports (inputs to w3_ad_bridge)
|
---|
787 | PORT clk200 = net_gnd
|
---|
788 | PORT sys_samp_clk_Tx = clk_40MHz
|
---|
789 | PORT sys_samp_clk_Tx_90 = clk_40MHz_90degphase
|
---|
790 | PORT sys_samp_clk_Rx = clk_40MHz
|
---|
791 | # Top-level AD9963 ports
|
---|
792 | PORT ad_RFA_TXD = rfc_txd
|
---|
793 | PORT ad_RFA_TXCLK = rfc_txclk
|
---|
794 | PORT ad_RFA_TXIQ = rfc_txiq
|
---|
795 | PORT ad_RFA_TRXD = rfc_trxd
|
---|
796 | PORT ad_RFA_TRXCLK = rfc_trxclk
|
---|
797 | PORT ad_RFA_TRXIQ = rfc_trxiq
|
---|
798 | PORT ad_RFB_TXD = rfd_txd
|
---|
799 | PORT ad_RFB_TXCLK = rfd_txclk
|
---|
800 | PORT ad_RFB_TXIQ = rfd_txiq
|
---|
801 | PORT ad_RFB_TRXD = rfd_trxd
|
---|
802 | PORT ad_RFB_TRXCLK = rfd_trxclk
|
---|
803 | PORT ad_RFB_TRXIQ = rfd_trxiq
|
---|
804 | # ####
|
---|
805 | # User ports - connect these to custom logic
|
---|
806 | # Each port is Fix12_11
|
---|
807 | PORT user_RFA_TXD_I = warplab_radio3_Tx_I
|
---|
808 | PORT user_RFA_TXD_Q = warplab_radio3_Tx_Q
|
---|
809 | PORT user_RFA_RXD_I = warplab_radio3_Rx_I
|
---|
810 | PORT user_RFA_RXD_Q = warplab_radio3_Rx_Q
|
---|
811 | PORT user_RFB_TXD_I = warplab_radio4_Tx_I
|
---|
812 | PORT user_RFB_TXD_Q = warplab_radio4_Tx_Q
|
---|
813 | PORT user_RFB_RXD_I = warplab_radio4_Rx_I
|
---|
814 | PORT user_RFB_RXD_Q = warplab_radio4_Rx_Q
|
---|
815 | END
|
---|
816 |
|
---|
817 | BEGIN plbv46_plbv46_bridge
|
---|
818 | PARAMETER INSTANCE = plb_primary_secondary_bridge
|
---|
819 | PARAMETER HW_VER = 1.04.a
|
---|
820 | PARAMETER C_BUS_CLOCK_RATIO = 2
|
---|
821 | PARAMETER C_NUM_ADDR_RNG = 1
|
---|
822 | PARAMETER C_BRIDGE_BASEADDR = 0xc08b0000
|
---|
823 | PARAMETER C_BRIDGE_HIGHADDR = 0xc08bffff
|
---|
824 | PARAMETER C_RNG0_BASEADDR = 0x80800000
|
---|
825 | PARAMETER C_RNG0_HIGHADDR = 0x80ffffff
|
---|
826 | BUS_INTERFACE MPLB = plb_secondary_80MHz
|
---|
827 | BUS_INTERFACE SPLB = plb_primary
|
---|
828 | END
|
---|
829 |
|
---|
830 | BEGIN plb_v46
|
---|
831 | PARAMETER INSTANCE = plb_secondary_80MHz
|
---|
832 | PARAMETER HW_VER = 1.05.a
|
---|
833 | PORT PLB_Clk = clk_80MHz
|
---|
834 | PORT SYS_Rst = sys_bus_reset
|
---|
835 | END
|
---|
836 |
|
---|
837 | BEGIN xps_sysmon_adc
|
---|
838 | PARAMETER INSTANCE = xps_sysmon_adc_0
|
---|
839 | PARAMETER HW_VER = 3.00.b
|
---|
840 | PARAMETER C_DCLK_RATIO = 2
|
---|
841 | PARAMETER C_BASEADDR = 0xc0880000
|
---|
842 | PARAMETER C_HIGHADDR = 0xc088ffff
|
---|
843 | BUS_INTERFACE SPLB = plb_primary
|
---|
844 | END
|
---|
845 |
|
---|
846 | BEGIN w3_warplab_buffers_plbw
|
---|
847 | PARAMETER INSTANCE = warplab_buffers_plbw_0
|
---|
848 | PARAMETER HW_VER = 1.00.a
|
---|
849 | PARAMETER C_BASEADDR = 0x80c00000
|
---|
850 | PARAMETER C_HIGHADDR = 0x80ffffff
|
---|
851 | BUS_INTERFACE SPLB = plb_secondary_80MHz
|
---|
852 | PORT sysgen_clk = clk_40MHz
|
---|
853 | PORT radio1_dac_i = warplab_radio1_Tx_I
|
---|
854 | PORT radio1_dac_q = warplab_radio1_Tx_Q
|
---|
855 | PORT radio1_adc_i = warplab_radio1_Rx_I
|
---|
856 | PORT radio1_adc_q = warplab_radio1_Rx_Q
|
---|
857 | PORT radio2_dac_i = warplab_radio2_Tx_I
|
---|
858 | PORT radio2_dac_q = warplab_radio2_Tx_Q
|
---|
859 | PORT radio2_adc_i = warplab_radio2_Rx_I
|
---|
860 | PORT radio2_adc_q = warplab_radio2_Rx_Q
|
---|
861 | PORT radio3_dac_i = warplab_radio3_Tx_I
|
---|
862 | PORT radio3_dac_q = warplab_radio3_Tx_Q
|
---|
863 | PORT radio3_adc_i = warplab_radio3_Rx_I
|
---|
864 | PORT radio3_adc_q = warplab_radio3_Rx_Q
|
---|
865 | PORT radio4_dac_i = warplab_radio4_Tx_I
|
---|
866 | PORT radio4_dac_q = warplab_radio4_Tx_Q
|
---|
867 | PORT radio4_adc_i = warplab_radio4_Rx_I
|
---|
868 | PORT radio4_adc_q = warplab_radio4_Rx_Q
|
---|
869 | PORT radio1_rssi = warplab_radio1_rssi_D
|
---|
870 | PORT radio2_rssi = warplab_radio2_rssi_D
|
---|
871 | PORT radio3_rssi = warplab_radio3_rssi_D
|
---|
872 | PORT radio4_rssi = warplab_radio4_rssi_D
|
---|
873 | PORT rssi_adc_clk = warplab_rssi_clk
|
---|
874 | PORT startcapture = net_gnd
|
---|
875 | PORT starttx = net_gnd
|
---|
876 | PORT stoptx = net_gnd
|
---|
877 | PORT agc_done = agc_is_done
|
---|
878 | PORT fromagc_radio1_i = dc_filtered_i_a
|
---|
879 | PORT fromagc_radio1_q = dc_filtered_q_a
|
---|
880 | PORT fromagc_radio2_i = dc_filtered_i_b
|
---|
881 | PORT fromagc_radio2_q = dc_filtered_q_b
|
---|
882 | PORT fromagc_radio3_i = dc_filtered_i_c
|
---|
883 | PORT fromagc_radio3_q = dc_filtered_q_c
|
---|
884 | PORT fromagc_radio4_i = dc_filtered_i_d
|
---|
885 | PORT fromagc_radio4_q = dc_filtered_q_d
|
---|
886 | PORT debug_capturing = warplab_mimo_4x4_plbw_0_debug_capturing
|
---|
887 | PORT debug_transmitting = warplab_mimo_4x4_plbw_0_debug_transmitting
|
---|
888 | END
|
---|
889 |
|
---|
890 | BEGIN w3_warplab_agc_plbw
|
---|
891 | PARAMETER INSTANCE = warplab_agc_plbw_0
|
---|
892 | PARAMETER HW_VER = 1.00.a
|
---|
893 | PARAMETER C_BASEADDR = 0x80900000
|
---|
894 | PARAMETER C_HIGHADDR = 0x8090ffff
|
---|
895 | BUS_INTERFACE SPLB = plb_secondary_80MHz
|
---|
896 | PORT sysgen_clk = clk_40MHz
|
---|
897 | PORT rxhp_a = agc_rxhp_a
|
---|
898 | PORT rxhp_b = agc_rxhp_b
|
---|
899 | PORT rxhp_c = agc_rxhp_c
|
---|
900 | PORT rxhp_d = agc_rxhp_d
|
---|
901 | PORT g_rf_a = agc_g_rf_a
|
---|
902 | PORT g_rf_b = agc_g_rf_b
|
---|
903 | PORT g_rf_c = agc_g_rf_c
|
---|
904 | PORT g_rf_d = agc_g_rf_d
|
---|
905 | PORT g_bb_a = agc_g_bb_a
|
---|
906 | PORT g_bb_b = agc_g_bb_b
|
---|
907 | PORT g_bb_c = agc_g_bb_c
|
---|
908 | PORT g_bb_d = agc_g_bb_d
|
---|
909 | PORT agc_done = agc_is_done
|
---|
910 | PORT rssi_in_a = warplab_radio1_rssi_D
|
---|
911 | PORT rssi_in_b = warplab_radio2_rssi_D
|
---|
912 | PORT rssi_in_c = warplab_radio3_rssi_D
|
---|
913 | PORT rssi_in_d = warplab_radio4_rssi_D
|
---|
914 | PORT reset_in = net_gnd
|
---|
915 | PORT i_in_a = warplab_radio1_Rx_I
|
---|
916 | PORT i_in_b = warplab_radio2_Rx_I
|
---|
917 | PORT i_in_c = warplab_radio3_Rx_I
|
---|
918 | PORT i_in_d = warplab_radio4_Rx_I
|
---|
919 | PORT q_in_a = warplab_radio1_Rx_Q
|
---|
920 | PORT q_in_b = warplab_radio2_Rx_Q
|
---|
921 | PORT q_in_c = warplab_radio3_Rx_Q
|
---|
922 | PORT q_in_d = warplab_radio4_Rx_Q
|
---|
923 | PORT packet_in = net_gnd
|
---|
924 | PORT mreset_in = net_gnd
|
---|
925 | PORT i_out_a = dc_filtered_i_a
|
---|
926 | PORT i_out_b = dc_filtered_i_b
|
---|
927 | PORT i_out_c = dc_filtered_i_c
|
---|
928 | PORT i_out_d = dc_filtered_i_d
|
---|
929 | PORT q_out_a = dc_filtered_q_a
|
---|
930 | PORT q_out_b = dc_filtered_q_b
|
---|
931 | PORT q_out_c = dc_filtered_q_c
|
---|
932 | PORT q_out_d = dc_filtered_q_d
|
---|
933 | END
|
---|
934 |
|
---|
935 | BEGIN xps_central_dma
|
---|
936 | PARAMETER INSTANCE = xps_central_dma_0
|
---|
937 | PARAMETER HW_VER = 2.03.a
|
---|
938 | PARAMETER C_BASEADDR = 0xc0bb0000
|
---|
939 | PARAMETER C_HIGHADDR = 0xc0bbffff
|
---|
940 | BUS_INTERFACE MPLB = plb_primary
|
---|
941 | BUS_INTERFACE SPLB = plb_primary
|
---|
942 | END
|
---|
943 |
|
---|
944 | BEGIN xps_gpio
|
---|
945 | PARAMETER INSTANCE = xps_gpio_0
|
---|
946 | PARAMETER HW_VER = 2.00.a
|
---|
947 | PARAMETER C_GPIO_WIDTH = 6
|
---|
948 | PARAMETER C_BASEADDR = 0xc0ae0000
|
---|
949 | PARAMETER C_HIGHADDR = 0xc0aeffff
|
---|
950 | BUS_INTERFACE SPLB = plb_primary
|
---|
951 | PORT GPIO_IO_O = debug_sw_gpio
|
---|
952 | END
|
---|
953 |
|
---|