1 | #Debug header LOC constraints (manually entered) |
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2 | NET "debug_status<0>" LOC = "AG27" | IOSTANDARD = LVCMOS25; #pin 0 |
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3 | NET "debug_status<1>" LOC = "AE26" | IOSTANDARD = LVCMOS25; #pin 1 |
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4 | |
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5 | NET "debug_sw_gpio<0>" LOC = "AF26" | IOSTANDARD = "LVCMOS25"; #pin 2 |
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6 | NET "debug_sw_gpio<1>" LOC = "AD25" | IOSTANDARD = "LVCMOS25"; #pin 3 |
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7 | NET "debug_sw_gpio<2>" LOC = "V24" | IOSTANDARD = "LVCMOS25"; #pin 4 |
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8 | NET "debug_sw_gpio<3>" LOC = "AA23" | IOSTANDARD = "LVCMOS25"; #pin 5 |
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9 | NET "debug_sw_gpio<4>" LOC = "AH30" | IOSTANDARD = "LVCMOS25"; #pin 6 |
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10 | NET "debug_sw_gpio<5>" LOC = "AK31" | IOSTANDARD = "LVCMOS25"; #pin 7 |
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11 |
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12 | #SIP switch on CM-MMCX |
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13 | NET "cm_mmcx_sw<0>" LOC = V30 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL12 in schematics |
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14 | NET "cm_mmcx_sw<1>" LOC = R34 | IOSTANDARD = LVCMOS25 | PULLUP; #CLKHDR_CTRL13 in schematics
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15 | |
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16 | #User IO |
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17 | Net USERIO_hexdisp_left_pin<0> LOC=AL33 | IOSTANDARD = LVCMOS25; |
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18 | Net USERIO_hexdisp_left_pin<1> LOC=AK33 | IOSTANDARD = LVCMOS25; |
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19 | Net USERIO_hexdisp_left_pin<2> LOC=AH32 | IOSTANDARD = LVCMOS25; |
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20 | Net USERIO_hexdisp_left_pin<3> LOC=AF29 | IOSTANDARD = LVCMOS25; |
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21 | Net USERIO_hexdisp_left_pin<4> LOC=AE29 | IOSTANDARD = LVCMOS25; |
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22 | Net USERIO_hexdisp_left_pin<5> LOC=AK32 | IOSTANDARD = LVCMOS25; |
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23 | Net USERIO_hexdisp_left_pin<6> LOC=AF30 | IOSTANDARD = LVCMOS25; |
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24 | Net USERIO_hexdisp_right_pin<0> LOC=AE28 | IOSTANDARD = LVCMOS25; |
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25 | Net USERIO_hexdisp_right_pin<1> LOC=AD26 | IOSTANDARD = LVCMOS25; |
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26 | Net USERIO_hexdisp_right_pin<2> LOC=AC24 | IOSTANDARD = LVCMOS25; |
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27 | Net USERIO_hexdisp_right_pin<3> LOC=AE23 | IOSTANDARD = LVCMOS25; |
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28 | Net USERIO_hexdisp_right_pin<4> LOC=AC22 | IOSTANDARD = LVCMOS25; |
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29 | Net USERIO_hexdisp_right_pin<5> LOC=AD27 | IOSTANDARD = LVCMOS25; |
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30 | Net USERIO_hexdisp_right_pin<6> LOC=AB23 | IOSTANDARD = LVCMOS25; |
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31 | Net USERIO_hexdisp_left_dp_pin LOC=AG30 | IOSTANDARD = LVCMOS25; |
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32 | Net USERIO_hexdisp_right_dp_pin LOC=AC23 | IOSTANDARD = LVCMOS25; |
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33 | Net USERIO_leds_red_pin<0> LOC=AN34 | IOSTANDARD = LVCMOS25; |
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34 | Net USERIO_leds_red_pin<1> LOC=AM33 | IOSTANDARD = LVCMOS25; |
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35 | Net USERIO_leds_red_pin<2> LOC=AN33 | IOSTANDARD = LVCMOS25; |
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36 | Net USERIO_leds_red_pin<3> LOC=AP33 | IOSTANDARD = LVCMOS25; |
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37 | Net USERIO_leds_green_pin<0> LOC=AD22 | IOSTANDARD = LVCMOS25; |
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38 | Net USERIO_leds_green_pin<1> LOC=AE22 | IOSTANDARD = LVCMOS25; |
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39 | Net USERIO_leds_green_pin<2> LOC=AM32 | IOSTANDARD = LVCMOS25; |
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40 | Net USERIO_leds_green_pin<3> LOC=AN32 | IOSTANDARD = LVCMOS25; |
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41 | Net USERIO_rfa_led_red_pin LOC=AL34 | IOSTANDARD = LVCMOS25; |
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42 | Net USERIO_rfa_led_green_pin LOC=AK34 | IOSTANDARD = LVCMOS25; |
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43 | Net USERIO_rfb_led_red_pin LOC=AJ34 | IOSTANDARD = LVCMOS25; |
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44 | Net USERIO_rfb_led_green_pin LOC=AH34 | IOSTANDARD = LVCMOS25; |
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45 | Net USERIO_dipsw_pin<3> LOC=AM22 | IOSTANDARD = LVCMOS15; |
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46 | Net USERIO_dipsw_pin<2> LOC=AL23 | IOSTANDARD = LVCMOS15; |
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47 | Net USERIO_dipsw_pin<1> LOC=AM23 | IOSTANDARD = LVCMOS15; |
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48 | Net USERIO_dipsw_pin<0> LOC=AN23 | IOSTANDARD = LVCMOS15; |
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49 | Net USERIO_pb_u_pin LOC=AM21 | IOSTANDARD = LVCMOS15; |
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50 | Net USERIO_pb_m_pin LOC=AN22 | IOSTANDARD = LVCMOS15; |
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51 | Net USERIO_pb_d_pin LOC=AP22 | IOSTANDARD = LVCMOS15; |
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52 | |
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53 | #USB UART on WARP v3 rev 1.1 |
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54 | Net UART_USB_TX_pin LOC = H9 | IOSTANDARD=LVCMOS25; #FT230X RXD pin |
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55 | Net UART_USB_RX_pin LOC = J9 | IOSTANDARD=LVCMOS25; #FT230X TXD pin |
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56 | |
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57 | #IIC EEPROM (on board) |
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58 | Net IIC_EEPROM_iic_sda_pin LOC = AG23 | IOSTANDARD=LVCMOS25; |
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59 | Net IIC_EEPROM_iic_scl_pin LOC = AF23 | IOSTANDARD=LVCMOS25; |
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60 | |
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61 | #ETH A |
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62 | Net ETH_A_TemacPhy_RST_n_pin LOC=L9 | IOSTANDARD = LVCMOS25 | TIG; |
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63 | Net ETH_A_RGMII_TXD_0_pin<0> LOC=AF9 | IOSTANDARD = LVCMOS25; |
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64 | Net ETH_A_RGMII_TXD_0_pin<1> LOC=AF10 | IOSTANDARD = LVCMOS25; |
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65 | Net ETH_A_RGMII_TXD_0_pin<2> LOC=AD9 | IOSTANDARD = LVCMOS25; |
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66 | Net ETH_A_RGMII_TXD_0_pin<3> LOC=AD10 | IOSTANDARD = LVCMOS25; |
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67 | Net ETH_A_RGMII_TX_CTL_0_pin LOC=AG8 | IOSTANDARD = LVCMOS25; |
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68 | Net ETH_A_RGMII_TXC_0_pin LOC=AE9 | IOSTANDARD = LVCMOS25; |
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69 | Net ETH_A_RGMII_RXD_0_pin<0> LOC=AK9 | IOSTANDARD = LVCMOS25; |
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70 | Net ETH_A_RGMII_RXD_0_pin<1> LOC=AJ9 | IOSTANDARD = LVCMOS25; |
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71 | Net ETH_A_RGMII_RXD_0_pin<2> LOC=AH8 | IOSTANDARD = LVCMOS25; |
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72 | Net ETH_A_RGMII_RXD_0_pin<3> LOC=AH9 | IOSTANDARD = LVCMOS25; |
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73 | Net ETH_A_RGMII_RX_CTL_0_pin LOC=AL9 | IOSTANDARD = LVCMOS25; |
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74 | Net ETH_A_RGMII_RXC_0_pin LOC=AC10 | IOSTANDARD = LVCMOS25; |
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75 | #Fix for errata in rev 1.1 schematics |
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76 | Net ETH_A_MDC_0_pin LOC=AK8 | IOSTANDARD = LVCMOS25; |
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77 | Net ETH_A_MDIO_0_pin LOC=AP9 | IOSTANDARD = LVCMOS25 | PULLUP; |
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78 | |
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79 | #ETH B |
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80 | Net ETH_B_RGMII_TXD_0_pin<0> LOC=M10 | IOSTANDARD = LVCMOS25; |
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81 | Net ETH_B_RGMII_TXD_0_pin<1> LOC=B8 | IOSTANDARD = LVCMOS25; |
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82 | Net ETH_B_RGMII_TXD_0_pin<2> LOC=AC9 | IOSTANDARD = LVCMOS25; |
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83 | Net ETH_B_RGMII_TXD_0_pin<3> LOC=E9 | IOSTANDARD = LVCMOS25; |
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84 | Net ETH_B_RGMII_TX_CTL_0_pin LOC=D10 | IOSTANDARD = LVCMOS25; |
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85 | Net ETH_B_RGMII_TXC_0_pin LOC=AB10 | IOSTANDARD = LVCMOS25; |
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86 | Net ETH_B_RGMII_RXD_0_pin<0> LOC=A9 | IOSTANDARD = LVCMOS25; |
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87 | Net ETH_B_RGMII_RXD_0_pin<1> LOC=D9 | IOSTANDARD = LVCMOS25; |
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88 | Net ETH_B_RGMII_RXD_0_pin<2> LOC=C9 | IOSTANDARD = LVCMOS25; |
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89 | Net ETH_B_RGMII_RXD_0_pin<3> LOC=F10 | IOSTANDARD = LVCMOS25; |
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90 | Net ETH_B_RGMII_RX_CTL_0_pin LOC=A8 | IOSTANDARD = LVCMOS25; |
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91 | Net ETH_B_RGMII_RXC_0_pin LOC=L10 | IOSTANDARD = LVCMOS25; |
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92 | Net ETH_B_MDC_0_pin LOC=AN9 | IOSTANDARD = LVCMOS25; |
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93 | Net ETH_B_MDIO_0_pin LOC=AL8 | IOSTANDARD = LVCMOS25; |
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94 | |
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95 | #DDR3 SO-DIMM |
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96 | Net DDR3_2GB_SODIMM_Clk_pin LOC=AC15 | IOSTANDARD = DIFF_SSTL15; |
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97 | Net DDR3_2GB_SODIMM_Clk_n_pin LOC=AD15 | IOSTANDARD = DIFF_SSTL15; |
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98 | Net DDR3_2GB_SODIMM_CE_pin LOC=AF18 | IOSTANDARD = SSTL15; |
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99 | Net DDR3_2GB_SODIMM_CS_n_pin LOC=AL16 | IOSTANDARD = SSTL15; |
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100 | Net DDR3_2GB_SODIMM_ODT_pin LOC=AP15 | IOSTANDARD = SSTL15; |
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101 | Net DDR3_2GB_SODIMM_RAS_n_pin LOC=AM16 | IOSTANDARD = SSTL15; |
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102 | Net DDR3_2GB_SODIMM_CAS_n_pin LOC=AJ17 | IOSTANDARD = SSTL15; |
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103 | Net DDR3_2GB_SODIMM_WE_n_pin LOC=AF15 | IOSTANDARD = SSTL15; |
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104 | Net DDR3_2GB_SODIMM_BankAddr_pin<0> LOC=AG15 | IOSTANDARD = SSTL15; |
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105 | Net DDR3_2GB_SODIMM_BankAddr_pin<1> LOC=AP16 | IOSTANDARD = SSTL15; |
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106 | Net DDR3_2GB_SODIMM_BankAddr_pin<2> LOC=AD17 | IOSTANDARD = SSTL15; |
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107 | Net DDR3_2GB_SODIMM_Addr_pin<0> LOC=AM17 | IOSTANDARD = SSTL15; |
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108 | Net DDR3_2GB_SODIMM_Addr_pin<1> LOC=AF16 | IOSTANDARD = SSTL15; |
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109 | Net DDR3_2GB_SODIMM_Addr_pin<2> LOC=AN17 | IOSTANDARD = SSTL15; |
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110 | Net DDR3_2GB_SODIMM_Addr_pin<3> LOC=AG17 | IOSTANDARD = SSTL15; |
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111 | Net DDR3_2GB_SODIMM_Addr_pin<4> LOC=AK16 | IOSTANDARD = SSTL15; |
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112 | Net DDR3_2GB_SODIMM_Addr_pin<5> LOC=AG16 | IOSTANDARD = SSTL15; |
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113 | Net DDR3_2GB_SODIMM_Addr_pin<6> LOC=AK17 | IOSTANDARD = SSTL15; |
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114 | Net DDR3_2GB_SODIMM_Addr_pin<7> LOC=AG18 | IOSTANDARD = SSTL15; |
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115 | Net DDR3_2GB_SODIMM_Addr_pin<8> LOC=AE16 | IOSTANDARD = SSTL15; |
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116 | Net DDR3_2GB_SODIMM_Addr_pin<9> LOC=AD16 | IOSTANDARD = SSTL15; |
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117 | Net DDR3_2GB_SODIMM_Addr_pin<10> LOC=AH15 | IOSTANDARD = SSTL15; |
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118 | Net DDR3_2GB_SODIMM_Addr_pin<11> LOC=AH18 | IOSTANDARD = SSTL15; |
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119 | Net DDR3_2GB_SODIMM_Addr_pin<12> LOC=AE17 | IOSTANDARD = SSTL15; |
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120 | Net DDR3_2GB_SODIMM_Addr_pin<13> LOC=AJ16 | IOSTANDARD = SSTL15; |
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121 | Net DDR3_2GB_SODIMM_Addr_pin<14> LOC=AK18 | IOSTANDARD = SSTL15; |
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122 | Net DDR3_2GB_SODIMM_DQ_pin<0> LOC=AK29 | IOSTANDARD = SSTL15_T_DCI; |
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123 | Net DDR3_2GB_SODIMM_DQ_pin<1> LOC=AN30 | IOSTANDARD = SSTL15_T_DCI; |
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124 | Net DDR3_2GB_SODIMM_DQ_pin<2> LOC=AL29 | IOSTANDARD = SSTL15_T_DCI; |
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125 | Net DDR3_2GB_SODIMM_DQ_pin<3> LOC=AN29 | IOSTANDARD = SSTL15_T_DCI; |
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126 | Net DDR3_2GB_SODIMM_DQ_pin<4> LOC=AP31 | IOSTANDARD = SSTL15_T_DCI; |
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127 | Net DDR3_2GB_SODIMM_DQ_pin<5> LOC=AP30 | IOSTANDARD = SSTL15_T_DCI; |
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128 | Net DDR3_2GB_SODIMM_DQ_pin<6> LOC=AH28 | IOSTANDARD = SSTL15_T_DCI; |
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129 | Net DDR3_2GB_SODIMM_DQ_pin<7> LOC=AH27 | IOSTANDARD = SSTL15_T_DCI; |
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130 | Net DDR3_2GB_SODIMM_DQ_pin<8> LOC=AK28 | IOSTANDARD = SSTL15_T_DCI; |
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131 | Net DDR3_2GB_SODIMM_DQ_pin<9> LOC=AL28 | IOSTANDARD = SSTL15_T_DCI; |
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132 | Net DDR3_2GB_SODIMM_DQ_pin<10> LOC=AJ27 | IOSTANDARD = SSTL15_T_DCI; |
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133 | Net DDR3_2GB_SODIMM_DQ_pin<11> LOC=AH25 | IOSTANDARD = SSTL15_T_DCI; |
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134 | Net DDR3_2GB_SODIMM_DQ_pin<12> LOC=AP29 | IOSTANDARD = SSTL15_T_DCI; |
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135 | Net DDR3_2GB_SODIMM_DQ_pin<13> LOC=AM27 | IOSTANDARD = SSTL15_T_DCI; |
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136 | Net DDR3_2GB_SODIMM_DQ_pin<14> LOC=AJ25 | IOSTANDARD = SSTL15_T_DCI; |
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137 | Net DDR3_2GB_SODIMM_DQ_pin<15> LOC=AH24 | IOSTANDARD = SSTL15_T_DCI; |
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138 | Net DDR3_2GB_SODIMM_DQ_pin<16> LOC=AJ24 | IOSTANDARD = SSTL15_T_DCI; |
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139 | Net DDR3_2GB_SODIMM_DQ_pin<17> LOC=AK24 | IOSTANDARD = SSTL15_T_DCI; |
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140 | Net DDR3_2GB_SODIMM_DQ_pin<18> LOC=AL24 | IOSTANDARD = SSTL15_T_DCI; |
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141 | Net DDR3_2GB_SODIMM_DQ_pin<19> LOC=AK23 | IOSTANDARD = SSTL15_T_DCI; |
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142 | Net DDR3_2GB_SODIMM_DQ_pin<20> LOC=AP27 | IOSTANDARD = SSTL15_T_DCI; |
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143 | Net DDR3_2GB_SODIMM_DQ_pin<21> LOC=AM26 | IOSTANDARD = SSTL15_T_DCI; |
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144 | Net DDR3_2GB_SODIMM_DQ_pin<22> LOC=AN25 | IOSTANDARD = SSTL15_T_DCI; |
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145 | Net DDR3_2GB_SODIMM_DQ_pin<23> LOC=AN24 | IOSTANDARD = SSTL15_T_DCI; |
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146 | Net DDR3_2GB_SODIMM_DQ_pin<24> LOC=AD21 | IOSTANDARD = SSTL15_T_DCI; |
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147 | Net DDR3_2GB_SODIMM_DQ_pin<25> LOC=AE21 | IOSTANDARD = SSTL15_T_DCI; |
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148 | Net DDR3_2GB_SODIMM_DQ_pin<26> LOC=AK22 | IOSTANDARD = SSTL15_T_DCI; |
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149 | Net DDR3_2GB_SODIMM_DQ_pin<27> LOC=AL18 | IOSTANDARD = SSTL15_T_DCI; |
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150 | Net DDR3_2GB_SODIMM_DQ_pin<28> LOC=AN19 | IOSTANDARD = SSTL15_T_DCI; |
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151 | Net DDR3_2GB_SODIMM_DQ_pin<29> LOC=AP19 | IOSTANDARD = SSTL15_T_DCI; |
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152 | Net DDR3_2GB_SODIMM_DQ_pin<30> LOC=AM18 | IOSTANDARD = SSTL15_T_DCI; |
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153 | Net DDR3_2GB_SODIMM_DQ_pin<31> LOC=AN18 | IOSTANDARD = SSTL15_T_DCI; |
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154 | Net DDR3_2GB_SODIMM_DM_pin<0> LOC=AM30 | IOSTANDARD = SSTL15; |
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155 | Net DDR3_2GB_SODIMM_DM_pin<1> LOC=AL26 | IOSTANDARD = SSTL15; |
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156 | Net DDR3_2GB_SODIMM_DM_pin<2> LOC=AP26 | IOSTANDARD = SSTL15; |
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157 | Net DDR3_2GB_SODIMM_DM_pin<3> LOC=AJ22 | IOSTANDARD = SSTL15; |
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158 | Net DDR3_2GB_SODIMM_Reset_n_pin LOC=AP17 | IOSTANDARD = SSTL15; |
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159 | Net DDR3_2GB_SODIMM_DQS_pin<0> LOC=AG25 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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160 | Net DDR3_2GB_SODIMM_DQS_pin<1> LOC=AN28 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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161 | Net DDR3_2GB_SODIMM_DQS_pin<2> LOC=AM25 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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162 | Net DDR3_2GB_SODIMM_DQS_pin<3> LOC=AG22 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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163 | Net DDR3_2GB_SODIMM_DQS_n_pin<0> LOC=AG26 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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164 | Net DDR3_2GB_SODIMM_DQS_n_pin<1> LOC=AM28 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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165 | Net DDR3_2GB_SODIMM_DQS_n_pin<2> LOC=AL25 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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166 | Net DDR3_2GB_SODIMM_DQS_n_pin<3> LOC=AH22 | IOSTANDARD = DIFF_SSTL15_T_DCI; |
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167 | |
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168 | #System clock (80MHz, from sampling clock buffer) |
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169 | NET samp_clk_n_pin LOC = V23 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; |
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170 | NET samp_clk_p_pin LOC = U23 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE; |
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171 | Net samp_clk_p_pin TNM_NET = samp_clk_pin; |
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172 | TIMESPEC TS_samp_clk_pin = PERIOD samp_clk_pin 80000 kHz; |
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173 | |
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174 | #System clock (200MHz, from LVDS oscillator) |
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175 | Net osc200_p_pin LOC = A10 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE; |
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176 | Net osc200_n_pin LOC = B10 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE; |
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177 | Net osc200_p_pin TNM_NET = osc200_p_pin; |
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178 | TIMESPEC TS_osc200_p_pin = PERIOD osc200_p_pin 200000 kHz; |
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179 | |
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180 | #Processor reset (RESET button on board) |
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181 | Net rst_1_sys_rst_pin LOC = AH13 | IOSTANDARD=LVCMOS15 | TIG; |
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182 | Net rst_1_sys_rst_pin TIG; |
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183 | |
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184 | INST clock_generator_MPMC_Clocks/*/MMCM0_INST*/MMCM_ADV_inst LOC = MMCM_ADV_X0Y2; |
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185 | |
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186 | ############################# |
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187 | #On-board RF interfaces |
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188 | ############################# |
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189 | |
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190 | #MAX2829 transceivers and RF front end |
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191 | NET RFA_SPI_SCLK_pin LOC=T34 | IOSTANDARD=LVCMOS25; |
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192 | NET RFA_SPI_MOSI_pin LOC=T33 | IOSTANDARD=LVCMOS25; |
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193 | NET RFA_SPI_CSn_pin LOC=U32 | IOSTANDARD=LVCMOS25; |
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194 | NET RFA_SHDN_pin LOC=U27 | IOSTANDARD=LVCMOS25; |
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195 | NET RFA_TxEn_pin LOC=T31 | IOSTANDARD=LVCMOS25; |
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196 | NET RFA_RxEn_pin LOC=U33 | IOSTANDARD=LVCMOS25; |
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197 | NET RFA_RxHP_pin LOC=AG32 | IOSTANDARD=LVCMOS25; |
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198 | NET RFA_PAEn_24_pin LOC=U25 | IOSTANDARD=LVCMOS25; |
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199 | NET RFA_PAEn_5_pin LOC=U28 | IOSTANDARD=LVCMOS25; |
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200 | NET RFA_ANTSW_pin<0> LOC=U31 | IOSTANDARD=LVCMOS25; |
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201 | NET RFA_ANTSW_pin<1> LOC=U30 | IOSTANDARD=LVCMOS25; |
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202 | NET RFA_LD_pin LOC=U26 | IOSTANDARD=LVCMOS25; |
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203 | NET RFA_B_pin<0> LOC=AG33 | IOSTANDARD=LVCMOS25; |
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204 | NET RFA_B_pin<1> LOC=AF31 | IOSTANDARD=LVCMOS25; |
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205 | NET RFA_B_pin<2> LOC=AF33 | IOSTANDARD=LVCMOS25; |
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206 | NET RFA_B_pin<3> LOC=AG31 | IOSTANDARD=LVCMOS25; |
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207 | NET RFA_B_pin<4> LOC=AF34 | IOSTANDARD=LVCMOS25; |
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208 | NET RFA_B_pin<5> LOC=AE33 | IOSTANDARD=LVCMOS25; |
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209 | NET RFA_B_pin<6> LOC=AE34 | IOSTANDARD=LVCMOS25; |
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210 | |
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211 | NET RFB_SPI_SCLK_pin LOC=H34 | IOSTANDARD=LVCMOS25; |
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212 | NET RFB_SPI_MOSI_pin LOC=H33 | IOSTANDARD=LVCMOS25; |
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213 | NET RFB_SPI_CSn_pin LOC=J32 | IOSTANDARD=LVCMOS25; |
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214 | NET RFB_SHDN_pin LOC=J34 | IOSTANDARD=LVCMOS25; |
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215 | NET RFB_TxEn_pin LOC=H32 | IOSTANDARD=LVCMOS25; |
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216 | NET RFB_RxEn_pin LOC=J31 | IOSTANDARD=LVCMOS25; |
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217 | NET RFB_RxHP_pin LOC=R28 | IOSTANDARD=LVCMOS25; |
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218 | NET RFB_PAEn_24_pin LOC=T25 | IOSTANDARD=LVCMOS25; |
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219 | NET RFB_PAEn_5_pin LOC=T28 | IOSTANDARD=LVCMOS25; |
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220 | NET RFB_ANTSW_pin<0> LOC=T30 | IOSTANDARD=LVCMOS25; |
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221 | NET RFB_ANTSW_pin<1> LOC=T29 | IOSTANDARD=LVCMOS25; |
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222 | NET RFB_LD_pin LOC=K33 | IOSTANDARD=LVCMOS25; |
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223 | NET RFB_B_pin<0> LOC=P27 | IOSTANDARD=LVCMOS25; |
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224 | NET RFB_B_pin<1> LOC=R27 | IOSTANDARD=LVCMOS25; |
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225 | NET RFB_B_pin<2> LOC=R29 | IOSTANDARD=LVCMOS25; |
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226 | NET RFB_B_pin<3> LOC=R26 | IOSTANDARD=LVCMOS25; |
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227 | NET RFB_B_pin<4> LOC=R32 | IOSTANDARD=LVCMOS25; |
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228 | NET RFB_B_pin<5> LOC=T26 | IOSTANDARD=LVCMOS25; |
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229 | NET RFB_B_pin<6> LOC=R31 | IOSTANDARD=LVCMOS25; |
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230 | |
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231 | NET RFA_AD_spi_sclk_pin LOC = AB33 | IOSTANDARD = LVCMOS25;# |
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232 | NET RFA_AD_spi_sdio LOC = AC30 | IOSTANDARD = LVCMOS25;# |
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233 | NET RFA_AD_spi_cs_n_pin LOC = AB31 | IOSTANDARD = LVCMOS25;# |
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234 | NET RFA_AD_reset_n_pin LOC = AA34 | IOSTANDARD = LVCMOS25;# |
---|
235 | |
---|
236 | NET RFB_AD_spi_sclk_pin LOC = P32 | IOSTANDARD = LVCMOS25;# |
---|
237 | NET RFB_AD_spi_sdio LOC = P34 | IOSTANDARD = LVCMOS25;# |
---|
238 | NET RFB_AD_spi_cs_n_pin LOC = N32 | IOSTANDARD = LVCMOS25;# |
---|
239 | NET RFB_AD_reset_n_pin LOC = N34 | IOSTANDARD = LVCMOS25;# |
---|
240 | |
---|
241 | NET clk_rfref_spi_sclk_pin LOC = V25 | IOSTANDARD = LVCMOS25;# |
---|
242 | NET clk_rfref_spi_mosi_pin LOC = W25 | IOSTANDARD = LVCMOS25;# |
---|
243 | NET clk_rfref_spi_cs_n_pin LOC = W27 | IOSTANDARD = LVCMOS25;# |
---|
244 | NET clk_rfref_spi_miso_pin LOC = Y27 | IOSTANDARD = LVCMOS25;# |
---|
245 | NET clk_rfref_func_pin LOC = L26 | IOSTANDARD = LVCMOS25; |
---|
246 | |
---|
247 | NET clk_samp_spi_sclk_pin LOC = W32 | IOSTANDARD = LVCMOS25;# |
---|
248 | NET clk_samp_spi_mosi_pin LOC = Y29 | IOSTANDARD = LVCMOS25;# |
---|
249 | NET clk_samp_spi_cs_n_pin LOC = W31 | IOSTANDARD = LVCMOS25;# |
---|
250 | NET clk_samp_spi_miso_pin LOC = Y28 | IOSTANDARD = LVCMOS25;# |
---|
251 | NET clk_samp_func_pin LOC = R33 | IOSTANDARD = LVCMOS25;# |
---|
252 | |
---|
253 | #TRXCLK pins driven by AD9963's; assuming 80MHz worst case |
---|
254 | Net RFA_AD_TRXCLK TNM_NET = RFA_AD_TRXCLK; |
---|
255 | TIMESPEC TS_RFA_AD_TRXCLK = PERIOD RFA_AD_TRXCLK 80 MHz; |
---|
256 | |
---|
257 | Net RFB_AD_TRXCLK TNM_NET = RFB_AD_TRXCLK; |
---|
258 | TIMESPEC TS_RFB_AD_TRXCLK = PERIOD RFB_AD_TRXCLK 80 MHz; |
---|
259 | |
---|
260 | #RFA AD9963 |
---|
261 | NET RFA_AD_TRXD<0> LOC = AC25 | IOSTANDARD = LVCMOS25; |
---|
262 | NET RFA_AD_TRXD<1> LOC = AB25 | IOSTANDARD = LVCMOS25; |
---|
263 | NET RFA_AD_TRXD<2> LOC = AB32 | IOSTANDARD = LVCMOS25; |
---|
264 | NET RFA_AD_TRXD<3> LOC = AC29 | IOSTANDARD = LVCMOS25; |
---|
265 | NET RFA_AD_TRXD<4> LOC = AD29 | IOSTANDARD = LVCMOS25; |
---|
266 | NET RFA_AD_TRXD<5> LOC = AC33 | IOSTANDARD = LVCMOS25; |
---|
267 | NET RFA_AD_TRXD<6> LOC = AD34 | IOSTANDARD = LVCMOS25; |
---|
268 | NET RFA_AD_TRXD<7> LOC = AC32 | IOSTANDARD = LVCMOS25; |
---|
269 | NET RFA_AD_TRXD<8> LOC = AD31 | IOSTANDARD = LVCMOS25; |
---|
270 | NET RFA_AD_TRXD<9> LOC = AD32 | IOSTANDARD = LVCMOS25; |
---|
271 | NET RFA_AD_TRXD<10> LOC = AE31 | IOSTANDARD = LVCMOS25; |
---|
272 | NET RFA_AD_TRXD<11> LOC = AE32 | IOSTANDARD = LVCMOS25; |
---|
273 | |
---|
274 | NET RFA_AD_TRXCLK LOC = AD30 | IOSTANDARD = LVCMOS25; |
---|
275 | NET RFA_AD_TRXIQ LOC = AC34 | IOSTANDARD = LVCMOS25; |
---|
276 | |
---|
277 | NET RFA_AD_TXCLK LOC = AA31 | IOSTANDARD = LVCMOS25; |
---|
278 | NET RFA_AD_TXIQ LOC = AA33 | IOSTANDARD = LVCMOS25; |
---|
279 | |
---|
280 | NET RFA_AD_TXD<0> LOC = AA25 | IOSTANDARD = LVCMOS25; |
---|
281 | NET RFA_AD_TXD<1> LOC = AB26 | IOSTANDARD = LVCMOS25; |
---|
282 | NET RFA_AD_TXD<2> LOC = Y26 | IOSTANDARD = LVCMOS25; |
---|
283 | NET RFA_AD_TXD<3> LOC = AA26 | IOSTANDARD = LVCMOS25; |
---|
284 | NET RFA_AD_TXD<4> LOC = AA28 | IOSTANDARD = LVCMOS25; |
---|
285 | NET RFA_AD_TXD<5> LOC = AA29 | IOSTANDARD = LVCMOS25; |
---|
286 | NET RFA_AD_TXD<6> LOC = AA30 | IOSTANDARD = LVCMOS25; |
---|
287 | NET RFA_AD_TXD<7> LOC = AB30 | IOSTANDARD = LVCMOS25; |
---|
288 | NET RFA_AD_TXD<8> LOC = AB28 | IOSTANDARD = LVCMOS25; |
---|
289 | NET RFA_AD_TXD<9> LOC = AB27 | IOSTANDARD = LVCMOS25; |
---|
290 | NET RFA_AD_TXD<10> LOC = AC28 | IOSTANDARD = LVCMOS25; |
---|
291 | NET RFA_AD_TXD<11> LOC = AC27 | IOSTANDARD = LVCMOS25; |
---|
292 | |
---|
293 | #RFB |
---|
294 | NET RFB_AD_TRXD<0> LOC = N25 | IOSTANDARD = LVCMOS25; |
---|
295 | NET RFB_AD_TRXD<1> LOC = M25 | IOSTANDARD = LVCMOS25; |
---|
296 | NET RFB_AD_TRXD<2> LOC = N28 | IOSTANDARD = LVCMOS25; |
---|
297 | NET RFB_AD_TRXD<3> LOC = N27 | IOSTANDARD = LVCMOS25; |
---|
298 | NET RFB_AD_TRXD<4> LOC = P29 | IOSTANDARD = LVCMOS25; |
---|
299 | NET RFB_AD_TRXD<5> LOC = M30 | IOSTANDARD = LVCMOS25; |
---|
300 | NET RFB_AD_TRXD<6> LOC = N30 | IOSTANDARD = LVCMOS25; |
---|
301 | NET RFB_AD_TRXD<7> LOC = N29 | IOSTANDARD = LVCMOS25; |
---|
302 | NET RFB_AD_TRXD<8> LOC = P26 | IOSTANDARD = LVCMOS25; |
---|
303 | NET RFB_AD_TRXD<9> LOC = P31 | IOSTANDARD = LVCMOS25; |
---|
304 | NET RFB_AD_TRXD<10> LOC = P25 | IOSTANDARD = LVCMOS25; |
---|
305 | NET RFB_AD_TRXD<11> LOC = P30 | IOSTANDARD = LVCMOS25; |
---|
306 | |
---|
307 | NET RFB_AD_TRXCLK LOC = N33 | IOSTANDARD = LVCMOS25; |
---|
308 | NET RFB_AD_TRXIQ LOC = M33 | IOSTANDARD = LVCMOS25; |
---|
309 | |
---|
310 | NET RFB_AD_TXCLK LOC = L28 | IOSTANDARD = LVCMOS25; |
---|
311 | NET RFB_AD_TXIQ LOC = L29 | IOSTANDARD = LVCMOS25; |
---|
312 | |
---|
313 | NET RFB_AD_TXD<0> LOC = K32 | IOSTANDARD = LVCMOS25; |
---|
314 | NET RFB_AD_TXD<1> LOC = M26 | IOSTANDARD = LVCMOS25; |
---|
315 | NET RFB_AD_TXD<2> LOC = M32 | IOSTANDARD = LVCMOS25; |
---|
316 | NET RFB_AD_TXD<3> LOC = K34 | IOSTANDARD = LVCMOS25; |
---|
317 | NET RFB_AD_TXD<4> LOC = M31 | IOSTANDARD = LVCMOS25; |
---|
318 | NET RFB_AD_TXD<5> LOC = L30 | IOSTANDARD = LVCMOS25; |
---|
319 | NET RFB_AD_TXD<6> LOC = L33 | IOSTANDARD = LVCMOS25; |
---|
320 | NET RFB_AD_TXD<7> LOC = L31 | IOSTANDARD = LVCMOS25; |
---|
321 | NET RFB_AD_TXD<8> LOC = M28 | IOSTANDARD = LVCMOS25; |
---|
322 | NET RFB_AD_TXD<9> LOC = L34 | IOSTANDARD = LVCMOS25; |
---|
323 | NET RFB_AD_TXD<10> LOC = M27 | IOSTANDARD = LVCMOS25; |
---|
324 | NET RFB_AD_TXD<11> LOC = K31 | IOSTANDARD = LVCMOS25; |
---|
325 | |
---|
326 | NET RF_RSSI_CLK LOC = B32 | IOSTANDARD = LVCMOS25; |
---|
327 | NET RF_RSSI_PD LOC = B34 | IOSTANDARD = LVCMOS25; |
---|
328 | NET RFB_RSSI_D<0> LOC = A33 | IOSTANDARD = LVCMOS25; |
---|
329 | NET RFB_RSSI_D<1> LOC = B33 | IOSTANDARD = LVCMOS25; |
---|
330 | NET RFB_RSSI_D<2> LOC = C33 | IOSTANDARD = LVCMOS25; |
---|
331 | NET RFB_RSSI_D<3> LOC = C34 | IOSTANDARD = LVCMOS25; |
---|
332 | NET RFB_RSSI_D<4> LOC = C32 | IOSTANDARD = LVCMOS25; |
---|
333 | NET RFB_RSSI_D<5> LOC = D31 | IOSTANDARD = LVCMOS25; |
---|
334 | NET RFB_RSSI_D<6> LOC = G30 | IOSTANDARD = LVCMOS25; |
---|
335 | NET RFB_RSSI_D<7> LOC = E31 | IOSTANDARD = LVCMOS25; |
---|
336 | NET RFB_RSSI_D<8> LOC = D32 | IOSTANDARD = LVCMOS25; |
---|
337 | NET RFB_RSSI_D<9> LOC = D34 | IOSTANDARD = LVCMOS25; |
---|
338 | NET RFA_RSSI_D<0> LOC = E32 | IOSTANDARD = LVCMOS25; |
---|
339 | NET RFA_RSSI_D<1> LOC = E33 | IOSTANDARD = LVCMOS25; |
---|
340 | NET RFA_RSSI_D<2> LOC = E34 | IOSTANDARD = LVCMOS25; |
---|
341 | NET RFA_RSSI_D<3> LOC = F30 | IOSTANDARD = LVCMOS25; |
---|
342 | NET RFA_RSSI_D<4> LOC = F31 | IOSTANDARD = LVCMOS25; |
---|
343 | NET RFA_RSSI_D<5> LOC = F34 | IOSTANDARD = LVCMOS25; |
---|
344 | NET RFA_RSSI_D<6> LOC = F33 | IOSTANDARD = LVCMOS25; |
---|
345 | NET RFA_RSSI_D<7> LOC = G31 | IOSTANDARD = LVCMOS25; |
---|
346 | NET RFA_RSSI_D<8> LOC = G33 | IOSTANDARD = LVCMOS25; |
---|
347 | NET RFA_RSSI_D<9> LOC = G32 | IOSTANDARD = LVCMOS25; |
---|
348 | |
---|
349 | |
---|
350 | ############################# |
---|
351 | # FMC-RF-2X245 RF Interfaces |
---|
352 | ############################# |
---|
353 | #User LEDs |
---|
354 | NET "RFC_LED_G" LOC = L19 | IOSTANDARD = LVCMOS25; |
---|
355 | NET "RFC_LED_R" LOC = L18 | IOSTANDARD = LVCMOS25; |
---|
356 | |
---|
357 | NET "RFD_LED_G" LOC = D16 | IOSTANDARD = LVCMOS25; |
---|
358 | NET "RFD_LED_R" LOC = A15 | IOSTANDARD = LVCMOS25; |
---|
359 | |
---|
360 | #FMC module I2C EEPROM |
---|
361 | NET "FMC_IIC_EEPROM_scl_pin" LOC = F23 | IOSTANDARD = LVCMOS25; |
---|
362 | NET "FMC_IIC_EEPROM_sda_pin" LOC = F24 | IOSTANDARD = LVCMOS25; |
---|
363 | |
---|
364 | #RSSI ADC |
---|
365 | NET "RFC_RSSI_D<0>" LOC = D21 | IOSTANDARD = LVCMOS25; |
---|
366 | NET "RFC_RSSI_D<1>" LOC = E19 | IOSTANDARD = LVCMOS25; |
---|
367 | NET "RFC_RSSI_D<2>" LOC = G20 | IOSTANDARD = LVCMOS25; |
---|
368 | NET "RFC_RSSI_D<3>" LOC = E22 | IOSTANDARD = LVCMOS25; |
---|
369 | NET "RFC_RSSI_D<4>" LOC = E23 | IOSTANDARD = LVCMOS25; |
---|
370 | NET "RFC_RSSI_D<5>" LOC = F21 | IOSTANDARD = LVCMOS25; |
---|
371 | NET "RFC_RSSI_D<6>" LOC = B20 | IOSTANDARD = LVCMOS25; |
---|
372 | NET "RFC_RSSI_D<7>" LOC = B23 | IOSTANDARD = LVCMOS25; |
---|
373 | NET "RFC_RSSI_D<8>" LOC = C19 | IOSTANDARD = LVCMOS25; |
---|
374 | NET "RFC_RSSI_D<9>" LOC = C23 | IOSTANDARD = LVCMOS25; |
---|
375 | |
---|
376 | NET "RFD_RSSI_D<0>" LOC = D19 | IOSTANDARD = LVCMOS25; |
---|
377 | NET "RFD_RSSI_D<1>" LOC = E21 | IOSTANDARD = LVCMOS25; |
---|
378 | NET "RFD_RSSI_D<2>" LOC = A23 | IOSTANDARD = LVCMOS25; |
---|
379 | NET "RFD_RSSI_D<3>" LOC = A24 | IOSTANDARD = LVCMOS25; |
---|
380 | NET "RFD_RSSI_D<4>" LOC = F19 | IOSTANDARD = LVCMOS25; |
---|
381 | NET "RFD_RSSI_D<5>" LOC = H19 | IOSTANDARD = LVCMOS25; |
---|
382 | NET "RFD_RSSI_D<6>" LOC = F20 | IOSTANDARD = LVCMOS25; |
---|
383 | NET "RFD_RSSI_D<7>" LOC = H20 | IOSTANDARD = LVCMOS25; |
---|
384 | NET "RFD_RSSI_D<8>" LOC = C20 | IOSTANDARD = LVCMOS25; |
---|
385 | NET "RFD_RSSI_D<9>" LOC = J20 | IOSTANDARD = LVCMOS25; |
---|
386 | |
---|
387 | NET "FMC_RF_RSSI_CLK" LOC = G13 | IOSTANDARD = LVCMOS25; |
---|
388 | NET "FMC_RF_RSSI_PD" LOC = A21 | IOSTANDARD = LVCMOS25; |
---|
389 | |
---|
390 | #FMC module RF A pins (probably renamed RF C in user project) |
---|
391 | |
---|
392 | #ADC/DAC |
---|
393 | NET "RFC_AD_spi_sclk_pin" LOC = B25 | IOSTANDARD = LVCMOS25; |
---|
394 | NET "RFC_AD_SPI_SDIO" LOC = D26 | IOSTANDARD = LVCMOS25 | PULLDOWN; |
---|
395 | NET "RFC_AD_spi_cs_n_pin" LOC = D27 | IOSTANDARD = LVCMOS25; |
---|
396 | NET "RFC_AD_reset_n_pin" LOC = B27 | IOSTANDARD = LVCMOS25; |
---|
397 | |
---|
398 | NET "RFC_AD_TRXCLK" LOC = C28 | IOSTANDARD = LVCMOS25; |
---|
399 | NET "RFC_AD_TRXIQ" LOC = D29 | IOSTANDARD = LVCMOS25; |
---|
400 | |
---|
401 | NET "RFC_AD_TRXD<0>" LOC = C29 | IOSTANDARD = LVCMOS25; |
---|
402 | NET "RFC_AD_TRXD<1>" LOC = C24 | IOSTANDARD = LVCMOS25; |
---|
403 | NET "RFC_AD_TRXD<2>" LOC = C22 | IOSTANDARD = LVCMOS25; |
---|
404 | NET "RFC_AD_TRXD<3>" LOC = G27 | IOSTANDARD = LVCMOS25; |
---|
405 | NET "RFC_AD_TRXD<4>" LOC = G28 | IOSTANDARD = LVCMOS25; |
---|
406 | NET "RFC_AD_TRXD<5>" LOC = D22 | IOSTANDARD = LVCMOS25; |
---|
407 | NET "RFC_AD_TRXD<6>" LOC = G26 | IOSTANDARD = LVCMOS25; |
---|
408 | NET "RFC_AD_TRXD<7>" LOC = A25 | IOSTANDARD = LVCMOS25; |
---|
409 | NET "RFC_AD_TRXD<8>" LOC = A26 | IOSTANDARD = LVCMOS25; |
---|
410 | NET "RFC_AD_TRXD<9>" LOC = H27 | IOSTANDARD = LVCMOS25; |
---|
411 | NET "RFC_AD_TRXD<10>" LOC = E27 | IOSTANDARD = LVCMOS25; |
---|
412 | NET "RFC_AD_TRXD<11>" LOC = B26 | IOSTANDARD = LVCMOS25; |
---|
413 | |
---|
414 | NET "RFC_AD_TXCLK" LOC = C27 | IOSTANDARD = LVCMOS25; |
---|
415 | NET "RFC_AD_TXIQ" LOC = C30 | IOSTANDARD = LVCMOS25; |
---|
416 | |
---|
417 | NET "RFC_AD_TXD<0>" LOC = F26 | IOSTANDARD = LVCMOS25; |
---|
418 | NET "RFC_AD_TXD<1>" LOC = K21 | IOSTANDARD = LVCMOS25; |
---|
419 | NET "RFC_AD_TXD<2>" LOC = E24 | IOSTANDARD = LVCMOS25; |
---|
420 | NET "RFC_AD_TXD<3>" LOC = G25 | IOSTANDARD = LVCMOS25; |
---|
421 | NET "RFC_AD_TXD<4>" LOC = F25 | IOSTANDARD = LVCMOS25; |
---|
422 | NET "RFC_AD_TXD<5>" LOC = E26 | IOSTANDARD = LVCMOS25; |
---|
423 | NET "RFC_AD_TXD<6>" LOC = A19 | IOSTANDARD = LVCMOS25; |
---|
424 | NET "RFC_AD_TXD<7>" LOC = D24 | IOSTANDARD = LVCMOS25; |
---|
425 | NET "RFC_AD_TXD<8>" LOC = A18 | IOSTANDARD = LVCMOS25; |
---|
426 | NET "RFC_AD_TXD<9>" LOC = L21 | IOSTANDARD = LVCMOS25; |
---|
427 | NET "RFC_AD_TXD<10>" LOC = L20 | IOSTANDARD = LVCMOS25; |
---|
428 | NET "RFC_AD_TXD<11>" LOC = D30 | IOSTANDARD = LVCMOS25; |
---|
429 | |
---|
430 | #Front end |
---|
431 | NET "RFC_PAEn_24_pin" LOC = D14 | IOSTANDARD = LVCMOS25; |
---|
432 | NET "RFC_PAEn_5_pin" LOC = M12 | IOSTANDARD = LVCMOS25; |
---|
433 | NET "RFC_AntSw_pin<0>" LOC = M11 | IOSTANDARD = LVCMOS25; |
---|
434 | NET "RFC_AntSw_pin<1>" LOC = A13 | IOSTANDARD = LVCMOS25; |
---|
435 | |
---|
436 | #Transceiver |
---|
437 | NET "RFC_B_pin<0>" LOC = B30 | IOSTANDARD = LVCMOS25; |
---|
438 | NET "RFC_B_pin<1>" LOC = F28 | IOSTANDARD = LVCMOS25; |
---|
439 | NET "RFC_B_pin<2>" LOC = B31 | IOSTANDARD = LVCMOS25; |
---|
440 | NET "RFC_B_pin<3>" LOC = E28 | IOSTANDARD = LVCMOS25; |
---|
441 | NET "RFC_B_pin<4>" LOC = D25 | IOSTANDARD = LVCMOS25; |
---|
442 | NET "RFC_B_pin<5>" LOC = A30 | IOSTANDARD = LVCMOS25; |
---|
443 | NET "RFC_B_pin<6>" LOC = A31 | IOSTANDARD = LVCMOS25; |
---|
444 | |
---|
445 | NET "RFC_SPI_SCLK_pin" LOC = A29 | IOSTANDARD = LVCMOS25; |
---|
446 | NET "RFC_SPI_CSn_pin" LOC = B18 | IOSTANDARD = LVCMOS25; |
---|
447 | NET "RFC_SPI_MOSI_pin" LOC = J22 | IOSTANDARD = LVCMOS25; |
---|
448 | NET "RFC_RXEN_pin" LOC = H22 | IOSTANDARD = LVCMOS25; |
---|
449 | NET "RFC_RXHP_pin" LOC = B28 | IOSTANDARD = LVCMOS25; |
---|
450 | NET "RFC_SHDN_pin" LOC = K22 | IOSTANDARD = LVCMOS25; |
---|
451 | NET "RFC_TXEN_pin" LOC = C18 | IOSTANDARD = LVCMOS25; |
---|
452 | NET "RFC_LD_pin" LOC = A28 | IOSTANDARD = LVCMOS25; |
---|
453 | |
---|
454 | #FMC module RF B pins (probably renamed RF D in user project) |
---|
455 | |
---|
456 | #ADC/DAC |
---|
457 | NET "RFD_AD_spi_sclk_pin" LOC = K17 | IOSTANDARD = LVCMOS25; |
---|
458 | NET "RFD_AD_SPI_SDIO" LOC = B17 | IOSTANDARD = LVCMOS25 | PULLDOWN; |
---|
459 | NET "RFD_AD_spi_cs_n_pin" LOC = D15 | IOSTANDARD = LVCMOS25; |
---|
460 | NET "RFD_AD_reset_n_pin" LOC = G15 | IOSTANDARD = LVCMOS25; |
---|
461 | |
---|
462 | NET "RFD_AD_TRXCLK" LOC = L15 | IOSTANDARD = LVCMOS25; |
---|
463 | NET "RFD_AD_TRXIQ" LOC = K18 | IOSTANDARD = LVCMOS25; |
---|
464 | |
---|
465 | NET "RFD_AD_TRXD<0>" LOC = J16 | IOSTANDARD = LVCMOS25; |
---|
466 | NET "RFD_AD_TRXD<1>" LOC = H17 | IOSTANDARD = LVCMOS25; |
---|
467 | NET "RFD_AD_TRXD<2>" LOC = J17 | IOSTANDARD = LVCMOS25; |
---|
468 | NET "RFD_AD_TRXD<3>" LOC = L16 | IOSTANDARD = LVCMOS25; |
---|
469 | NET "RFD_AD_TRXD<4>" LOC = G18 | IOSTANDARD = LVCMOS25; |
---|
470 | NET "RFD_AD_TRXD<5>" LOC = M18 | IOSTANDARD = LVCMOS25; |
---|
471 | NET "RFD_AD_TRXD<6>" LOC = H18 | IOSTANDARD = LVCMOS25; |
---|
472 | NET "RFD_AD_TRXD<7>" LOC = M17 | IOSTANDARD = LVCMOS25; |
---|
473 | NET "RFD_AD_TRXD<8>" LOC = D17 | IOSTANDARD = LVCMOS25; |
---|
474 | NET "RFD_AD_TRXD<9>" LOC = J19 | IOSTANDARD = LVCMOS25; |
---|
475 | NET "RFD_AD_TRXD<10>" LOC = K19 | IOSTANDARD = LVCMOS25; |
---|
476 | NET "RFD_AD_TRXD<11>" LOC = E18 | IOSTANDARD = LVCMOS25; |
---|
477 | |
---|
478 | NET "RFD_AD_TXCLK" LOC = C17 | IOSTANDARD = LVCMOS25; |
---|
479 | NET "RFD_AD_TXIQ" LOC = E17 | IOSTANDARD = LVCMOS25; |
---|
480 | |
---|
481 | NET "RFD_AD_TXD<0>" LOC = B16 | IOSTANDARD = LVCMOS25; |
---|
482 | NET "RFD_AD_TXD<1>" LOC = J15 | IOSTANDARD = LVCMOS25; |
---|
483 | NET "RFD_AD_TXD<2>" LOC = A16 | IOSTANDARD = LVCMOS25; |
---|
484 | NET "RFD_AD_TXD<3>" LOC = H15 | IOSTANDARD = LVCMOS25; |
---|
485 | NET "RFD_AD_TXD<4>" LOC = M15 | IOSTANDARD = LVCMOS25; |
---|
486 | NET "RFD_AD_TXD<5>" LOC = F15 | IOSTANDARD = LVCMOS25; |
---|
487 | NET "RFD_AD_TXD<6>" LOC = C15 | IOSTANDARD = LVCMOS25; |
---|
488 | NET "RFD_AD_TXD<7>" LOC = M16 | IOSTANDARD = LVCMOS25; |
---|
489 | NET "RFD_AD_TXD<8>" LOC = B15 | IOSTANDARD = LVCMOS25; |
---|
490 | NET "RFD_AD_TXD<9>" LOC = G16 | IOSTANDARD = LVCMOS25; |
---|
491 | NET "RFD_AD_TXD<10>" LOC = F18 | IOSTANDARD = LVCMOS25; |
---|
492 | NET "RFD_AD_TXD<11>" LOC = F16 | IOSTANDARD = LVCMOS25; |
---|
493 | |
---|
494 | #Front end |
---|
495 | NET "RFD_PAEn_24_pin" LOC = A14 | IOSTANDARD = LVCMOS25; |
---|
496 | NET "RFD_PAEn_5_pin" LOC = B13 | IOSTANDARD = LVCMOS25; |
---|
497 | NET "RFD_AntSw_pin<0>" LOC = C14 | IOSTANDARD = LVCMOS25; |
---|
498 | NET "RFD_AntSw_pin<1>" LOC = B12 | IOSTANDARD = LVCMOS25; |
---|
499 | |
---|
500 | #Transceiver |
---|
501 | NET "RFD_B_pin<0>" LOC = H12 | IOSTANDARD = LVCMOS25; |
---|
502 | NET "RFD_B_pin<1>" LOC = H13 | IOSTANDARD = LVCMOS25; |
---|
503 | NET "RFD_B_pin<2>" LOC = M13 | IOSTANDARD = LVCMOS25; |
---|
504 | NET "RFD_B_pin<3>" LOC = G12 | IOSTANDARD = LVCMOS25; |
---|
505 | NET "RFD_B_pin<4>" LOC = F14 | IOSTANDARD = LVCMOS25; |
---|
506 | NET "RFD_B_pin<5>" LOC = H14 | IOSTANDARD = LVCMOS25; |
---|
507 | NET "RFD_B_pin<6>" LOC = J12 | IOSTANDARD = LVCMOS25; |
---|
508 | NET "RFD_SPI_SCLK_pin" LOC = G10 | IOSTANDARD = LVCMOS25; |
---|
509 | NET "RFD_SPI_CSn_pin" LOC = K13 | IOSTANDARD = LVCMOS25; |
---|
510 | NET "RFD_SPI_MOSI_pin" LOC = F11 | IOSTANDARD = LVCMOS25; |
---|
511 | NET "RFD_RXEN_pin" LOC = K12 | IOSTANDARD = LVCMOS25; |
---|
512 | NET "RFD_RXHP_pin" LOC = L13 | IOSTANDARD = LVCMOS25; |
---|
513 | NET "RFD_SHDN_pin" LOC = K11 | IOSTANDARD = LVCMOS25; |
---|
514 | NET "RFD_TXEN_pin" LOC = H10 | IOSTANDARD = LVCMOS25; |
---|
515 | NET "RFD_LD_pin" LOC = L11 | IOSTANDARD = LVCMOS25; |
---|
516 | |
---|
517 | |
---|
518 | ###### ETH_A |
---|
519 | ###### Hard_Ethernet_MAC |
---|
520 | # This is a RGMII system |
---|
521 | # GTX_CLK_0 = 125MHz |
---|
522 | # LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator |
---|
523 | # Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods |
---|
524 | # Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency |
---|
525 | # allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, |
---|
526 | # the constraints are over constrained. Relaxing them for your system may reduce build time. |
---|
527 | |
---|
528 | NET "*ETH_A*/hrst*" TIG; |
---|
529 | |
---|
530 | # Locate the Tri-Mode Ethernet MAC instance |
---|
531 | INST "*ETH_A*v6_emac" LOC = "TEMAC_X0Y0"; |
---|
532 | |
---|
533 | ############################################################################### |
---|
534 | # CLOCK CONSTRAINTS |
---|
535 | # The following constraints are required. If you choose to not use the example |
---|
536 | # design level of wrapper hierarchy, the net names should be translated to |
---|
537 | # match your design. |
---|
538 | ############################################################################### |
---|
539 | |
---|
540 | # Ethernet GTX_CLK high quality 125 MHz reference clock |
---|
541 | NET "*/GTX_CLK_0" TNM_NET = "ref_gtx_clk"; #name of signal connected to TEMAC GTX_CLK_0 input |
---|
542 | TIMEGRP "v6_emac_v1_3_clk_ref_gtx" = "ref_gtx_clk"; |
---|
543 | TIMESPEC "TS_v6_emac_v1_3_clk_ref_gtx" = PERIOD "v6_emac_v1_3_clk_ref_gtx" 8 ns HIGH 50 %; #constant value based on constant 125 MHZ GTX clock |
---|
544 | |
---|
545 | # Ethernet RGMII PHY-side transmit clock |
---|
546 | # Changed NET Name - Input to bufg_tx_0 |
---|
547 | # ___________ |
---|
548 | # | | |\ |
---|
549 | # | Hard Core |--- tx_clk_0_o --| >---- Tx_Cl_Clk ----- |
---|
550 | # |___________| |/ |
---|
551 | # BUFG |
---|
552 | # |
---|
553 | NET "*ETH_A*/tx_cl_clk" TNM_NET = "A_phy_clk_tx"; |
---|
554 | TIMEGRP "A_v6_emac_v1_3_clk_phy_tx" = "A_phy_clk_tx"; |
---|
555 | TIMESPEC "TS_A_v6_emac_v1_3_clk_phy_tx" = PERIOD "A_v6_emac_v1_3_clk_phy_tx" 8 ns HIGH 50 %; |
---|
556 | |
---|
557 | # Ethernet RGMII PHY-side receive clock |
---|
558 | # Changed NET Name |
---|
559 | # RGMII_RXC_0 is the name of the clock net at the TEMAC Port |
---|
560 | # It is the input to the IODELAY |
---|
561 | # RxClientClk_0 is the name of the BUFG output clock net |
---|
562 | # |
---|
563 | # _________ BUFR |
---|
564 | # | | |\ |
---|
565 | # ---RGMII_RXC_0----| IODELAY |------| >----RxClientClk_0------------ |
---|
566 | # |_________| |/ |
---|
567 | # |
---|
568 | NET "ETH_A_RGMII_RXC_0_pin" TNM_NET = "A_phy_clk_rx"; |
---|
569 | TIMEGRP "A_v6_emac_v1_3_clk_phy_rx" = "A_phy_clk_rx"; |
---|
570 | TIMESPEC "TS_A_v6_emac_v1_3_clk_phy_rx" = PERIOD "A_v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %; |
---|
571 | |
---|
572 | # IDELAYCTRL 200 MHz reference clock |
---|
573 | NET "clk_200*MHz*" TNM_NET = "clk_ref_clk"; #name of signal connected to TEMAC REFCLK input |
---|
574 | TIMEGRP "ref_clk" = "clk_ref_clk"; |
---|
575 | TIMESPEC "TS_ref_clk" = PERIOD "ref_clk" 5 ns HIGH 50 %; #constant value based on constant 200 MHZ ref clock |
---|
576 | |
---|
577 | # Constrain the DCR interface clock to an example frequency of 100 MHz |
---|
578 | # Changed NET Name |
---|
579 | # NET "DCREMACCLK" TNM_NET = "host_clock"; |
---|
580 | #NET "*ETH_A*/SPLB_CLK" TNM_NET = "host_clock"; |
---|
581 | #TIMEGRP "A_clk_host" = "A_host_clock"; |
---|
582 | #TIMESPEC "TS_A_clk_host" = PERIOD "A_clk_host" 10 ns HIGH 50 %; |
---|
583 | |
---|
584 | ############################################################################### |
---|
585 | # PHYSICAL INTERFACE CONSTRAINTS |
---|
586 | # The following constraints are necessary for proper operation, and are tuned |
---|
587 | # for this example design. They should be modified to suit your design. |
---|
588 | ############################################################################### |
---|
589 | |
---|
590 | # RGMII physical interface constraints |
---|
591 | # ----------------------------------------------------------------------------- |
---|
592 | |
---|
593 | # Set the IDELAY and ODELAY values, tuned for this example design. |
---|
594 | # These values should be modified to suit your design. |
---|
595 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
---|
596 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
---|
597 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
---|
598 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
---|
599 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
---|
600 | |
---|
601 | INST "*ETH_A*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
---|
602 | INST "*ETH_A*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
---|
603 | INST "*ETH_A*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
---|
604 | INST "*ETH_A*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
---|
605 | INST "*ETH_A*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
---|
606 | |
---|
607 | INST "*ETH_A*rgmii_rxc0_delay" IDELAY_VALUE = 0; |
---|
608 | INST "*ETH_A*rgmii_rxc0_delay" SIGNAL_PATTERN = CLOCK; |
---|
609 | |
---|
610 | INST "*ETH_A*rgmii?rgmii_tx_clk_delay" ODELAY_VALUE = 6; |
---|
611 | INST "*ETH_A*rgmii?rgmii_tx_clk_delay" SIGNAL_PATTERN = CLOCK; |
---|
612 | |
---|
613 | # Group all IODELAY-related blocks to use a single IDELAYCTRL |
---|
614 | |
---|
615 | # Change - added TNMs for trace length variations |
---|
616 | INST "ETH_A_RGMII_RXD_0_pin[0]" TNM = "A_rgmii_rx_d0"; |
---|
617 | INST "ETH_A_RGMII_RXD_0_pin[1]" TNM = "A_rgmii_rx_d1"; |
---|
618 | INST "ETH_A_RGMII_RXD_0_pin[2]" TNM = "A_rgmii_rx_d2"; |
---|
619 | INST "ETH_A_RGMII_RXD_0_pin[3]" TNM = "A_rgmii_rx_d3"; |
---|
620 | INST "ETH_A_RGMII_RX_CTL_0_pin" TNM = "A_rgmii_rx_ctrl"; |
---|
621 | |
---|
622 | # Spec: 1.2ns setup time, 1.2ns hold time |
---|
623 | # The internal PHY delays were not used to derive the OFFSET constraints |
---|
624 | # Changed NET Name |
---|
625 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock |
---|
626 | # Therefore the offset in constraint must have less setup time than nominal |
---|
627 | TIMEGRP "A_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
---|
628 | TIMEGRP "A_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
---|
629 | |
---|
630 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock |
---|
631 | # Therefore the offset in constraint must have more setup time than nominal |
---|
632 | TIMEGRP "A_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
---|
633 | TIMEGRP "A_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
---|
634 | |
---|
635 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock |
---|
636 | # Therefore the offset in constraint must have more setup time than nominal |
---|
637 | TIMEGRP "A_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
---|
638 | TIMEGRP "A_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
---|
639 | |
---|
640 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock |
---|
641 | # Therefore the offset in constraint must have more setup time than nominal |
---|
642 | TIMEGRP "A_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
---|
643 | TIMEGRP "A_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
---|
644 | |
---|
645 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock |
---|
646 | # Therefore the offset in constraint must have more setup time than nominal |
---|
647 | TIMEGRP "A_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" RISING; |
---|
648 | TIMEGRP "A_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_A_RGMII_RXC_0_pin" FALLING; |
---|
649 | |
---|
650 | |
---|
651 | NET "*ETH_A*/LlinkTemac0_CLK" TNM_NET = "A_LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input |
---|
652 | NET "*ETH_A*/SPLB_Clk" TNM_NET = "A_PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input |
---|
653 | NET "*ETH_A*/REFCLK" TNM_NET = "A_REFCLK"; #name of signal connected to TEMAC REFCLK input |
---|
654 | |
---|
655 | TIMESPEC "TS_A_LL_CLK0_2_RX_CLIENT_CLK0" = FROM A_LLCLK0 TO A_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
---|
656 | TIMESPEC "TS_A_LL_CLK0_2_TX_CLIENT_CLK0" = FROM A_LLCLK0 TO A_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
---|
657 | TIMESPEC "TS_A_RX_CLIENT_CLK0_2_LL_CLK0" = FROM A_phy_clk_rx TO A_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
---|
658 | TIMESPEC "TS_A_TX_CLIENT_CLK0_2_LL_CLK0" = FROM A_phy_clk_tx TO A_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
---|
659 | |
---|
660 | TIMESPEC "TS_A_REF_CLK_2_PLB_CLIENT_CLK" = FROM A_REFCLK TO A_PLBCLK 8000 ps DATAPATHONLY; #varies based on period of PLB clock |
---|
661 | TIMESPEC "TS_A_PLB_CLIENT_CLK_2_REF_CLK" = FROM A_PLBCLK TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock |
---|
662 | |
---|
663 | TIMESPEC "TS_A_REF_CLK_2_TX_CLIENT_CLK0" = FROM A_REFCLK TO A_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
---|
664 | TIMESPEC "TS_A_TX_CLIENT_CLK0_2_REF_CLK" = FROM A_phy_clk_tx TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock |
---|
665 | |
---|
666 | TIMESPEC "TS_A_REF_CLK_2_RX_CLIENT_CLK0" = FROM A_REFCLK TO A_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
---|
667 | TIMESPEC "TS_A_RX_CLIENT_CLK0_2_REF_CLK" = FROM A_phy_clk_rx TO A_REFCLK 5000 ps DATAPATHONLY; #constant value based on constant 200 MHZ ref clock |
---|
668 | |
---|
669 | |
---|
670 | |
---|
671 | ###### ETH_B |
---|
672 | ###### Hard_Ethernet_MAC |
---|
673 | # This is a RGMII system |
---|
674 | # GTX_CLK_0 = 125MHz |
---|
675 | # LlinkTemac0_CLK = plb_v46 clk = host clock = 100MHz from clock generator |
---|
676 | # Rx/Tx Client clocks are Rx/Tx PHY clocks so CORE Gen PHY clock constraints propagate to Rx/Tx client clock periods |
---|
677 | # Time domain crossing constraints (DATAPATHONLY) are set for maximum bus frequency |
---|
678 | # allowed by IP which is the maximum option in BSB. For lower bus frequency choice in BSB, |
---|
679 | # the constraints are over constrained. Relaxing them for your system may reduce build time. |
---|
680 | |
---|
681 | NET "*ETH_B*/hrst*" TIG; |
---|
682 | |
---|
683 | # Locate the Tri-Mode Ethernet MAC instance |
---|
684 | INST "*ETH_B*v6_emac" LOC = "TEMAC_X0Y1"; |
---|
685 | |
---|
686 | ############################################################################### |
---|
687 | # CLOCK CONSTRAINTS |
---|
688 | # The following constraints are required. If you choose to not use the example |
---|
689 | # design level of wrapper hierarchy, the net names should be translated to |
---|
690 | # match your design. |
---|
691 | ############################################################################### |
---|
692 | |
---|
693 | # Ethernet RGMII PHY-side transmit clock |
---|
694 | # Changed NET Name - Input to bufg_tx_0 |
---|
695 | # ___________ |
---|
696 | # | | |\ |
---|
697 | # | Hard Core |--- tx_clk_0_o --| >---- Tx_Cl_Clk ----- |
---|
698 | # |___________| |/ |
---|
699 | # BUFG |
---|
700 | # |
---|
701 | NET "*ETH_B*/tx_cl_clk" TNM_NET = "B_phy_clk_tx"; |
---|
702 | TIMEGRP "B_v6_emac_v1_3_clk_phy_tx" = "B_phy_clk_tx"; |
---|
703 | TIMESPEC "TS_B_v6_emac_v1_3_clk_phy_tx" = PERIOD "B_v6_emac_v1_3_clk_phy_tx" 8 ns HIGH 50 %; |
---|
704 | |
---|
705 | # Ethernet RGMII PHY-side receive clock |
---|
706 | # Changed NET Name |
---|
707 | # RGMII_RXC_0 is the name of the clock net at the TEMAC Port |
---|
708 | # It is the input to the IODELAY |
---|
709 | # RxClientClk_0 is the name of the BUFG output clock net |
---|
710 | # |
---|
711 | # _________ BUFR |
---|
712 | # | | |\ |
---|
713 | # ---RGMII_RXC_0----| IODELAY |------| >----RxClientClk_0------------ |
---|
714 | # |_________| |/ |
---|
715 | # |
---|
716 | NET "ETH_B_RGMII_RXC_0_pin" TNM_NET = "B_phy_clk_rx"; |
---|
717 | TIMEGRP "B_v6_emac_v1_3_clk_phy_rx" = "B_phy_clk_rx"; |
---|
718 | TIMESPEC "TS_B_v6_emac_v1_3_clk_phy_rx" = PERIOD "B_v6_emac_v1_3_clk_phy_rx" 7.5 ns HIGH 50 %; |
---|
719 | |
---|
720 | # Constrain the DCR interface clock to an example frequency of 100 MHz |
---|
721 | # Changed NET Name |
---|
722 | # NET "DCREMACCLK" TNM_NET = "host_clock"; |
---|
723 | NET "*ETH_B*/SPLB_CLK" TNM_NET = "host_clock"; |
---|
724 | TIMEGRP "B_clk_host" = "B_host_clock"; |
---|
725 | TIMESPEC "TS_B_clk_host" = PERIOD "B_clk_host" 10 ns HIGH 50 %; |
---|
726 | |
---|
727 | ############################################################################### |
---|
728 | # PHYSICAL INTERFACE CONSTRAINTS |
---|
729 | # The following constraints are necessary for proper operation, and are tuned |
---|
730 | # for this example design. They should be modified to suit your design. |
---|
731 | ############################################################################### |
---|
732 | |
---|
733 | # RGMII physical interface constraints |
---|
734 | # ----------------------------------------------------------------------------- |
---|
735 | |
---|
736 | # Set the IDELAY and ODELAY values, tuned for this example design. |
---|
737 | # These values should be modified to suit your design. |
---|
738 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
---|
739 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
---|
740 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
---|
741 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
---|
742 | # original assuming equal trace lengths INST "*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
---|
743 | |
---|
744 | INST "*ETH_B*rgmii?rgmii_rx_ctl_delay" IDELAY_VALUE = 13; |
---|
745 | INST "*ETH_B*rgmii?rgmii_rx_d0_delay" IDELAY_VALUE = 13; |
---|
746 | INST "*ETH_B*rgmii?rgmii_rx_d1_delay" IDELAY_VALUE = 13; |
---|
747 | INST "*ETH_B*rgmii?rgmii_rx_d2_delay" IDELAY_VALUE = 13; |
---|
748 | INST "*ETH_B*rgmii?rgmii_rx_d3_delay" IDELAY_VALUE = 13; |
---|
749 | |
---|
750 | INST "*ETH_B*rgmii_rxc0_delay" IDELAY_VALUE = 0; |
---|
751 | INST "*ETH_B*rgmii_rxc0_delay" SIGNAL_PATTERN = CLOCK; |
---|
752 | |
---|
753 | INST "*ETH_B*rgmii?rgmii_tx_clk_delay" ODELAY_VALUE = 6; |
---|
754 | INST "*ETH_B*rgmii?rgmii_tx_clk_delay" SIGNAL_PATTERN = CLOCK; |
---|
755 | |
---|
756 | # Group all IODELAY-related blocks to use a single IDELAYCTRL |
---|
757 | |
---|
758 | # Change - added TNMs for trace length variations |
---|
759 | INST "ETH_B_RGMII_RXD_0_pin[0]" TNM = "B_rgmii_rx_d0"; |
---|
760 | INST "ETH_B_RGMII_RXD_0_pin[1]" TNM = "B_rgmii_rx_d1"; |
---|
761 | INST "ETH_B_RGMII_RXD_0_pin[2]" TNM = "B_rgmii_rx_d2"; |
---|
762 | INST "ETH_B_RGMII_RXD_0_pin[3]" TNM = "B_rgmii_rx_d3"; |
---|
763 | INST "ETH_B_RGMII_RX_CTL_0_pin" TNM = "B_rgmii_rx_ctrl"; |
---|
764 | |
---|
765 | # Spec: 1.2ns setup time, 1.2ns hold time |
---|
766 | # The internal PHY delays were not used to derive the OFFSET constraints |
---|
767 | # Changed NET Name |
---|
768 | # This signal trace is longer than the clock trace, and arrives at the FPGA pin 64 ps after the clock |
---|
769 | # Therefore the offset in constraint must have less setup time than nominal |
---|
770 | TIMEGRP "B_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
---|
771 | TIMEGRP "B_rgmii_rx_d0" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
---|
772 | |
---|
773 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 376 ps before the clock |
---|
774 | # Therefore the offset in constraint must have more setup time than nominal |
---|
775 | TIMEGRP "B_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
---|
776 | TIMEGRP "B_rgmii_rx_d1" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
---|
777 | |
---|
778 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 372 ps before the clock |
---|
779 | # Therefore the offset in constraint must have more setup time than nominal |
---|
780 | TIMEGRP "B_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
---|
781 | TIMEGRP "B_rgmii_rx_d2" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
---|
782 | |
---|
783 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 115 ps before the clock |
---|
784 | # Therefore the offset in constraint must have more setup time than nominal |
---|
785 | TIMEGRP "B_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
---|
786 | TIMEGRP "B_rgmii_rx_d3" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
---|
787 | |
---|
788 | # This signal trace is shorter than the clock trace, and arrives at the FPGA pin 292 ps before the clock |
---|
789 | # Therefore the offset in constraint must have more setup time than nominal |
---|
790 | TIMEGRP "B_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" RISING; |
---|
791 | TIMEGRP "B_rgmii_rx_ctrl" OFFSET = IN 1.2 ns VALID 2.4 ns BEFORE "ETH_B_RGMII_RXC_0_pin" FALLING; |
---|
792 | |
---|
793 | |
---|
794 | NET "*ETH_B*/LlinkTemac0_CLK" TNM_NET = "B_LLCLK0"; #name of signal connected to TEMAC LlinkTemac0_CLK input |
---|
795 | NET "*ETH_B*/SPLB_Clk" TNM_NET = "B_PLBCLK"; #name of signal connected to TEMAC SPLB_Clk input |
---|
796 | |
---|
797 | TIMESPEC "TS_B_LL_CLK0_2_RX_CLIENT_CLK0" = FROM B_LLCLK0 TO B_phy_clk_rx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
---|
798 | TIMESPEC "TS_B_LL_CLK0_2_TX_CLIENT_CLK0" = FROM B_LLCLK0 TO B_phy_clk_tx 8000 ps DATAPATHONLY; #constant value based on Ethernet clock |
---|
799 | TIMESPEC "TS_B_RX_CLIENT_CLK0_2_LL_CLK0" = FROM B_phy_clk_rx TO B_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
---|
800 | TIMESPEC "TS_B_TX_CLIENT_CLK0_2_LL_CLK0" = FROM B_phy_clk_tx TO B_LLCLK0 8000 ps DATAPATHONLY; #varies based on period of LocalLink clock |
---|
801 | |
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802 | ###### DDR3_2GB_SODIMM |
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803 | #2012-Apr-2: |
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804 | # -Started with old UCF snippet from early FPGA pinout testing |
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805 | # -Updated LOC constraints to match MIG 13.4 design which met timing for 2GB SO-DIMM (-1 @ 400MHz, -2 @ 533MHz) |
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806 | |
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807 | ###### DDR3_SDRAM |
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808 | |
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809 | # Constrain BUFR clocks used to synchronize data from IOB to fabric logic |
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810 | # Note that ISE cannot infer this from other PERIOD constraints because |
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811 | # of the use of OSERDES blocks in the BUFR clock generation path |
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812 | NET "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/clk_rsync[?]" TNM_NET = TNM_clk_rsync; |
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813 | TIMESPEC "TS_clk_rsync" = PERIOD "TNM_clk_rsync" 5000 ps; # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0 |
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814 | |
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815 | # Paths between DQ/DQS ISERDES.Q outputs and CLB flops clocked by falling |
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816 | # edge of BUFR will by design only be used if DYNCLKDIVSEL is asserted for |
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817 | # that particular flop. Mark this path as being a full-cycle, rather than |
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818 | # a half cycle path for timing purposes. NOTE: This constraint forces full- |
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819 | # cycle timing to be applied globally for all rising->falling edge paths |
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820 | # in all resynchronizaton clock domains. If the user had modified the logic |
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821 | # in the resync clock domain such that other rising->falling edge paths |
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822 | # exist, then constraint below should be modified to utilize pattern |
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823 | # matching to specific affect only the DQ/DQS ISERDES.Q outputs |
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824 | TIMEGRP "TG_clk_rsync_rise" = RISING "TNM_clk_rsync"; |
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825 | TIMEGRP "TG_clk_rsync_fall" = FALLING "TNM_clk_rsync"; |
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826 | TIMESPEC "TS_clk_rsync_rise_to_fall" = FROM "TG_clk_rsync_rise" TO "TG_clk_rsync_fall" 5000 ps; # This is over-constraint for 200MHz, user can relax it to match mpmc_clk0 |
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827 | |
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828 | # Signal to select between controller and physical layer signals. Four divided by two clock |
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829 | # cycles (4 memory clock cycles) are provided by design for the signal to settle down. |
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830 | # Used only by the phy modules. |
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831 | INST "*/mpmc_core_0/gen_v6_ddr3_phy.mpmc_phy_if_0/u_phy_init/u_ff_phy_init_data_sel" TNM = "TNM_PHY_INIT_SEL"; |
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832 | TIMESPEC "TS_MC_PHY_INIT_SEL" = FROM "TNM_PHY_INIT_SEL" TO FFS = 10000 ps; # This is over-constraint, user can relax it to match 4 memory clock cycles |
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833 | |
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834 | #Internal Vref |
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835 | CONFIG INTERNAL_VREF_BANK22=0.75; |
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836 | CONFIG INTERNAL_VREF_BANK23=0.75; |
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837 | CONFIG INTERNAL_VREF_BANK33=0.75; |
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838 | |
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839 | #DCI Cascading |
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840 | CONFIG DCI_CASCADE = "23 22"; |
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841 | |
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842 | #BUFR IOBs (must be unconnected in FPGA and PCB) |
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843 | CONFIG PROHIBIT = AH17,AP20; |
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844 | |
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845 | #BUFIO IOBs (must be unconnected in FPGA and PCB) |
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846 | CONFIG PROHIBIT = AC13,AD12,AF19,AF20,AH23,AK27,AN27,AP11; |
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847 | |
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848 | ###################################################################################### |
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849 | ##Place RSYNC OSERDES and IODELAY: ## |
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850 | ###################################################################################### |
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851 | |
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852 | #MPMC as of EDK 13.4 only supports 32-bit memories |
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853 | ##Site: AH17 -- Bank 32 |
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854 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_oserdes_rsync" LOC = "OLOGIC_X2Y23"; |
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855 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync" LOC = "IODELAY_X2Y23"; |
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856 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_bufr_rsync" LOC = "BUFR_X2Y1"; |
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857 | |
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858 | ##Site: AP20 -- Bank 22 |
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859 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_oserdes_rsync" LOC = "OLOGIC_X1Y21"; |
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860 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync" LOC = "IODELAY_X1Y21"; |
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861 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_bufr_rsync" LOC = "BUFR_X1Y1"; |
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862 | |
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863 | |
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864 | ###################################################################################### |
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865 | ##Place CPT OSERDES and IODELAY: ## |
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866 | ###################################################################################### |
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867 | |
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868 | ##Site: AH23 -- Bank 23 |
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869 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_oserdes_cpt" LOC = "OLOGIC_X1Y57"; |
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870 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[0].u_odelay_cpt" LOC = "IODELAY_X1Y57"; |
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871 | |
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872 | ##Site: AK27 -- Bank 23 |
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873 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_oserdes_cpt" LOC = "OLOGIC_X1Y59"; |
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874 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[1].u_odelay_cpt" LOC = "IODELAY_X1Y59"; |
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875 | |
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876 | ##Site: AN27 -- Bank 23 |
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877 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_oserdes_cpt" LOC = "OLOGIC_X1Y61"; |
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878 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[2].u_odelay_cpt" LOC = "IODELAY_X1Y61"; |
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879 | |
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880 | ##Site: AF19 -- Bank 22 |
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881 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_oserdes_cpt" LOC = "OLOGIC_X1Y23"; |
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882 | INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[3].u_odelay_cpt" LOC = "IODELAY_X1Y23"; |
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883 | |
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884 | #MPMC as of EDK 13.4 only supports 32-bit memories |
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885 | ##Site: AF20 -- Bank 22 |
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886 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_oserdes_cpt" LOC = "OLOGIC_X1Y17"; |
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887 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[4].u_odelay_cpt" LOC = "IODELAY_X1Y17"; |
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888 | |
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889 | ##Site: AP11 -- Bank 33 |
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890 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_oserdes_cpt" LOC = "OLOGIC_X2Y57"; |
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891 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[5].u_odelay_cpt" LOC = "IODELAY_X2Y57"; |
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892 | |
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893 | ##Site: AC13 -- Bank 33 |
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894 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_oserdes_cpt" LOC = "OLOGIC_X2Y61"; |
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895 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[6].u_odelay_cpt" LOC = "IODELAY_X2Y61"; |
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896 | |
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897 | ##Site: AD12 -- Bank 33 |
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898 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_oserdes_cpt" LOC = "OLOGIC_X2Y59"; |
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899 | #INST "*/u_phy_read/u_phy_rdclk_gen/gen_ck_cpt[7].u_odelay_cpt" LOC = "IODELAY_X2Y59"; |
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900 | |
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901 | |
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