[1929] | 1 | //////////////////////////////////////////////////////////////////////////////// |
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| 2 | // Copyright (c) 2004 Xilinx, Inc. All rights reserved. |
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| 3 | // |
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| 4 | // Xilinx, Inc. |
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| 5 | // XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A |
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| 6 | // COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS |
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| 7 | // ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR |
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| 8 | // STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION |
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| 9 | // IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE |
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| 10 | // FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. |
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| 11 | // XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO |
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| 12 | // THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO |
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| 13 | // ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE |
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| 14 | // FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY |
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| 15 | // AND FITNESS FOR A PARTICULAR PURPOSE. |
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| 16 | // |
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| 17 | // File : eth.c |
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| 18 | // Date : 2002, March 20. |
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| 19 | // Author : Sathya Thammanur |
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| 20 | // Company: Xilinx |
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| 21 | // Group : Emerging Software Technologies |
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| 22 | // |
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| 23 | // Summary: |
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| 24 | // Ethernet layer specific functions |
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| 25 | // |
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| 26 | // $Id: eth.c,v 1.2.8.6 2005/11/15 23:41:10 salindac Exp $ |
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| 27 | // |
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| 28 | //////////////////////////////////////////////////////////////////////////////// |
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| 29 | |
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| 30 | //////////////////////////////////////////////////////////////////////////////// |
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| 31 | // see copyright.txt for Rice University/Mango Communications modifications |
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| 32 | //////////////////////////////////////////////////////////////////////////////// |
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| 33 | |
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| 34 | #include <string.h> |
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| 35 | #include <xilnet_config.h> |
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| 36 | #include <xilnet_xilsock.h> |
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| 37 | #ifdef _CONFIG_TEMAC_ |
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| 38 | #include "xlltemac.h" |
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| 39 | #include "xllfifo.h" |
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| 40 | #include "xdmacentral.h" |
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| 41 | #include "xdmacentral_l.h" |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifdef _CONFIG_AXI_ETHERNET_FIFO |
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| 45 | #include "xaxiethernet.h" /* defines Axi Ethernet APIs */ |
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| 46 | #include "xllfifo.h" |
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| 47 | #endif |
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| 48 | #include "xio.h" |
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| 49 | #include "stdio.h" |
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| 50 | struct xilnet_hw_addr_table xilnet_hw_tbl[HW_ADDR_TBL_ENTRIES]; |
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| 51 | unsigned char ishwaddrinit = 0; |
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| 52 | static unsigned long long curr_age = 0; |
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| 53 | |
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| 54 | |
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| 55 | /* |
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| 56 | * initialize xilnet hardware address |
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| 57 | */ |
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| 58 | void xilnet_eth_init_hw_addr(unsigned char* addr) { |
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| 59 | int k = 0; |
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| 60 | int j; |
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| 61 | int sum = 0; |
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| 62 | int val = 0; |
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| 63 | |
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| 64 | for (j = 0; j < 5; j++) { |
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| 65 | |
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| 66 | // parse input for colon separated hw address |
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| 67 | while(addr[k] != ':') { |
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| 68 | if (addr[k] >= 'a' && addr[k] <= 'f') |
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| 69 | val = addr[k] - 'a' + 10; |
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| 70 | else if (addr[k] >= 'A' && addr[k] <= 'F') |
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| 71 | val = addr[k] - 'A' + 10; |
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| 72 | else |
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| 73 | val = addr[k] - '0'; |
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| 74 | sum = sum * 16 + val; |
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| 75 | k++; |
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| 76 | } |
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| 77 | |
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| 78 | k++; // move over the colon |
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| 79 | node_hw_addr[j] = (unsigned char) sum; |
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| 80 | sum = 0; |
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| 81 | } |
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| 82 | |
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| 83 | // read last byte of hw address |
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| 84 | while (addr[k] != '\0') { |
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| 85 | if (addr[k] >= 'a' && addr[k] <= 'f') |
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| 86 | val = addr[k] - 'a' + 10; |
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| 87 | else if (addr[k] >= 'A' && addr[k] <= 'F') |
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| 88 | val = addr[k] - 'A' + 10; |
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| 89 | else |
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| 90 | val = addr[k] - '0'; |
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| 91 | sum = sum * 16 + val; |
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| 92 | k++; |
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| 93 | } |
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| 94 | node_hw_addr[5] = (unsigned char) sum; |
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| 95 | } |
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| 96 | |
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| 97 | #ifdef _CONFIG_TEMAC_ |
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| 98 | inline void waitForDMA() |
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| 99 | { |
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| 100 | |
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| 101 | int RegValue; |
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| 102 | |
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| 103 | //Wait until the DMA transfer is done by checking the Status register |
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| 104 | do {RegValue = XDmaCentral_GetStatus((XDmaCentral *)DMA_CENTRAL_INST);} |
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| 105 | while ((RegValue & XDMC_DMASR_BUSY_MASK) == XDMC_DMASR_BUSY_MASK); |
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| 106 | |
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| 107 | return; |
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| 108 | } |
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| 109 | #endif |
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| 110 | |
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| 111 | /* |
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| 112 | * Receive frame |
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| 113 | */ |
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| 114 | int xilnet_eth_recv_frame(unsigned char *buf, int len) { |
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| 115 | |
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| 116 | struct xilnet_eth_hdr *eth; |
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| 117 | //unsigned short RxPktLength; |
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| 118 | int size = -1; |
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| 119 | void* pktBufPtr; |
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| 120 | |
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| 121 | pktBufPtr = buf; |
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| 122 | |
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| 123 | //device specific routine for getting a frame |
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| 124 | |
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| 125 | #ifdef _CONFIG_EMACLITE_ |
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| 126 | size = XEmacLite_RecvFrame(MYMAC_BASEADDR, buf); |
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| 127 | #endif |
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| 128 | #ifdef _CONFIG_TEMAC_ |
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| 129 | if(XLlFifo_IsRxEmpty((XLlFifo *)FIFO_INST)) |
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| 130 | { |
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| 131 | size=-1; |
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| 132 | } |
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| 133 | else |
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| 134 | { |
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| 135 | if(XLlFifo_RxOccupancy((XLlFifo *)FIFO_INST)) |
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| 136 | { |
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| 137 | waitForDMA(); |
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| 138 | //Set DMA to non-increment source, increment dest addresses |
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| 139 | XDmaCentral_SetControl((XDmaCentral *)DMA_CENTRAL_INST, XDMC_DMACR_DEST_INCR_MASK); |
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| 140 | size = XLlFifo_RxGetLen((XLlFifo *)FIFO_INST); |
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| 141 | XDmaCentral_Transfer((XDmaCentral *)DMA_CENTRAL_INST, |
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| 142 | (u8 *)(((XLlFifo *)FIFO_INST)->BaseAddress+XLLF_RDFD_OFFSET), |
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| 143 | (u8 *)pktBufPtr, |
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| 144 | size); |
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| 145 | } |
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| 146 | } |
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| 147 | #endif |
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| 148 | #ifdef _CONFIG_AXI_ETHERNET_FIFO |
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| 149 | if(XLlFifo_IsRxEmpty((XLlFifo *)FIFO_INST)) |
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| 150 | { |
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| 151 | size=-1; |
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| 152 | } |
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| 153 | else |
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| 154 | { |
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| 155 | if(XLlFifo_RxOccupancy((XLlFifo *)FIFO_INST)) |
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| 156 | { |
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| 157 | size = XLlFifo_RxGetLen((XLlFifo *)FIFO_INST); |
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| 158 | XLlFifo_Read((XLlFifo *)FIFO_INST, pktBufPtr, size); |
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| 159 | } |
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| 160 | } |
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| 161 | #endif |
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| 162 | |
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| 163 | #ifdef _DEBUG_ |
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| 164 | xil_printf("Ethernet Recvd Frame of size %d...\r\n", size); |
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| 165 | xil_printf("src : %d%d%d%d%d%d...\r\n", buf[0], buf[1],buf[2],buf[3],buf[4],buf[5]); |
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| 166 | xil_printf("dst : %d%d%d%d%d%d...\r\n", buf[6], buf[7],buf[8],buf[9],buf[10],buf[11]); |
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| 167 | xil_printf("type : %d%d...\r\n", buf[12], buf[13]); |
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| 168 | #endif |
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| 169 | |
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| 170 | //} |
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| 171 | |
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| 172 | |
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| 173 | // Strip off the FCS(or CRC) from the received frame |
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| 174 | //buf[size-1] = 0; |
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| 175 | //buf[size-2] = 0; |
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| 176 | //buf[size-3] = 0; |
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| 177 | //buf[size-4] = 0; |
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| 178 | size -= 4; |
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| 179 | |
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| 180 | |
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| 181 | if(size>0){ |
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| 182 | eth = (struct xilnet_eth_hdr*) buf; |
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| 183 | |
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| 184 | switch (Xil_Ntohs(eth->type)) { |
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| 185 | case ETH_PROTO_IP: |
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| 186 | return (xilnet_ip(buf, size)); |
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| 187 | case ETH_PROTO_ARP: |
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| 188 | return (xilnet_arp(buf, size)); |
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| 189 | default: |
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| 190 | #ifdef _DEBUG_ |
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| 191 | xil_printf("Unknown protocol %x...\r\n", eth->type); |
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| 192 | #endif |
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| 193 | break; |
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| 194 | } |
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| 195 | } |
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| 196 | return -1; |
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| 197 | } |
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| 198 | |
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| 199 | |
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| 200 | /* |
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| 201 | * Send frame to peer ip addr, peer hw addr |
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| 202 | */ |
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| 203 | |
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| 204 | |
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| 205 | int xilnet_eth_send_frame(unsigned char *pkt, int len, unsigned char *dip_addr, |
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| 206 | void *dhw_addr, unsigned short type) |
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| 207 | { |
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| 208 | int i; |
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| 209 | int hw_tbl_index = 0; |
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| 210 | |
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| 211 | for (i = 0; i < ETH_ADDR_LEN; i++) { |
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| 212 | ((struct xilnet_eth_hdr*)pkt)->src_addr[i] = node_hw_addr[i]; |
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| 213 | } |
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| 214 | |
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| 215 | if (dhw_addr) |
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| 216 | memcpy(((struct xilnet_eth_hdr*)pkt)->dest_addr, dhw_addr, ETH_ADDR_LEN); |
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| 217 | else { |
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| 218 | // find the hw tbl entry index corr to dip_addr |
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| 219 | hw_tbl_index = xilnet_eth_get_hw_addr(dip_addr); |
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| 220 | |
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| 221 | for (i = 0; i < ETH_ADDR_LEN; i++) { |
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| 222 | ((struct xilnet_eth_hdr*)pkt)->dest_addr[i] = xilnet_hw_tbl[hw_tbl_index].hw_addr[i]; |
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| 223 | } |
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| 224 | } |
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| 225 | ((struct xilnet_eth_hdr*)pkt)->type = Xil_Htons(type); |
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| 226 | |
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| 227 | // pad the ethernet frame if < 60 bytes |
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| 228 | if (len < 60) { |
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| 229 | for(i = len; i < ETH_MIN_FRAME_LEN; i++) { |
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| 230 | pkt[i] = 0; |
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| 231 | } |
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| 232 | len = ETH_MIN_FRAME_LEN; |
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| 233 | } |
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| 234 | // Write to MAC |
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| 235 | #ifdef _CONFIG_EMACLITE_ |
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| 236 | XEmacLite_SendFrame(MYMAC_BASEADDR, pkt, len); |
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| 237 | #endif |
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| 238 | #ifdef _CONFIG_TEMAC_ |
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| 239 | waitForDMA(); |
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| 240 | //Set DMA to increment src, non-increment dest addresses |
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| 241 | XDmaCentral_SetControl((XDmaCentral *)DMA_CENTRAL_INST, XDMC_DMACR_SOURCE_INCR_MASK); |
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| 242 | //Transfer the packet into the LLFIFO |
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| 243 | XDmaCentral_Transfer((XDmaCentral *)DMA_CENTRAL_INST, |
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| 244 | (u8 *)(pkt), |
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| 245 | (u8 *)(((XLlFifo *)FIFO_INST)->BaseAddress + XLLF_TDFD_OFFSET), |
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| 246 | len); |
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| 247 | waitForDMA(); |
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| 248 | //Write the length to the LL_FIFO; this write initiates the TEMAC transmission |
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| 249 | // XIo_Out32( (FIFO_BASEADDR + XLLF_TLF_OFFSET), len); |
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| 250 | XLlFifo_TxSetLen((XLlFifo *)FIFO_INST, len); |
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| 251 | |
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| 252 | //xil_printf("xilnet_eth_send_frame(), len = %d \r\n",len); |
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| 253 | #endif |
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| 254 | #ifdef _CONFIG_AXI_ETHERNET_FIFO |
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| 255 | |
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| 256 | XLlFifo_Write((XLlFifo *)FIFO_INST, pkt, len); |
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| 257 | |
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| 258 | //Write the length to the LL_FIFO; this write initiates the TEMAC transmission |
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| 259 | // XIo_Out32( (FIFO_BASEADDR + XLLF_TLF_OFFSET), len); |
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| 260 | XLlFifo_TxSetLen((XLlFifo *)FIFO_INST, len); |
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| 261 | |
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| 262 | //xil_printf("xilnet_eth_send_frame(), len = %d \r\n",len); |
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| 263 | #endif |
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| 264 | |
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| 265 | |
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| 266 | return len; |
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| 267 | } |
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| 268 | |
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| 269 | |
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| 270 | /* |
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| 271 | * Update Hardware Address Table |
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| 272 | */ |
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| 273 | |
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| 274 | void xilnet_eth_update_hw_tbl(unsigned char *buf, int proto) { |
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| 275 | |
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| 276 | unsigned char ip[IP_VERSION]; |
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| 277 | unsigned char hw[ETH_ADDR_LEN]; |
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| 278 | int i, j; |
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| 279 | //struct xilnet_eth_hdr *eth = (struct xilnet_eth_hdr*) buf; |
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| 280 | |
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| 281 | // Update the current age |
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| 282 | curr_age++; |
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| 283 | |
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| 284 | // get hw addr |
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| 285 | for (i = 0; i < ETH_ADDR_LEN; i++) { |
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| 286 | hw[i] = ((struct xilnet_eth_hdr*)buf)->src_addr[i]; |
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| 287 | } |
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| 288 | |
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| 289 | // get ip addr |
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| 290 | switch (proto) { |
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| 291 | case ETH_PROTO_ARP: |
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| 292 | for (i = 0; i < IP_VERSION; i++) { |
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| 293 | ip[i] = (buf+ETH_HDR_LEN)[ARP_SIP_OFFSET+i]; |
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| 294 | } |
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| 295 | break; |
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| 296 | case ETH_PROTO_IP: |
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| 297 | for (i = 0; i < IP_VERSION; i++) { |
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| 298 | ip[i] = (buf+ETH_HDR_LEN)[IP_SADDR_BASE+i]; |
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| 299 | } |
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| 300 | break; |
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| 301 | } |
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| 302 | |
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| 303 | // update the hw addr table |
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| 304 | |
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| 305 | for (i = 0; i < HW_ADDR_TBL_ENTRIES; i++) { |
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| 306 | if (xilnet_hw_tbl[i].flag) { |
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| 307 | if ( (hw[0] == xilnet_hw_tbl[i].hw_addr[0]) && |
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| 308 | (hw[1] == xilnet_hw_tbl[i].hw_addr[1]) && |
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| 309 | (hw[2] == xilnet_hw_tbl[i].hw_addr[2]) && |
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| 310 | (hw[3] == xilnet_hw_tbl[i].hw_addr[3]) && |
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| 311 | (hw[4] == xilnet_hw_tbl[i].hw_addr[4]) && |
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| 312 | (hw[5] == xilnet_hw_tbl[i].hw_addr[5]) |
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| 313 | ) { |
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| 314 | for (j = 0; j < IP_VERSION; j++) |
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| 315 | xilnet_hw_tbl[i].ip_addr[j] = ip[j];; |
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| 316 | xilnet_hw_tbl[i].flag = HW_ADDR_ENTRY_IS_TRUE; |
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| 317 | xilnet_hw_tbl[i].age = curr_age; |
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| 318 | return; |
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| 319 | } |
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| 320 | } |
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| 321 | } |
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| 322 | xilnet_add_hw_tbl_entry(ip, hw); |
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| 323 | } |
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| 324 | |
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| 325 | |
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| 326 | /* |
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| 327 | * Add an entry into Hw Addr table |
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| 328 | */ |
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| 329 | |
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| 330 | void xilnet_add_hw_tbl_entry(unsigned char *ip, unsigned char *hw) |
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| 331 | { |
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| 332 | int i, j; |
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| 333 | |
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| 334 | for (i = 0; i < HW_ADDR_TBL_ENTRIES; i++) { |
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| 335 | if (!xilnet_hw_tbl[i].flag) { |
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| 336 | for (j = 0; j < ETH_ADDR_LEN; j++) { |
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| 337 | xilnet_hw_tbl[i].hw_addr[j] = hw[j]; |
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| 338 | } |
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| 339 | for (j = 0; j < IP_VERSION; j++) { |
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| 340 | xilnet_hw_tbl[i].ip_addr[j] = ip[j]; |
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| 341 | } |
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| 342 | xilnet_hw_tbl[i].flag = HW_ADDR_ENTRY_IS_TRUE; |
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| 343 | xilnet_hw_tbl[i].age = curr_age; |
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| 344 | return; |
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| 345 | } |
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| 346 | } |
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| 347 | |
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| 348 | // Find an old entry to be eliminated from hw tbl |
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| 349 | i = xilnet_eth_find_old_entry(); |
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| 350 | for (j = 0; j < ETH_ADDR_LEN; j++) { |
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| 351 | xilnet_hw_tbl[i].hw_addr[j] = hw[j]; |
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| 352 | } |
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| 353 | for (j = 0; j < IP_VERSION; j++) { |
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| 354 | xilnet_hw_tbl[i].ip_addr[j] = ip[j]; |
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| 355 | } |
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| 356 | xilnet_hw_tbl[i].flag = HW_ADDR_ENTRY_IS_TRUE; |
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| 357 | xilnet_hw_tbl[i].age = curr_age; |
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| 358 | |
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| 359 | } |
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| 360 | |
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| 361 | |
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| 362 | /* |
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| 363 | * Get index into hw tbl for ip_addr |
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| 364 | */ |
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| 365 | |
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| 366 | int xilnet_eth_get_hw_addr(unsigned char *ip) { |
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| 367 | |
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| 368 | int i; |
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| 369 | |
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| 370 | for (i = 0; i < HW_ADDR_TBL_ENTRIES; i++) { |
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| 371 | if (xilnet_hw_tbl[i].flag) |
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| 372 | if ( (ip[0] == xilnet_hw_tbl[i].ip_addr[0]) && |
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| 373 | (ip[1] == xilnet_hw_tbl[i].ip_addr[1]) && |
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| 374 | (ip[2] == xilnet_hw_tbl[i].ip_addr[2]) && |
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| 375 | (ip[3] == xilnet_hw_tbl[i].ip_addr[3]) ) { |
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| 376 | return i; |
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| 377 | } |
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| 378 | } |
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| 379 | |
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| 380 | xil_printf("Hw Addr Not found for IP \r\n"); |
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| 381 | return -1; |
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| 382 | |
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| 383 | } |
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| 384 | |
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| 385 | |
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| 386 | /* |
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| 387 | * Init the hw addr table |
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| 388 | */ |
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| 389 | |
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| 390 | void xilnet_eth_init_hw_addr_tbl() { |
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| 391 | |
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| 392 | int i; |
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| 393 | |
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| 394 | for (i = 0; i < HW_ADDR_TBL_ENTRIES; i++) { |
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| 395 | xilnet_hw_tbl[i].flag = HW_ADDR_ENTRY_IS_FALSE; |
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| 396 | xilnet_hw_tbl[i].age = 0; |
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| 397 | } |
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| 398 | |
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| 399 | ishwaddrinit = 1; |
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| 400 | } |
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| 401 | |
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| 402 | /* |
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| 403 | * Find the oldest entry in the Hw Table and |
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| 404 | * return its index |
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| 405 | */ |
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| 406 | |
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| 407 | int xilnet_eth_find_old_entry() |
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| 408 | { |
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| 409 | int i; |
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| 410 | int oldest_age = 0; |
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| 411 | int oldest = 0; |
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| 412 | |
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| 413 | for (i = 0; i < HW_ADDR_TBL_ENTRIES; i++) { |
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| 414 | |
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| 415 | if (curr_age - xilnet_hw_tbl[i].age > HW_ADDR_TBL_MAXAGE) { |
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| 416 | oldest = i; |
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| 417 | break; |
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| 418 | } |
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| 419 | else { |
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| 420 | if (( curr_age - xilnet_hw_tbl[i].age) > oldest_age) { |
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| 421 | oldest_age = curr_age - xilnet_hw_tbl[i].age; |
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| 422 | oldest = i; |
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| 423 | } |
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| 424 | } |
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| 425 | } |
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| 426 | |
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| 427 | return oldest; |
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| 428 | |
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| 429 | } |
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