source: edk_user_repository/WARP/sw_services/WARPxilnet_v3_02_a/src/xilnet_config.c

Last change on this file was 2053, checked in by welsh, 11 years ago

Adding WARPXilnet v 3.02.a library
File size: 5.4 KB
Line 
1
2/*******************************************************************
3*
4* CAUTION: This file is automatically generated by libgen.
5* Version: Xilinx EDK 14.4 EDK_P.49d
6* DO NOT EDIT.
7*
8* Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
9
10*
11* Description: XilNet MAC Configuration File
12*
13*******************************************************************/
14
15#include <string.h>
16#include <xilnet_config.h>
17
18// TODO:  FIX TEMAC for WARP V2
19#ifdef _CONFIG_TEMAC_
20#include "xlltemac.h"
21#include "xllfifo.h"
22#include "xdmacentral.h"
23#include "xdmacentral_l.h"
24#endif
25
26
27
28// Variables for ETH 0
29
30XLlFifo              ETH_0_FIFO_Instance;
31
32#if 0
33XAxiDma              ETH_0_DMA_Instance;
34
35// Aligned memory segments to be used for buffer descriptors
36char ETH_0_RX_BD_space[XILNET_ETH_0_RXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT)));
37char ETH_0_TX_BD_space[XILNET_ETH_0_RXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT)));
38#endif
39
40
41// Variables for ETH 1
42#if 0
43XLlFifo              ETH_1_FIFO_Instance;
44#endif
45
46XAxiDma              ETH_1_DMA_Instance;
47
48// Aligned memory segments to be used for buffer descriptors
49char ETH_1_RX_BD_space[XILNET_ETH_1_RXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT)));
50char ETH_1_TX_BD_space[XILNET_ETH_1_TXBD_SPACE_BYTES] __attribute__ ((aligned(XILNET_BD_ALIGNMENT)));
51
52
53
54// Ethernet Buffers
55
56// Buffers for ETH 0
57unsigned int recvBuffer_eth_0[XILNET_ETH_0_NUM_RECV_BUF*((XILNET_ETH_0_BUF_SIZE+3)/4)];
58unsigned int sendBuffer_eth_0[(XILNET_ETH_0_BUF_SIZE+3)/4];
59struct xilsock_socket xilsock_sockets_eth_0[NO_OF_XILSOCKS];
60struct xilnet_udp_conn xilnet_udp_conns_eth_0[XILNET_MAX_UDP_CONNS];
61
62// Buffers for ETH 1
63unsigned int recvBuffer_eth_1[XILNET_ETH_1_NUM_RECV_BUF*((XILNET_ETH_1_BUF_SIZE+3)/4)];
64unsigned int sendBuffer_eth_1[(XILNET_ETH_1_BUF_SIZE+3)/4];
65struct xilsock_socket  xilsock_sockets_eth_1[NO_OF_XILSOCKS];
66struct xilnet_udp_conn xilnet_udp_conns_eth_1[XILNET_MAX_UDP_CONNS];
67
68
69
70// Ethernet Device Structure
71xilnet_eth_device eth_device[XILNET_NUM_ETH_DEVICES];
72
73
74void xilnet_init_eth_device_struct(unsigned int eth_dev_num) {
75
76    switch( eth_dev_num ) {
77        case XILNET_ETH_0:
78            eth_device[eth_dev_num].inf_type             = XILNET_AXI_FIFO_INF;
79            eth_device[eth_dev_num].inf_id               = XILNET_ETH_0_INF_DEVICE_ID;
80            eth_device[eth_dev_num].inf_ref              = &ETH_0_FIFO_Instance;
81            eth_device[eth_dev_num].inf_cfg_ref          = 0;
82            eth_device[eth_dev_num].dma_rx_ring_ref      = 0;
83            eth_device[eth_dev_num].dma_tx_ring_ref      = 0;
84            eth_device[eth_dev_num].dma_rx_bd_ref        = 0;
85            eth_device[eth_dev_num].dma_tx_bd_ref        = 0;
86            eth_device[eth_dev_num].dma_rx_bd_cnt        = 0;
87            eth_device[eth_dev_num].dma_tx_bd_cnt        = 0;
88            eth_device[eth_dev_num].xilsock_status_flag  = 0;
89            eth_device[eth_dev_num].sync_IP_octet        = 255;
90            eth_device[eth_dev_num].is_xilsock_init      = 0;
91            eth_device[eth_dev_num].xilsock_sockets      = &xilsock_sockets_eth_0;
92            eth_device[eth_dev_num].is_udp_init          = 0;
93            eth_device[eth_dev_num].xilnet_udp_conns     = &xilnet_udp_conns_eth_0;
94            eth_device[eth_dev_num].buf_size             = XILNET_ETH_0_BUF_SIZE;
95            eth_device[eth_dev_num].num_recvbuf          = XILNET_ETH_0_NUM_RECV_BUF;
96            eth_device[eth_dev_num].recvbuf              = (unsigned int *)&recvBuffer_eth_0;
97            eth_device[eth_dev_num].sendbuf              = (unsigned int *)&sendBuffer_eth_0;
98        break;
99        case XILNET_ETH_1:
100            eth_device[eth_dev_num].inf_type             = XILNET_AXI_DMA_INF;
101            eth_device[eth_dev_num].inf_id               = XILNET_ETH_1_INF_DEVICE_ID;
102            eth_device[eth_dev_num].inf_ref              = &ETH_1_DMA_Instance;
103            eth_device[eth_dev_num].inf_cfg_ref          = 0;
104            eth_device[eth_dev_num].dma_rx_ring_ref      = 0;
105            eth_device[eth_dev_num].dma_tx_ring_ref      = 0;
106            eth_device[eth_dev_num].dma_rx_bd_ref        = &ETH_1_RX_BD_space;
107            eth_device[eth_dev_num].dma_tx_bd_ref        = &ETH_1_TX_BD_space;
108            eth_device[eth_dev_num].dma_rx_bd_cnt        = XILNET_ETH_1_RXBD_CNT;
109            eth_device[eth_dev_num].dma_tx_bd_cnt        = XILNET_ETH_1_TXBD_CNT;
110            eth_device[eth_dev_num].xilsock_status_flag  = 0;
111            eth_device[eth_dev_num].sync_IP_octet        = 255;
112            eth_device[eth_dev_num].is_xilsock_init      = 0;
113            eth_device[eth_dev_num].xilsock_sockets      = &xilsock_sockets_eth_1;
114            eth_device[eth_dev_num].is_udp_init          = 0;
115            eth_device[eth_dev_num].xilnet_udp_conns     = &xilnet_udp_conns_eth_1;
116            eth_device[eth_dev_num].buf_size             = XILNET_ETH_1_BUF_SIZE;
117            eth_device[eth_dev_num].num_recvbuf          = XILNET_ETH_1_NUM_RECV_BUF;
118            eth_device[eth_dev_num].recvbuf              = (unsigned int *)&recvBuffer_eth_1;
119            eth_device[eth_dev_num].sendbuf              = (unsigned int *)&sendBuffer_eth_1;
120            break;
121        default:
122            xil_printf("  **** ERROR:  Trying to initialize Ethernet device %d.  Only %d configured in the HW.", (eth_dev_num+1), XILNET_NUM_ETH_DEVICES);
123        break;
124    }
125}
126
127
128
129#ifdef __cplusplus
130}
131#endif
132
133
134
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