############################################################################
## This system.ucf file is generated by Base System Builder based on the
## settings in the selected Xilinx Board Definition file. Please add other
## user constraints to this file based on customer design specifications.
############################################################################

Net sys_clk_pin LOC=AH21;
Net sys_clk_pin IOSTANDARD = LVTTL;
Net sys_rst_pin LOC=AM16;
Net sys_rst_pin IOSTANDARD = LVTTL;
## System level constraints
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
Net sys_rst_pin TIG;
NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS  TIG;

## IO Devices constraints

#### Module LEDs_4Bit constraints

Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<0> LOC=AJ14;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<1> LOC=AM13;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<2> LOC=AR12;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<3> LOC=AH13;
Net fpga_0_LEDs_4Bit_GPIO_d_out_pin<3> IOSTANDARD = LVTTL;

#### Module Push_Buttons_4bit constraints

Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<0> LOC=AJ22;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<0> IOSTANDARD = LVTTL;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<1> LOC=AJ15;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<1> IOSTANDARD = LVTTL;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<2> LOC=AG18;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<2> IOSTANDARD = LVTTL;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<3> LOC=AG17;
Net fpga_0_Push_Buttons_4bit_GPIO_in_pin<3> IOSTANDARD = LVTTL;

#### Module RS232 constraints

Net fpga_0_RS232_RX_pin LOC=AA29;
Net fpga_0_RS232_RX_pin IOSTANDARD = LVTTL;
Net fpga_0_RS232_TX_pin LOC=AA28;
Net fpga_0_RS232_TX_pin IOSTANDARD = LVTTL;

