#FPGA Board v2.2 I/O constraints for User I/O Devices
#
# 8 LEDs directly controlled using the FPGA I/O pins (D10, D11, D13,
# D14, D18, D19, D20, D21)
NET LED<0> LOC = N24 | IOSTANDARD = LVCMOS25; #RED D11
NET LED<1> LOC = N20 | IOSTANDARD = LVCMOS25; #RED D14
NET LED<2> LOC = L18 | IOSTANDARD = LVCMOS25; #RED D19
NET LED<3> LOC = N18 | IOSTANDARD = LVCMOS25; #RED D21
NET LED<4> LOC = M18 | IOSTANDARD = LVCMOS25; #GREEN D10
NET LED<5> LOC = M25 | IOSTANDARD = LVCMOS25; #GREEN D13
NET LED<6> LOC = N19 | IOSTANDARD = LVCMOS25; #GREEN D18
NET LED<7> LOC = P19 | IOSTANDARD = LVCMOS25; #GREEN D20
#
# 5 pushbuttons arranged a cross orientation.
NET PUSHB_CENTER LOC = L23 | IOSTANDARD = LVCMOS25;
NET PUSHB_DOWN LOC = M21 | IOSTANDARD = LVCMOS25;
NET PUSHB_LEFT LOC = N22 | IOSTANDARD = LVCMOS25;
NET PUSHB_RIGHT LOC = M23 | IOSTANDARD = LVCMOS25;
NET PUSHB_UP LOC = N23 | IOSTANDARD = LVCMOS25;
#
# 4-bit DIP Switch (SW5)
NET DIPSW<0> LOC = M17 | IOSTANDARD = LVCMOS25;
NET DIPSW<1> LOC = R18 | IOSTANDARD = LVCMOS25;
NET DIPSW<2> LOC = P17 | IOSTANDARD = LVCMOS25;
NET DIPSW<3> LOC = M16 | IOSTANDARD = LVCMOS25;
#
# 2 IO Expanders that control the three hex displays (D30, D31, D32) and
# and 8 additional LEDs (D16, D17, D33, D34, D35, D36, D37, D38)
NET HEX_SDA LOC = AL18 | IOSTANDARD = LVCMOS33;
NET HEX_SCL LOC = AK17 | IOSTANDARD = LVCMOS33;