###################################################################
# Copyright (c) 2013 Mango Communications
# All Rights Reserved
# This code is covered by the WARP license
# See http://warpproject.org/license/ for details
###################################################################

BEGIN fmc_bb_4da_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = Mango FMC-BB-4DA bridge
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = ext_dac_ports, IO_TYPE = MANGO_4DABRIDGE_V1
IO_INTERFACE IO_IF = user_ports, IO_TYPE = MANGO_4DABRIDGE_V1

PARAMETER C_FAMILY = virtex6, DT = STRING

PARAMETER USER_DAC_A_BITS = 12, DT = INTEGER, RANGE = (12:16), DESC = "Bit width of user_DAC_A port; only 12 MSB will be used", PERMIT=BASE_USER
PARAMETER USER_DAC_B_BITS = 12, DT = INTEGER, RANGE = (12:16), DESC = "Bit width of user_DAC_B port; only 12 MSB will be used", PERMIT=BASE_USER
PARAMETER USER_DAC_C_BITS = 12, DT = INTEGER, RANGE = (12:16), DESC = "Bit width of user_DAC_C port; only 12 MSB will be used", PERMIT=BASE_USER
PARAMETER USER_DAC_D_BITS = 12, DT = INTEGER, RANGE = (12:16), DESC = "Bit width of user_DAC_D port; only 12 MSB will be used", PERMIT=BASE_USER

####################################################################################
## User Ports
## The user must connect sources to these ports in XPS in order to use
##  the 4DA board. The rest of the board's connections are made automatically
####################################################################################
PORT sys_samp_clk = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx, SIGIS = CLK, ASSIGNMENT = REQUIRE
PORT sys_samp_clk_90 = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx90, SIGIS = CLK, ASSIGNMENT = REQUIRE

PORT user_DAC_A = "", DIR = I, VEC = [0:USER_DAC_A_BITS-1], IO_IF = user_ports, IO_IS = user_DAC_A
PORT user_DAC_B = "", DIR = I, VEC = [0:USER_DAC_B_BITS-1], IO_IF = user_ports, IO_IS = user_DAC_B

PORT user_DAC_C = "", DIR = I, VEC = [0:USER_DAC_C_BITS-1], IO_IF = user_ports, IO_IS = user_DAC_C
PORT user_DAC_D = "", DIR = I, VEC = [0:USER_DAC_D_BITS-1], IO_IF = user_ports, IO_IS = user_DAC_D

####
# Bridge -> Board ports
####
PORT DAC_AB_DB = "", DIR = O, VEC = [13:0], IO_IS = DAC_AB_DB, ENDIAN = LITTLE, IO_IF = ext_dac_ports
PORT DAC_CD_DB = "", DIR = O, VEC = [13:0], IO_IS = DAC_AB_DB, ENDIAN = LITTLE, IO_IF = ext_dac_ports

PORT DAC_AB_CLK = "", DIR = O, IO_IS = DAC_AB_CLK, IO_IF = ext_dac_ports
PORT DAC_CD_CLK = "", DIR = O, IO_IS = DAC_AB_CLK, IO_IF = ext_dac_ports

PORT DAC_AB_PINMD = "", DIR = O, IO_IS = DAC_AB_PINMD, IO_IF = ext_dac_ports
PORT DAC_AB_CLKMD = "", DIR = O, IO_IS = DAC_AB_CLKMD, IO_IF = ext_dac_ports
PORT DAC_AB_FORMAT = "", DIR = O, IO_IS = DAC_AB_FORMAT, IO_IF = ext_dac_ports
PORT DAC_AB_PWDN = "", DIR = O, IO_IS = DAC_AB_PWDN, IO_IF = ext_dac_ports

PORT DAC_CD_PINMD = "", DIR = O, IO_IS = DAC_CD_PINMD, IO_IF = ext_dac_ports
PORT DAC_CD_CLKMD = "", DIR = O, IO_IS = DAC_CD_CLKMD, IO_IF = ext_dac_ports
PORT DAC_CD_FORMAT = "", DIR = O, IO_IS = DAC_CD_FORMAT, IO_IF = ext_dac_ports
PORT DAC_CD_PWDN = "", DIR = O, IO_IS = DAC_CD_PWDN, IO_IF = ext_dac_ports
	
END
