###################################################################
##
## Name     : null_pair_example
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
###################################################################

BEGIN mgt_null_controller

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex4=DEVELOPMENT, others=OBSOLETE)
OPTION IP_GROUP = USER
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE

PARAMETER enable_null_mgt02 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 102, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
PARAMETER enable_null_mgt12 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 112, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
PARAMETER enable_null_mgt13 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 113, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER
PARAMETER enable_null_mgt14 = 1, DT = INTEGER, DESC = Enable Null MGT Wrapper for Tile 114, VALUES = (0=Disable, 1=Enable), PERMIT = BASE_USER

## Bus Interfaces

## Generics for VHDL or Parameters for Verilog

## Ports
PORT grefclk = "", DIR = I
PORT rxn_mgt01 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt01 = "", DIR = I, VEC = [0:1]
PORT txn_mgt01 = "", DIR = O, VEC = [0:1]
PORT txp_mgt01 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt02 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt02 = "", DIR = I, VEC = [0:1]
PORT txn_mgt02 = "", DIR = O, VEC = [0:1]
PORT txp_mgt02 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt03 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt03 = "", DIR = I, VEC = [0:1]
PORT txn_mgt03 = "", DIR = O, VEC = [0:1]
PORT txp_mgt03 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt05 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt05 = "", DIR = I, VEC = [0:1]
PORT txn_mgt05 = "", DIR = O, VEC = [0:1]
PORT txp_mgt05 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt06 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt06 = "", DIR = I, VEC = [0:1]
PORT txn_mgt06 = "", DIR = O, VEC = [0:1]
PORT txp_mgt06 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt09 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt09 = "", DIR = I, VEC = [0:1]
PORT txn_mgt09 = "", DIR = O, VEC = [0:1]
PORT txp_mgt09 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt10 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt10 = "", DIR = I, VEC = [0:1]
PORT txn_mgt10 = "", DIR = O, VEC = [0:1]
PORT txp_mgt10 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt12 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt12 = "", DIR = I, VEC = [0:1]
PORT txn_mgt12 = "", DIR = O, VEC = [0:1]
PORT txp_mgt12 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt13 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt13 = "", DIR = I, VEC = [0:1]
PORT txn_mgt13 = "", DIR = O, VEC = [0:1]
PORT txp_mgt13 = "", DIR = O, VEC = [0:1]
PORT rxn_mgt14 = "", DIR = I, VEC = [0:1]
PORT rxp_mgt14 = "", DIR = I, VEC = [0:1]
PORT txn_mgt14 = "", DIR = O, VEC = [0:1]
PORT txp_mgt14 = "", DIR = O, VEC = [0:1]

END
