###################################################################
# Copyright (c) 2013 Mango Communications
# All Rights Reserved
# This code is covered by the WARP license
# See http://warpproject.org/license/ for details
###################################################################

BEGIN uart_mux

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = Mango UART Mux
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = ext_uart_ports, IO_TYPE = MANGO_UARTMUX_V1
IO_INTERFACE IO_IF = user_ports, IO_TYPE = MANGO_UARTMUX_V1

PARAMETER C_FAMILY = virtex6, DT = STRING

PARAMETER MIRROR_UART_RX = 0, DT = INTEGER, RANGE = (0:1), DESC = "Copy the UART input line to both UARTs; if 0 only the selected UART will receive data", PERMIT=BASE_USER

#Control input (0=select uart_0)
PORT uart_sel = "", DIR = I, IO_IF = user_ports, IO_IS = select, ASSIGNMENT = REQUIRE

#Two UART Tx inputs (uartlite -> mux)
PORT uart_0_tx = "", DIR = I, IO_IF = user_ports, IO_IS = uart_0_tx
PORT uart_1_tx = "", DIR = I, IO_IF = user_ports, IO_IS = uart_1_tx

#Two UART Rx outputs (mux -> uartlite)
PORT uart_0_rx = "", DIR = O, IO_IF = user_ports, IO_IS = uart_0_rx
PORT uart_1_rx = "", DIR = O, IO_IF = user_ports, IO_IS = uart_1_rx

#Top-level UART connections
# Tx = FPGA -> UART device
# Rx = UART device -> FPGA
PORT uart_tx = "", DIR = O, IO_IF = ext_uart_ports, IO_IS = uart_tx, ASSIGNMENT = REQUIRE
PORT uart_rx = "", DIR = I, IO_IF = ext_uart_ports, IO_IS = uart_rx, ASSIGNMENT = REQUIRE
	
END
