###################################################################
# Copyright (c) 2015 Mango Communications
# All Rights Reserved
# This code is covered by the WARP license
# See http://warpproject.org/license/ for details
###################################################################

BEGIN w3_ad_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = WARP v3 AD interface
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = ext_ad_ports, IO_TYPE = W3_ADBRIDGE_V1
IO_INTERFACE IO_IF = user_ports, IO_TYPE = W3_ADBRIDGE_V1

PARAMETER C_FAMILY = virtex6, DT = STRING

####################################################################################
## User Ports
## The user must connect sources/sinks to these ports in XPS in order to use
##  the analog interface board. The rest of the board's connections are made automatically
####################################################################################
PORT sys_samp_clk_RFA_Tx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxA, SIGIS = CLK
PORT sys_samp_clk_RFB_Tx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxB, SIGIS = CLK

PORT sys_samp_clk_RFA_Tx_90 = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx90A, SIGIS = CLK
PORT sys_samp_clk_RFB_Tx_90 = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkTx90B, SIGIS = CLK

PORT sys_samp_clk_RFA_Rx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkRxA, SIGIS = CLK
PORT sys_samp_clk_RFB_Rx = "", DIR = I, IO_IF = user_ports, IO_IS = sampClkRxB, SIGIS = CLK

PORT ad_RFA_TXCLK_out_en = "RF_AD_TXCLK_out_en", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxEnA
PORT ad_RFB_TXCLK_out_en = "RF_AD_TXCLK_out_en", DIR = I, IO_IF = user_ports, IO_IS = sampClkTxEnB

PORT user_RFA_RXD_I = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userARXDI
PORT user_RFA_RXD_Q = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userARXDQ

PORT user_RFA_TXD_I = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userATXDI
PORT user_RFA_TXD_Q = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userATXDQ

PORT user_RFA_TXIQ = "", DIR = I, IO_IF = user_ports, IO_IS = user_ATXIQ

PORT user_RFB_RXD_I = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userBRXDI
PORT user_RFB_RXD_Q = "", DIR = O, VEC = [0:11], IO_IF = user_ports, IO_IS = userBRXDQ

PORT user_RFB_TXD_I = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userBTXDI
PORT user_RFB_TXD_Q = "", DIR = I, VEC = [0:11], IO_IF = user_ports, IO_IS = userBTXDQ

PORT user_RFB_TXIQ = "", DIR = I, IO_IF = user_ports, IO_IS = user_BTXIQ

####
# Analog Bridge <-> Analog Board ports
####
PORT ad_RFA_TXD = "", DIR = O, VEC = [11:0], IO_IS = adATXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports
PORT ad_RFA_TXIQ = "", DIR = O, IO_IS = adATXIQ, IO_IF = ext_ad_ports
PORT ad_RFA_TXCLK = "", DIR = O, IO_IS = adATXCLK, IO_IF = ext_ad_ports

PORT ad_RFA_TRXD = "", DIR = I, VEC = [11:0], IO_IS = adATRXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports
PORT ad_RFA_TRXIQ = "", DIR = I, IO_IS = adATRXIQ, IO_IF = ext_ad_ports
PORT ad_RFA_TRXCLK = "", DIR = I, IO_IS = adATRXCLK, IO_IF = ext_ad_ports

PORT ad_RFB_TXD = "", DIR = O, VEC = [11:0], IO_IS = adATXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports
PORT ad_RFB_TXIQ = "", DIR = O, IO_IS = adATXIQ, IO_IF = ext_ad_ports
PORT ad_RFB_TXCLK = "", DIR = O, IO_IS = adATXCLK, IO_IF = ext_ad_ports

PORT ad_RFB_TRXD = "", DIR = I, VEC = [11:0], IO_IS = adBTRXD, ENDIAN = LITTLE, IO_IF = ext_ad_ports
PORT ad_RFB_TRXIQ = "", DIR = I, IO_IS = adBTRXIQ, IO_IF = ext_ad_ports
PORT ad_RFB_TRXCLK = "", DIR = I, IO_IS = adBTRXCLK, IO_IF = ext_ad_ports

END
