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##
## Name     : eeprom
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN eeprom

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = "EEPROM Controller based on Maxim OneWire Master core"
OPTION USAGE_LEVEL = BASE_USER #Enable this core in base system builder

IO_INTERFACE IO_IF = EEPROM, IO_TYPE = WARP_EEPROM_V1

## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_TYPE = SLAVE, BUS_STD = PLBV46

## Generics for VHDL or Parameters for Verilog
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 0, DT = INTEGER, RANGE = (0, 1)
PARAMETER C_FAMILY = virtex5, DT = STRING
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, BUS = SPLB, ADDRESS = BASE, PAIR = C_MEM0_HIGHADDR
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, BUS = SPLB, ADDRESS = HIGH, PAIR = C_MEM0_BASEADDR

## Ports
PORT DQ0 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ0_I, TRI_O = DQ0_O, TRI_T = DQ0_T
PORT DQ0_T = "", DIR = O
PORT DQ0_O = "", DIR = O
PORT DQ0_I = "", DIR = I

PORT DQ1 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ1_I, TRI_O = DQ1_O, TRI_T = DQ1_T
PORT DQ1_T = "", DIR = O
PORT DQ1_O = "", DIR = O
PORT DQ1_I = "", DIR = I, INITIALVAL = VCC

PORT DQ2 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ2_I, TRI_O = DQ2_O, TRI_T = DQ2_T
PORT DQ2_T = "", DIR = O
PORT DQ2_O = "", DIR = O
PORT DQ2_I = "", DIR = I, INITIALVAL = VCC

PORT DQ3 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ3_I, TRI_O = DQ3_O, TRI_T = DQ3_T
PORT DQ3_T = "", DIR = O
PORT DQ3_O = "", DIR = O
PORT DQ3_I = "", DIR = I, INITIALVAL = VCC

PORT DQ4 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ4_I, TRI_O = DQ4_O, TRI_T = DQ4_T
PORT DQ4_T = "", DIR = O
PORT DQ4_O = "", DIR = O
PORT DQ4_I = "", DIR = I, INITIALVAL = VCC

PORT DQ5 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ5_I, TRI_O = DQ5_O, TRI_T = DQ5_T
PORT DQ5_T = "", DIR = O
PORT DQ5_O = "", DIR = O
PORT DQ5_I = "", DIR = I, INITIALVAL = VCC

PORT DQ6 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ6_I, TRI_O = DQ6_O, TRI_T = DQ6_T
PORT DQ6_T = "", DIR = O
PORT DQ6_O = "", DIR = O
PORT DQ6_I = "", DIR = I, INITIALVAL = VCC

PORT DQ7 = "", DIR = IO, THREE_STATE = TRUE, TRI_I = DQ7_I, TRI_O = DQ7_O, TRI_T = DQ7_T
PORT DQ7_T = "", DIR = O
PORT DQ7_O = "", DIR = O
PORT DQ7_I = "", DIR = I, INITIALVAL = VCC

PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB

END
