# -------------------------------------------------------------
#  Copyright (c) 2006 Rice University
#  All Rights Reserved
#  This code is covered by the Rice-WARP license
#  See http://warp.rice.edu/license/ for details
# -------------------------------------------------------------

# Define the attributes of the board that will be displayed when listing the board. 
ATTRIBUTE VENDOR = Rice University - WARP Project 
ATTRIBUTE SPEC_URL = http://warp.rice.edu/
ATTRIBUTE CONTACT_INFO_URL= http://warp.rice.edu/
ATTRIBUTE NAME = WARP FPGA Board
ATTRIBUTE REVISION = FPGA 1.2
ATTRIBUTE DESC = Rice University WARP
ATTRIBUTE LONG_DESC = 'This board utilizes a Xilinx Virtex-II Pro FPGA XC2VP70-FF1517-6C. This XBD enables: 4 LEDs, 2 Hex Displays, 1 Reset Button, 4 Push-Buttons, SystemACE CompactFlash MCU interface, UART, 2 512kx32b ZBT SRAMs, Ethernet & OneWire EEPROM. It configures the XPS clock_generator to be driven by the 100MHz oscillator on the FPGA board. This XBD does not support use of the WARP clock and radio boards.'
# Defining hardware interfaces

# Define the first clock which is the processor clock. IOTYPE = XIL_CLOCK_V1 defines a general clock.
# port name can be named as desired but remain consistent when defining the pins in the FPGA section.
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_CLOCK_V1
	ATTRIBUTE INSTANCE =GCLK0
	PARAMETER CLK_FREQ =100000000, IO_IS=clk_freq, RANGE=(100000000) # 100 MHz
	PORT GCLK5S = CONN_GCLK0_GCLK5S , IO_IS=ext_clk
END

# Defines the reset interface.  Currently set to use first push button
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_RESET_V1
	ATTRIBUTE INSTANCE = rst_0
	PARAMETER RST_POLARITY =1, IO_IS=polarity, VALUE_NOTE=Active HIGH
	PORT INIT =  CONN_INIT_INIT, IO_IS=ext_rst
END

# A single GPIO core is used to interface with:
#  4 user LEDs (4-bits)
#  2 7-segment displays (14-bits)
#  4 push buttons (4-bits)
#  DIP switch (4-bits)
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_GPIO_V1
	ATTRIBUTE INSTANCE = USER_IO
	PARAMETER num_bits = 18, IO_IS=num_bits
	PARAMETER is_dual=1, IO_IS=is_dual			# Single channel
	PARAMETER bidir_data = 0, IO_IS=is_bidir	# No bi-directional I/O
	PARAMETER all_inputs = 1, IO_IS=all_inputs	# Channel 1 is all inputs
	PARAMETER bidir_data_2 = 1, IO_IS=is_bidir_2	# 
	PARAMETER all_inputs_2 = 0, IO_IS=all_inputs_2	# Channel 2 is all outputs

	#Channel 1 - User Inputs (buttons and switches)
	PORT SW_0 = SW_0, IO_IS = gpio_data_in[0]
	PORT SW_1 = SW_1, IO_IS = gpio_data_in[1]
	PORT SW_2 = SW_2, IO_IS = gpio_data_in[2]
	PORT SW_3 = SW_3, IO_IS = gpio_data_in[3]

	PORT PUSHU = CONN_PUSHU, IO_IS = gpio_data_in[4]
	PORT PUSHL = CONN_PUSHL, IO_IS = gpio_data_in[5]
	PORT PUSHR = CONN_PUSHR, IO_IS = gpio_data_in[6]
	PORT PUSHC = CONN_PUSHC, IO_IS = gpio_data_in[7]

	#Channel 2 - User Outputs (LEDs and hex displays)
	PORT SEG_LED0 = CONN_0_SEG1, IO_IS = gpio_data_out_2[0]
	PORT SEG_LED1 = CONN_0_SEG2, IO_IS = gpio_data_out_2[1]
	PORT SEG_LED2 = CONN_0_SEG3, IO_IS = gpio_data_out_2[2]
	PORT SEG_LED3 = CONN_0_SEG4, IO_IS = gpio_data_out_2[3]
	PORT SEG_LED4 = CONN_0_SEG5, IO_IS = gpio_data_out_2[4]
	PORT SEG_LED5 = CONN_0_SEG6, IO_IS = gpio_data_out_2[5]
	PORT SEG_LED6 = CONN_0_SEG7, IO_IS = gpio_data_out_2[6]

	PORT SEG_1_LED0 = CONN_1_SEG1, IO_IS = gpio_data_out_2[7]
	PORT SEG_1_LED1 = CONN_1_SEG2, IO_IS = gpio_data_out_2[8]
	PORT SEG_1_LED2 = CONN_1_SEG3, IO_IS = gpio_data_out_2[9]
	PORT SEG_1_LED3 = CONN_1_SEG4, IO_IS = gpio_data_out_2[10]
	PORT SEG_1_LED4 = CONN_1_SEG5, IO_IS = gpio_data_out_2[11]
	PORT SEG_1_LED5 = CONN_1_SEG6, IO_IS = gpio_data_out_2[12]
	PORT SEG_1_LED6 = CONN_1_SEG7, IO_IS = gpio_data_out_2[13]
	
	PORT LED0 = CONN_LEDs_LED0, IO_IS = gpio_data_out_2[14]
	PORT LED1 = CONN_LEDs_LED1, IO_IS = gpio_data_out_2[15]
	PORT LED2 = CONN_LEDs_LED2, IO_IS = gpio_data_out_2[16]
	PORT LED3 = CONN_LEDs_LED3, IO_IS = gpio_data_out_2[17]
END       

# This is the serial port.
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_UART_V1
	ATTRIBUTE INSTANCE = rs232
	PORT RXD = CONN_RXD, IO_IS=serial_in
	PORT TXD = CONN_TXD, IO_IS=serial_out
END       

# SystemACE Compact Flash microprocessor interface
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_SYSACE_V1
	ATTRIBUTE INSTANCE = sysace_compactflash
	PARAMETER C_MEM_WIDTH =16, IO_IS=mem_data_bus_width  
	PORT X104_5_OUT = sysace_clk, IO_IS=clk_in
	PORT X104_1_OE = sysace_clk_oe_n, IO_IS=clk_enable_n, INITIALVAL = VCC 
	PORT MPA00 = sysace_mpa_0, IO_IS = address[0] 
	PORT MPA01 = sysace_mpa_1, IO_IS = address[1] 
	PORT MPA02 = sysace_mpa_2, IO_IS = address[2] 
	PORT MPA03 = sysace_mpa_3, IO_IS = address[3] 
	PORT MPA04 = sysace_mpa_4, IO_IS = address[4] 
	PORT MPA05 = sysace_mpa_5, IO_IS = address[5] 
	PORT MPA06 = sysace_mpa_6, IO_IS = address[6] 
	PORT MPD00 = sysace_mpd_0, IO_IS = data[0]    
	PORT MPD01 = sysace_mpd_1, IO_IS = data[1]    
	PORT MPD02 = sysace_mpd_2, IO_IS = data[2]    
	PORT MPD03 = sysace_mpd_3, IO_IS = data[3]    
	PORT MPD04 = sysace_mpd_4, IO_IS = data[4]    
	PORT MPD05 = sysace_mpd_5, IO_IS = data[5]    
	PORT MPD06 = sysace_mpd_6, IO_IS = data[6]    
	PORT MPD07 = sysace_mpd_7, IO_IS = data[7]
	PORT MPD08 = sysace_mpd_8, IO_IS = data[8]
	PORT MPD09 = sysace_mpd_9, IO_IS = data[9]
	PORT MPD10 = sysace_mpd_10, IO_IS = data[10] 
	PORT MPD11 = sysace_mpd_11, IO_IS = data[11] 
	PORT MPD12 = sysace_mpd_12, IO_IS = data[12] 
	PORT MPD13 = sysace_mpd_13, IO_IS = data[13] 
	PORT MPD14 = sysace_mpd_14, IO_IS = data[14] 
	PORT MPD15 = sysace_mpd_15, IO_IS = data[15] 
	PORT MPCE  = sysace_mpce, IO_IS=chip_enable  
	PORT MPOE  = sysace_mpoe, IO_IS=output_enable
	PORT MPWE  = sysace_mpwe, IO_IS=write_enable 
	PORT MPIRQ = sysace_mpirq, IO_IS=intr_out     
END

# EEPROM Serial Number and Memory interface
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = WARP_EEPROM_V1
	ATTRIBUTE INSTANCE = eeprom_controller
	PORT DQ0   = EEPROM_0_DQ0, INITIALVAL = VCC
#	PORT DQ0_T = 
#	PORT DQ0_O = 
#	PORT DQ0_I =

#	PORT DQ1   =
	PORT DQ1_T = DQ1_T_user_EEPROM_IO_T
	PORT DQ1_O = DQ1_O_user_EEPROM_IO_O
	PORT DQ1_I = DQ1_I_user_EEPROM_IO_I, INITIALVAL = VCC

#	PORT DQ2   =
	PORT DQ2_T = DQ2_T_user_EEPROM_IO_T
	PORT DQ2_O = DQ2_O_user_EEPROM_IO_O
	PORT DQ2_I = DQ2_I_user_EEPROM_IO_I, INITIALVAL = VCC

#	PORT DQ3   =
	PORT DQ3_T = DQ3_T_user_EEPROM_IO_T
	PORT DQ3_O = DQ3_O_user_EEPROM_IO_O
	PORT DQ3_I = DQ3_I_user_EEPROM_IO_I, INITIALVAL = VCC

#	PORT DQ4   =
	PORT DQ4_T = DQ4_T_user_EEPROM_IO_T
	PORT DQ4_O = DQ4_O_user_EEPROM_IO_O
	PORT DQ4_I = DQ4_I_user_EEPROM_IO_I, INITIALVAL = VCC

#	PORT DQ5   =
#	PORT DQ5_T =
#	PORT DQ5_O =
	PORT DQ5_I = "net_vcc"

#	PORT DQ6   =
#	PORT DQ6_T =
#	PORT DQ6_O =
	PORT DQ6_I = "net_vcc"

#	PORT DQ7   =
#	PORT DQ7_T =
#	PORT DQ7_O =
	PORT DQ7_I = "net_vcc"
END

# LTX972A Ethernet MAC (10/100)
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_ETHERNET_V1
	ATTRIBUTE INSTANCE = Ethernet_MAC
	PORT TXSLEW0  = phy_slew0, IO_IS=slew1,      INITIALVAL = VCC
	PORT TXSLEW1  = phy_slew1, IO_IS=slew2,      INITIALVAL = VCC
	PORT RESET    = phy_rst_n, IO_IS=PHY_RESETn, INITIALVAL = VCC
	PORT MDINT    = phy_mii_int_n, IO_IS = mii_int_n
	PORT CRS      = phy_crs,       IO_IS = ETH_CRS
	PORT COL      = phy_col,       IO_IS = ETH_COL
	PORT TXD3     = phy_tx_data_3, IO_IS = ETH_TXD[3]
	PORT TXD2     = phy_tx_data_2, IO_IS = ETH_TXD[2]
	PORT TXD1     = phy_tx_data_1, IO_IS = ETH_TXD[1]
	PORT TXD0     = phy_tx_data_0, IO_IS = ETH_TXD[0]
	PORT TX_EN    = phy_tx_en,     IO_IS = ETH_TXEN
	PORT TX_CLK   = phy_tx_clk,    IO_IS = ETH_TXC
	PORT TX_ER    = phy_tx_er,     IO_IS = ETH_TXER
	PORT RX_ER    = phy_rx_er,     IO_IS = ETH_RXER
	PORT RX_CLK   = phy_rx_clk,    IO_IS = ETH_RXC
	PORT RX_DV    = phy_dv,        IO_IS = ETH_RXDV
	PORT RXD0     = phy_rx_data_0, IO_IS = ETH_RXD[0]
	PORT RXD1     = phy_rx_data_1, IO_IS = ETH_RXD[1]
	PORT RXD2     = phy_rx_data_2, IO_IS = ETH_RXD[2]
	PORT RXD3     = phy_rx_data_3, IO_IS = ETH_RXD[3]
	PORT PHY_MDC  = phy_mii_clk,   IO_IS = ETH_MDC
	PORT PHY_MDIO = phy_mii_data,  IO_IS = ETH_MDIO
END


# One user I/O board controller handles a single board
#  The user can enabled up to four controllers (one per slot)
BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_USERIOBOARD_V1
	ATTRIBUTE INSTANCE = user_io_board_controller_slot1
	ATTRIBUTE EXCLUSIVE = slot1

	#Hardware reset input (same as software reset)
	PORT reset = userio_board_slot1_reset, IO_IS = userio_board_reset

	#LCD SPI interface
	PORT sdi = user_ioboard_slot1_sdi, IO_IS = userio_board_sdi
	PORT scl = userio_board_slot1_scl, IO_IS = userio_board_scl
	PORT resetlcd = userio_board_slot1_resetlcd, IO_IS = userio_board_resetlcd
	PORT cs = userio_board_slot1_cs, IO_IS = userio_board_cs

	#Buzzer output
	PORT buzzer = userio_board_slot1_buzzer, IO_IS = userio_board_buzzer

	#Trackball I/O
	PORT trackball_yscn = userio_board_slot1_trackball_yscn, IO_IS = userio_board_trackball_yscn
	PORT trackball_sel1 = userio_board_slot1_trackball_sel1, IO_IS = userio_board_trackball_sel1
	PORT trackball_xscn = userio_board_slot1_trackball_xscn, IO_IS = userio_board_trackball_xscn
	PORT trackball_sel2 = userio_board_slot1_trackball_sel2, IO_IS = userio_board_trackball_sel2
	PORT trackball_oyn = userio_board_slot1_trackball_oyn, IO_IS = userio_board_trackball_oyn
	PORT trackball_oy = userio_board_slot1_trackball_oy, IO_IS = userio_board_trackball_oy
	PORT trackball_oxn = userio_board_slot1_trackball_oxn, IO_IS = userio_board_trackball_oxn
	PORT trackball_ox = userio_board_slot1_trackball_ox, IO_IS = userio_board_trackball_ox

	#Eight LEDs
	PORT leds_0 = userio_board_slot1_leds_0, IO_IS = userio_board_leds[0]
	PORT leds_1 = userio_board_slot1_leds_1, IO_IS = userio_board_leds[1]
	PORT leds_2 = userio_board_slot1_leds_2, IO_IS = userio_board_leds[2]
	PORT leds_3 = userio_board_slot1_leds_3, IO_IS = userio_board_leds[3]
	PORT leds_4 = userio_board_slot1_leds_4, IO_IS = userio_board_leds[4]
	PORT leds_5 = userio_board_slot1_leds_5, IO_IS = userio_board_leds[5]
	PORT leds_6 = userio_board_slot1_leds_6, IO_IS = userio_board_leds[6]
	PORT leds_7 = userio_board_slot1_leds_7, IO_IS = userio_board_leds[7]

	#DIP switch
	PORT dip_switch_0 = userio_board_slot1_dip_switch_0, IO_IS = userio_board_dip_switch[0]
	PORT dip_switch_1 = userio_board_slot1_dip_switch_1, IO_IS = userio_board_dip_switch[1]
	PORT dip_switch_2 = userio_board_slot1_dip_switch_2, IO_IS = userio_board_dip_switch[2]
	PORT dip_switch_3 = userio_board_slot1_dip_switch_3, IO_IS = userio_board_dip_switch[3]

	#Six small push buttons
	PORT buttons_small_0 = userio_board_slot1_buttons_small_0, IO_IS = userio_board_buttons_small[0]
	PORT buttons_small_1 = userio_board_slot1_buttons_small_1, IO_IS = userio_board_buttons_small[1]
	PORT buttons_small_2 = userio_board_slot1_buttons_small_2, IO_IS = userio_board_buttons_small[2]
	PORT buttons_small_3 = userio_board_slot1_buttons_small_3, IO_IS = userio_board_buttons_small[3]
	PORT buttons_small_4 = userio_board_slot1_buttons_small_4, IO_IS = userio_board_buttons_small[4]
	PORT buttons_small_5 = userio_board_slot1_buttons_small_5, IO_IS = userio_board_buttons_small[5]

	#Two big push buttons
	PORT buttons_big_0 = userio_board_slot1_buttons_big_0, IO_IS = userio_board_buttons_big[0]
	PORT buttons_big_1 = userio_board_slot1_buttons_big_1, IO_IS = userio_board_buttons_big[1]
END

BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_EMC_V1
	ATTRIBUTE INSTANCE = SRAM0_ZBT_512Kx32
	PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
	PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE
	PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH
	PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1, IO_IS=C_INCLUDE_NEGEDGE_IOREGS

	PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
	PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
	PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=SRAM_256Kx32
	PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
	PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH
	PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
	PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0

	PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_SLOW_PS_0
	PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_SLOW_PS_0
	PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 0,  IO_IS = C_WRITE_MIN_PULSE_WIDTH_PS_0
	PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_FAST_PS_0
	PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_FAST_PS_0
	PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0, IO_IS = C_READ_RECOVERY_BEFORE_WRITE_PS_0
	PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0, IO_IS = C_WRITE_RECOVERY_BEFORE_READ_PS_0

	PORT A0 = CONN_SRAM0_A0, IO_IS = emc_addr[29]
	PORT A1 = CONN_SRAM0_A1, IO_IS = emc_addr[28]
	PORT A2 = CONN_SRAM0_A2, IO_IS = emc_addr[27]
	PORT A3 = CONN_SRAM0_A3, IO_IS = emc_addr[26]
	PORT A4 = CONN_SRAM0_A4, IO_IS = emc_addr[25]
	PORT A5 = CONN_SRAM0_A5, IO_IS = emc_addr[24]
	PORT A6 = CONN_SRAM0_A6, IO_IS = emc_addr[23]
	PORT A7 = CONN_SRAM0_A7, IO_IS = emc_addr[22]
	PORT A8 = CONN_SRAM0_A8, IO_IS = emc_addr[21]
	PORT A9 = CONN_SRAM0_A9, IO_IS = emc_addr[20]
	PORT A10 = CONN_SRAM0_A10, IO_IS = emc_addr[19]
	PORT A11 = CONN_SRAM0_A11, IO_IS = emc_addr[18]
	PORT A12 = CONN_SRAM0_A12, IO_IS = emc_addr[17]
	PORT A13 = CONN_SRAM0_A13, IO_IS = emc_addr[16]
	PORT A14 = CONN_SRAM0_A14, IO_IS = emc_addr[15]
	PORT A15 = CONN_SRAM0_A15, IO_IS = emc_addr[14]
	PORT A16 = CONN_SRAM0_A16, IO_IS = emc_addr[13]
	PORT A17 = CONN_SRAM0_A17, IO_IS = emc_addr[12]
	PORT A18 = CONN_SRAM0_A18, IO_IS = emc_addr[11]

	PORT BEN0 = CONN_SRAM0_BEN0, IO_IS = emc_ben[3]
	PORT BEN1 = CONN_SRAM0_BEN1, IO_IS = emc_ben[2]
	PORT BEN2 = CONN_SRAM0_BEN2, IO_IS = emc_ben[1]
	PORT BEN3 = CONN_SRAM0_BEN3, IO_IS = emc_ben[0]
	PORT WEN = CONN_SRAM0_WEN, IO_IS=emc_wen

	PORT D0 = CONN_SRAM0_D0, IO_IS = emc_data[31]
	PORT D1 = CONN_SRAM0_D1, IO_IS = emc_data[30]
	PORT D2 = CONN_SRAM0_D2, IO_IS = emc_data[29]
	PORT D3 = CONN_SRAM0_D3, IO_IS = emc_data[28]
	PORT D4 = CONN_SRAM0_D4, IO_IS = emc_data[27]
	PORT D5 = CONN_SRAM0_D5, IO_IS = emc_data[26]
	PORT D6 = CONN_SRAM0_D6,  IO_IS = emc_data[25]
	PORT D7 = CONN_SRAM0_D7, IO_IS = emc_data[24]
	PORT D8 = CONN_SRAM0_D8, IO_IS = emc_data[23]
	PORT D9 = CONN_SRAM0_D9, IO_IS = emc_data[22]
	PORT D10 = CONN_SRAM0_D10, IO_IS = emc_data[21]
	PORT D11 = CONN_SRAM0_D11, IO_IS = emc_data[20]
	PORT D12 = CONN_SRAM0_D12, IO_IS = emc_data[19]
	PORT D13 = CONN_SRAM0_D13, IO_IS = emc_data[18]
	PORT D14 = CONN_SRAM0_D14, IO_IS = emc_data[17]
	PORT D15 = CONN_SRAM0_D15, IO_IS = emc_data[16]
	PORT D16 = CONN_SRAM0_D16, IO_IS = emc_data[15]
	PORT D17 = CONN_SRAM0_D17, IO_IS = emc_data[14]
	PORT D18 = CONN_SRAM0_D18, IO_IS = emc_data[13]
	PORT D19 = CONN_SRAM0_D19, IO_IS = emc_data[12]
	PORT D20 = CONN_SRAM0_D20, IO_IS = emc_data[11]
	PORT D21 = CONN_SRAM0_D21, IO_IS = emc_data[10]
	PORT D22 = CONN_SRAM0_D22, IO_IS = emc_data[9]
	PORT D23 = CONN_SRAM0_D23, IO_IS = emc_data[8]
	PORT D24 = CONN_SRAM0_D24, IO_IS = emc_data[7]
	PORT D25 = CONN_SRAM0_D25, IO_IS = emc_data[6]
	PORT D26 = CONN_SRAM0_D26, IO_IS = emc_data[5]
	PORT D27 = CONN_SRAM0_D27, IO_IS = emc_data[4]
	PORT D28 = CONN_SRAM0_D28, IO_IS = emc_data[3]
	PORT D29 = CONN_SRAM0_D29, IO_IS = emc_data[2]
	PORT D30 = CONN_SRAM0_D30, IO_IS = emc_data[1]
	PORT D31 = CONN_SRAM0_D31, IO_IS = emc_data[0]

	PORT OEN = CONN_SRAM0_OEN, IO_IS = emc_oen[0]
	PORT ADV_LDN = CONN_SRAM0_ADV_LDN, IO_IS = emc_adv_ldn
	PORT ZBT_CLK_OUT = CONN_SRAM0_CLK, IO_IS=EMC_CLK_OUT

	PORT CKEN_PORT = CONN_SRAM0_CKEN, IO_IS = emc_cken
	PORT CE_PORT = CONN_SRAM0_CE, IO_IS = emc_ce   
END

BEGIN IO_INTERFACE
	ATTRIBUTE IOTYPE = XIL_EMC_V1
	ATTRIBUTE INSTANCE = SRAM1_ZBT_512Kx32
	PARAMETER C_NUM_BANKS_MEM = 1, IO_IS=C_NUM_BANKS_MEM
	PARAMETER C_DEV_MIR_ENABLE = 0, IO_IS=C_DEV_MIR_ENABLE
	PARAMETER C_MAX_MEM_WIDTH = 32, IO_IS=C_MAX_MEM_WIDTH
	PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1, IO_IS=C_INCLUDE_NEGEDGE_IOREGS

	PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1, IO_IS=C_INCLUDE_BURST_CACHELN_SUPPORT
	PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1, IO_IS=C_INCLUDE_DATAWIDTH_MATCHING_0
	PARAMETER C_MEM0_BASEADDR = 0x0, IO_IS=C_MEM0_BASEADDR, SHORT_DESC=SRAM_256Kx32
	PARAMETER C_MEM0_HIGHADDR = 0x1FFFFF, IO_IS=C_MEM0_HIGHADDR
	PARAMETER C_MEM0_WIDTH = 32, IO_IS=C_MEM0_WIDTH
	PARAMETER C_SYNCH_MEM_0 = 1, IO_IS=C_SYNCH_MEM_0
	PARAMETER C_SYNCH_PIPEDELAY_0 = 2, IO_IS=C_SYNCH_PIPEDELAY_0

	PARAMETER C_READ_ADDR_TO_OUT_SLOW_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_SLOW_PS_0
	PARAMETER C_WRITE_ADDR_TO_OUT_SLOW_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_SLOW_PS_0
	PARAMETER C_WRITE_MIN_PULSE_WIDTH_PS_0 = 0,  IO_IS = C_WRITE_MIN_PULSE_WIDTH_PS_0
	PARAMETER C_READ_ADDR_TO_OUT_FAST_PS_0 = 0,  IO_IS = C_READ_ADDR_TO_OUT_FAST_PS_0
	PARAMETER C_WRITE_ADDR_TO_OUT_FAST_PS_0 = 0, IO_IS = C_WRITE_ADDR_TO_OUT_FAST_PS_0
	PARAMETER C_READ_RECOVERY_BEFORE_WRITE_PS_0 = 0, IO_IS = C_READ_RECOVERY_BEFORE_WRITE_PS_0
	PARAMETER C_WRITE_RECOVERY_BEFORE_READ_PS_0 = 0, IO_IS = C_WRITE_RECOVERY_BEFORE_READ_PS_0

	PORT A0 = CONN_SRAM1_A0, IO_IS = emc_addr[29]
	PORT A1 = CONN_SRAM1_A1, IO_IS = emc_addr[28]
	PORT A2 = CONN_SRAM1_A2, IO_IS = emc_addr[27]
	PORT A3 = CONN_SRAM1_A3, IO_IS = emc_addr[26]
	PORT A4 = CONN_SRAM1_A4, IO_IS = emc_addr[25]
	PORT A5 = CONN_SRAM1_A5, IO_IS = emc_addr[24]
	PORT A6 = CONN_SRAM1_A6, IO_IS = emc_addr[23]
	PORT A7 = CONN_SRAM1_A7, IO_IS = emc_addr[22]
	PORT A8 = CONN_SRAM1_A8, IO_IS = emc_addr[21]
	PORT A9 = CONN_SRAM1_A9, IO_IS = emc_addr[20]
	PORT A10 = CONN_SRAM1_A10, IO_IS = emc_addr[19]
	PORT A11 = CONN_SRAM1_A11, IO_IS = emc_addr[18]
	PORT A12 = CONN_SRAM1_A12, IO_IS = emc_addr[17]
	PORT A13 = CONN_SRAM1_A13, IO_IS = emc_addr[16]
	PORT A14 = CONN_SRAM1_A14, IO_IS = emc_addr[15]
	PORT A15 = CONN_SRAM1_A15, IO_IS = emc_addr[14]
	PORT A16 = CONN_SRAM1_A16, IO_IS = emc_addr[13]
	PORT A17 = CONN_SRAM1_A17, IO_IS = emc_addr[12]
	PORT A18 = CONN_SRAM1_A18, IO_IS = emc_addr[11]

	PORT BEN0 = CONN_SRAM1_BEN0, IO_IS = emc_ben[3]
	PORT BEN1 = CONN_SRAM1_BEN1, IO_IS = emc_ben[2]
	PORT BEN2 = CONN_SRAM1_BEN2, IO_IS = emc_ben[1]
	PORT BEN3 = CONN_SRAM1_BEN3, IO_IS = emc_ben[0]
	PORT WEN = CONN_SRAM1_WEN, IO_IS=emc_wen

	PORT D0 = CONN_SRAM1_D0, IO_IS = emc_data[31]
	PORT D1 = CONN_SRAM1_D1, IO_IS = emc_data[30]
	PORT D2 = CONN_SRAM1_D2, IO_IS = emc_data[29]
	PORT D3 = CONN_SRAM1_D3, IO_IS = emc_data[28]
	PORT D4 = CONN_SRAM1_D4, IO_IS = emc_data[27]
	PORT D5 = CONN_SRAM1_D5, IO_IS = emc_data[26]
	PORT D6 = CONN_SRAM1_D6,  IO_IS = emc_data[25]
	PORT D7 = CONN_SRAM1_D7, IO_IS = emc_data[24]
	PORT D8 = CONN_SRAM1_D8, IO_IS = emc_data[23]
	PORT D9 = CONN_SRAM1_D9, IO_IS = emc_data[22]
	PORT D10 = CONN_SRAM1_D10, IO_IS = emc_data[21]
	PORT D11 = CONN_SRAM1_D11, IO_IS = emc_data[20]
	PORT D12 = CONN_SRAM1_D12, IO_IS = emc_data[19]
	PORT D13 = CONN_SRAM1_D13, IO_IS = emc_data[18]
	PORT D14 = CONN_SRAM1_D14, IO_IS = emc_data[17]
	PORT D15 = CONN_SRAM1_D15, IO_IS = emc_data[16]
	PORT D16 = CONN_SRAM1_D16, IO_IS = emc_data[15]
	PORT D17 = CONN_SRAM1_D17, IO_IS = emc_data[14]
	PORT D18 = CONN_SRAM1_D18, IO_IS = emc_data[13]
	PORT D19 = CONN_SRAM1_D19, IO_IS = emc_data[12]
	PORT D20 = CONN_SRAM1_D20, IO_IS = emc_data[11]
	PORT D21 = CONN_SRAM1_D21, IO_IS = emc_data[10]
	PORT D22 = CONN_SRAM1_D22, IO_IS = emc_data[9]
	PORT D23 = CONN_SRAM1_D23, IO_IS = emc_data[8]
	PORT D24 = CONN_SRAM1_D24, IO_IS = emc_data[7]
	PORT D25 = CONN_SRAM1_D25, IO_IS = emc_data[6]
	PORT D26 = CONN_SRAM1_D26, IO_IS = emc_data[5]
	PORT D27 = CONN_SRAM1_D27, IO_IS = emc_data[4]
	PORT D28 = CONN_SRAM1_D28, IO_IS = emc_data[3]
	PORT D29 = CONN_SRAM1_D29, IO_IS = emc_data[2]
	PORT D30 = CONN_SRAM1_D30, IO_IS = emc_data[1]
	PORT D31 = CONN_SRAM1_D31, IO_IS = emc_data[0]

	PORT OEN = CONN_SRAM1_OEN, IO_IS = emc_oen[0]
	PORT ADV_LDN = CONN_SRAM1_ADV_LDN, IO_IS = emc_adv_ldn
	PORT ZBT_CLK_OUT = CONN_SRAM1_CLK, IO_IS=EMC_CLK_OUT

	PORT CKEN_PORT = CONN_SRAM1_CKEN, IO_IS = emc_cken
	PORT CE_PORT = CONN_SRAM1_CE, IO_IS = emc_ce   
END

# This is the FPGA definition. First characterize the processor.
BEGIN FPGA
	ATTRIBUTE INSTANCE = fpga_0
	ATTRIBUTE FAMILY = virtex2p
	ATTRIBUTE  DEVICE =  XC2VP70
	ATTRIBUTE PACKAGE =  FF1517
	ATTRIBUTE SPEED_GRADE = -6
	ATTRIBUTE JTAG_POSITION = 2 #SysaceCF is in position 1

### Clock ###  Use the same port connection names as defined above.
	PORT CLK_0 = CONN_GCLK0_GCLK5S, UCF_NET_STRING=("LOC=AH21", "IOSTANDARD = LVTTL")

### RESET ### #Down push button
	PORT RESET = CONN_INIT_INIT, UCF_NET_STRING=("LOC=AM16", "IOSTANDARD = LVTTL") 



### LED 7Seg0 ###
	PORT SEG_LED0 = CONN_0_SEG1, UCF_NET_STRING=("LOC=AJ26", "IOSTANDARD = LVTTL")
	PORT SEG_LED1 = CONN_0_SEG2, UCF_NET_STRING=("LOC=AH26", "IOSTANDARD = LVTTL")
	PORT SEG_LED2 = CONN_0_SEG3, UCF_NET_STRING=("LOC=AH24", "IOSTANDARD = LVTTL")
	PORT SEG_LED3 = CONN_0_SEG4, UCF_NET_STRING=("LOC=AH25", "IOSTANDARD = LVTTL")
	PORT SEG_LED4 = CONN_0_SEG5, UCF_NET_STRING=("LOC=AH23", "IOSTANDARD = LVTTL")
	PORT SEG_LED5 = CONN_0_SEG6, UCF_NET_STRING=("LOC=AG22", "IOSTANDARD = LVTTL")
	PORT SEG_LED6 = CONN_0_SEG7, UCF_NET_STRING=("LOC=AG23", "IOSTANDARD = LVTTL")

### LED 7Seg1 ###
	PORT SEG_1_LED0 = CONN_1_SEG1, UCF_NET_STRING=("LOC=AG19", "IOSTANDARD = LVTTL")
	PORT SEG_1_LED1 = CONN_1_SEG2, UCF_NET_STRING=("LOC=AG21", "IOSTANDARD = LVTTL")
	PORT SEG_1_LED2 = CONN_1_SEG3, UCF_NET_STRING=("LOC=AH19", "IOSTANDARD = LVTTL")
	PORT SEG_1_LED3 = CONN_1_SEG4, UCF_NET_STRING=("LOC=AJ19", "IOSTANDARD = LVTTL")
	PORT SEG_1_LED4 = CONN_1_SEG5, UCF_NET_STRING=("LOC=AP12", "IOSTANDARD = LVTTL")
	PORT SEG_1_LED5 = CONN_1_SEG6, UCF_NET_STRING=("LOC=AN13", "IOSTANDARD = LVTTL")
	PORT SEG_1_LED6 = CONN_1_SEG7, UCF_NET_STRING=("LOC=AL15", "IOSTANDARD = LVTTL")

### LED ###
	PORT LED0 = CONN_LEDs_LED0, UCF_NET_STRING=("LOC=AJ14", "IOSTANDARD = LVTTL")
	PORT LED1 = CONN_LEDs_LED1, UCF_NET_STRING=("LOC=AM13", "IOSTANDARD = LVTTL")
	PORT LED2 = CONN_LEDs_LED2, UCF_NET_STRING=("LOC=AR12", "IOSTANDARD = LVTTL")
	PORT LED3 = CONN_LEDs_LED3, UCF_NET_STRING=("LOC=AH13", "IOSTANDARD = LVTTL")

### PUSH BUTTONS ###
	PORT PUSHU = CONN_PUSHU, UCF_NET_STRING=("LOC=AJ22", "IOSTANDARD = LVTTL")
	PORT PUSHL = CONN_PUSHL, UCF_NET_STRING=("LOC=AJ15", "IOSTANDARD = LVTTL")
	PORT PUSHR = CONN_PUSHR, UCF_NET_STRING=("LOC=AG18", "IOSTANDARD = LVTTL")
	PORT PUSHC = CONN_PUSHC, UCF_NET_STRING=("LOC=AG17", "IOSTANDARD = LVTTL")

### UART ###
	PORT RXD = CONN_RXD, UCF_NET_STRING=("LOC=AA29", "IOSTANDARD = LVTTL")
	PORT TXD = CONN_TXD, UCF_NET_STRING=("LOC=AA28", "IOSTANDARD = LVTTL")

### SYSACE FLASH ###
	PORT SYSACE_CLK = sysace_clk, UCF_NET_STRING=("LOC=N20", "IOSTANDARD = LVTTL") # Input CLK
# PORT SYSACE_CLK_OE_N = sysace_clk_oe_n, UCF_NET_STRING=("LOC= ", "IOSTANDARD = LVTTL")
	PORT MPA00 = sysace_mpa_0, UCF_NET_STRING=("LOC=N18", "IOSTANDARD = LVTTL")
	PORT MPA01 = sysace_mpa_1, UCF_NET_STRING=("LOC=N17", "IOSTANDARD = LVTTL")
	PORT MPA02 = sysace_mpa_2, UCF_NET_STRING=("LOC=M14", "IOSTANDARD = LVTTL")
	PORT MPA03 = sysace_mpa_3, UCF_NET_STRING=("LOC=M16", "IOSTANDARD = LVTTL")
	PORT MPA04 = sysace_mpa_4, UCF_NET_STRING=("LOC=G11", "IOSTANDARD = LVTTL")
	PORT MPA05 = sysace_mpa_5, UCF_NET_STRING=("LOC=E11", "IOSTANDARD = LVTTL")
	PORT MPA06 = sysace_mpa_6, UCF_NET_STRING=("LOC=F11", "IOSTANDARD = LVTTL")
	PORT MPD00 = sysace_mpd_0, UCF_NET_STRING=("LOC=M17", "IOSTANDARD = LVTTL")
	PORT MPD01 = sysace_mpd_1, UCF_NET_STRING=("LOC=L13", "IOSTANDARD = LVTTL")
	PORT MPD02 = sysace_mpd_2, UCF_NET_STRING=("LOC=K14", "IOSTANDARD = LVTTL")
	PORT MPD03 = sysace_mpd_3, UCF_NET_STRING=("LOC=L12", "IOSTANDARD = LVTTL")
	PORT MPD04 = sysace_mpd_4, UCF_NET_STRING=("LOC=J14", "IOSTANDARD = LVTTL")
	PORT MPD05 = sysace_mpd_5, UCF_NET_STRING=("LOC=K10", "IOSTANDARD = LVTTL")
	PORT MPD06 = sysace_mpd_6, UCF_NET_STRING=("LOC=J10", "IOSTANDARD = LVTTL")
	PORT MPD07 = sysace_mpd_7, UCF_NET_STRING=("LOC=K12", "IOSTANDARD = LVTTL")
	PORT MPD08 = sysace_mpd_8, UCF_NET_STRING=("LOC=H10", "IOSTANDARD = LVTTL")
	PORT MPD09 = sysace_mpd_9, UCF_NET_STRING=("LOC=J12", "IOSTANDARD = LVTTL")
	PORT MPD10 = sysace_mpd_10, UCF_NET_STRING=("LOC=G10", "IOSTANDARD = LVTTL")
	PORT MPD11 = sysace_mpd_11, UCF_NET_STRING=("LOC=K11", "IOSTANDARD = LVTTL")
	PORT MPD12 = sysace_mpd_12, UCF_NET_STRING=("LOC=F10", "IOSTANDARD = LVTTL")
	PORT MPD13 = sysace_mpd_13, UCF_NET_STRING=("LOC=J11", "IOSTANDARD = LVTTL")
	PORT MPD14 = sysace_mpd_14, UCF_NET_STRING=("LOC=H11", "IOSTANDARD = LVTTL")
	PORT MPD15 = sysace_mpd_15, UCF_NET_STRING=("LOC=H12", "IOSTANDARD = LVTTL")
	PORT MPCE  = sysace_mpce, UCF_NET_STRING=("LOC=C10", "IOSTANDARD = LVTTL")
	PORT MPOE  = sysace_mpoe, UCF_NET_STRING=("LOC=M15", "IOSTANDARD = LVTTL")
	PORT MPWE  = sysace_mpwe, UCF_NET_STRING=("LOC=M13", "IOSTANDARD = LVTTL")
	PORT MPIRQ = sysace_mpirq, UCF_NET_STRING=("LOC=E10", "IOSTANDARD = LVTTL")


# FPGA BOARD EEPROM Serial Number and Memory interface
	PORT DQ0 = EEPROM_0_DQ0, UCF_NET_STRING=("LOC=AB28", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8") 

# 10/100 Ethernet MAC
	PORT PHY_SLW0   = phy_slew0,     UCF_NET_STRING=("LOC=H20", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_SLW1   = phy_slew1,     UCF_NET_STRING=("LOC=J22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_RESET  = phy_rst_n,     UCF_NET_STRING=("LOC=J27", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_MDINT  = phy_mii_int_n, UCF_NET_STRING=("LOC=G27", "IOSTANDARD = LVTTL")
	PORT PHY_CRS    = phy_crs,       UCF_NET_STRING=("LOC=D29", "IOSTANDARD = LVTTL")
	PORT PHY_COL    = phy_col,       UCF_NET_STRING=("LOC=J26", "IOSTANDARD = LVTTL")
	PORT PHY_TXD3   = phy_tx_data_3, UCF_NET_STRING=("LOC=G26", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_TXD2   = phy_tx_data_2, UCF_NET_STRING=("LOC=D26", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_TXD1   = phy_tx_data_1, UCF_NET_STRING=("LOC=H23", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_TXD0   = phy_tx_data_0, UCF_NET_STRING=("LOC=D22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_TX_EN  = phy_tx_en,     UCF_NET_STRING=("LOC=H22", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_TX_CLK = phy_tx_clk,    UCF_NET_STRING=("LOC=F20", "IOSTANDARD = LVTTL")
	PORT PHY_TX_ER  = phy_tx_er,     UCF_NET_STRING=("LOC=H26", "IOSTANDARD = LVTTL")
	PORT PHY_RX_ER  = phy_rx_er,     UCF_NET_STRING=("LOC=F21", "IOSTANDARD = LVTTL")
	PORT PHY_RX_CLK = phy_rx_clk,    UCF_NET_STRING=("LOC=E24", "IOSTANDARD = LVTTL")
	PORT PHY_RX_DV  = phy_dv,        UCF_NET_STRING=("LOC=F22", "IOSTANDARD = LVTTL")
	PORT PHY_RXD0   = phy_rx_data_0, UCF_NET_STRING=("LOC=C22", "IOSTANDARD = LVTTL")
	PORT PHY_RXD1   = phy_rx_data_1, UCF_NET_STRING=("LOC=E21", "IOSTANDARD = LVTTL")
	PORT PHY_RXD2   = phy_rx_data_2, UCF_NET_STRING=("LOC=C21", "IOSTANDARD = LVTTL")
	PORT PHY_RXD3   = phy_rx_data_3, UCF_NET_STRING=("LOC=D23", "IOSTANDARD = LVTTL")
	PORT PHY_MDC    = phy_mii_clk,   UCF_NET_STRING=("LOC=J24", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")
	PORT PHY_MDIO   = phy_mii_data,  UCF_NET_STRING=("LOC=C23", "IOSTANDARD = LVTTL", "SLEW = SLOW", "DRIVE = 8")

# 4 Dip Switchs
	PORT SW_0 = SW_0, UCF_NET_STRING=("LOC=Y27", "IOSTANDARD = LVTTL") 
	PORT SW_1 = SW_1, UCF_NET_STRING=("LOC=Y28", "IOSTANDARD = LVTTL") 
	PORT SW_2 = SW_2, UCF_NET_STRING=("LOC=AA27", "IOSTANDARD = LVTTL") 
	PORT SW_3 = SW_3, UCF_NET_STRING=("LOC=Y29", "IOSTANDARD = LVTTL") 

### SRAM0_256Kx32 ###
	PORT SRAM0_OEN = CONN_SRAM0_OEN, UCF_NET_STRING=("LOC=AP15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM0_ADV_LDN = CONN_SRAM0_ADV_LDN, UCF_NET_STRING=("LOC=AP14", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM0_CLOCK = CONN_SRAM0_CLK, UCF_NET_STRING=("LOC=AR15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 16")
	PORT SRAM0_CKEN = CONN_SRAM0_CKEN, UCF_NET_STRING=("LOC=AH14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 8")
	PORT SRAM0_CE = CONN_SRAM0_CE, UCF_NET_STRING=("LOC=AP11", "IOSTANDARD = LVTTL")
	PORT SRAM0_BEN_0 = CONN_SRAM0_BEN0,  UCF_NET_STRING=("LOC=AP16", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM0_BEN_1 = CONN_SRAM0_BEN1,  UCF_NET_STRING=("LOC=AR17", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM0_BEN_2 = CONN_SRAM0_BEN2,  UCF_NET_STRING=("LOC=AN14", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM0_BEN_3 = CONN_SRAM0_BEN3,  UCF_NET_STRING=("LOC=AT15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM0_WEN = CONN_SRAM0_WEN, UCF_NET_STRING=("LOC=AN15", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")

	PORT SRAM0_A0 = CONN_SRAM0_A0,   UCF_NET_STRING=("LOC=AL16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A1 = CONN_SRAM0_A1,   UCF_NET_STRING=("LOC=AH15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A2 = CONN_SRAM0_A2,   UCF_NET_STRING=("LOC=AL14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A3 = CONN_SRAM0_A3,   UCF_NET_STRING=("LOC=AM15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A4 = CONN_SRAM0_A4,   UCF_NET_STRING=("LOC=AM14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A5 = CONN_SRAM0_A5,   UCF_NET_STRING=("LOC=AT9", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A6 = CONN_SRAM0_A6,   UCF_NET_STRING=("LOC=AU11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A7 = CONN_SRAM0_A7,   UCF_NET_STRING=("LOC=AN11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A8 = CONN_SRAM0_A8,   UCF_NET_STRING=("LOC=AN17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A9 = CONN_SRAM0_A9,   UCF_NET_STRING=("LOC=AH16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A10 = CONN_SRAM0_A10,   UCF_NET_STRING=("LOC=AR16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A11 = CONN_SRAM0_A11,   UCF_NET_STRING=("LOC=AU15", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A12 = CONN_SRAM0_A12,   UCF_NET_STRING=("LOC=AP18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A13 = CONN_SRAM0_A13,   UCF_NET_STRING=("LOC=AJ18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A14 = CONN_SRAM0_A14,   UCF_NET_STRING=("LOC=AM17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A15 = CONN_SRAM0_A15,   UCF_NET_STRING=("LOC=AM18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A16 = CONN_SRAM0_A16,   UCF_NET_STRING=("LOC=AK16", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A17 = CONN_SRAM0_A17,   UCF_NET_STRING=("LOC=AU14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_A18 = CONN_SRAM0_A18,   UCF_NET_STRING=("LOC=AT13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")

	PORT SRAM0_D0 = CONN_SRAM0_D0,   UCF_NET_STRING=("LOC=AU19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D1 = CONN_SRAM0_D1,   UCF_NET_STRING=("LOC=AH18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D2 = CONN_SRAM0_D2,   UCF_NET_STRING=("LOC=AP19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D3 = CONN_SRAM0_D3,   UCF_NET_STRING=("LOC=AT19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D4 = CONN_SRAM0_D4,   UCF_NET_STRING=("LOC=AN18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D5 = CONN_SRAM0_D5,   UCF_NET_STRING=("LOC=AR19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D6 = CONN_SRAM0_D6,   UCF_NET_STRING=("LOC=AJ17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D7 = CONN_SRAM0_D7,   UCF_NET_STRING=("LOC=AT18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D8 = CONN_SRAM0_D8,   UCF_NET_STRING=("LOC=AM19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D9 = CONN_SRAM0_D9,   UCF_NET_STRING=("LOC=AL19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D10 = CONN_SRAM0_D10,   UCF_NET_STRING=("LOC=AK18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D11 = CONN_SRAM0_D11,   UCF_NET_STRING=("LOC=AL18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D12 = CONN_SRAM0_D12,   UCF_NET_STRING=("LOC=AU17", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D13 = CONN_SRAM0_D13,   UCF_NET_STRING=("LOC=AR18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D14 = CONN_SRAM0_D14,   UCF_NET_STRING=("LOC=AU18", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D15 = CONN_SRAM0_D15,   UCF_NET_STRING=("LOC=AN19", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D16 = CONN_SRAM0_D16,   UCF_NET_STRING=("LOC=AK12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D17 = CONN_SRAM0_D17,   UCF_NET_STRING=("LOC=AL12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D18 = CONN_SRAM0_D18,   UCF_NET_STRING=("LOC=AK14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D19 = CONN_SRAM0_D19,   UCF_NET_STRING=("LOC=AR14", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D20 = CONN_SRAM0_D20,   UCF_NET_STRING=("LOC=AL11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D21 = CONN_SRAM0_D21,   UCF_NET_STRING=("LOC=AT11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D22 = CONN_SRAM0_D22,   UCF_NET_STRING=("LOC=AU10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D23 = CONN_SRAM0_D23,   UCF_NET_STRING=("LOC=AR11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D24 = CONN_SRAM0_D24,   UCF_NET_STRING=("LOC=AR13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D25 = CONN_SRAM0_D25,   UCF_NET_STRING=("LOC=AL13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D26 = CONN_SRAM0_D26,   UCF_NET_STRING=("LOC=AJ13", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D27 = CONN_SRAM0_D27,   UCF_NET_STRING=("LOC=AM10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D28 = CONN_SRAM0_D28,   UCF_NET_STRING=("LOC=AJ12", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D29 = CONN_SRAM0_D29,   UCF_NET_STRING=("LOC=AM11", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D30 = CONN_SRAM0_D30,   UCF_NET_STRING=("LOC=AL10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM0_D31 = CONN_SRAM0_D31,   UCF_NET_STRING=("LOC=AT10", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")


### SRAM1_256Kx32 ###

	PORT SRAM1_OEN = CONN_SRAM1_OEN, UCF_NET_STRING=("LOC=AP25", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_ADV_LDN = CONN_SRAM1_ADV_LDN, UCF_NET_STRING=("LOC=AU26", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_CLOCK = CONN_SRAM1_CLK, UCF_NET_STRING=("LOC=AP24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 16")
	PORT SRAM1_CKEN = CONN_SRAM1_CKEN, UCF_NET_STRING=("LOC=AR25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 8")
	PORT SRAM1_BEN_0 = CONN_SRAM1_BEN0,  UCF_NET_STRING=("LOC=AP26", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_BEN_1 = CONN_SRAM1_BEN1,  UCF_NET_STRING=("LOC=AN29", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_BEN_2 = CONN_SRAM1_BEN2,  UCF_NET_STRING=("LOC=AR23", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_BEN_3 = CONN_SRAM1_BEN3,  UCF_NET_STRING=("LOC=AT25", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_WEN = CONN_SRAM1_WEN, UCF_NET_STRING=("LOC=AM24", "IOSTANDARD = LVTTL", "SLEW = FAST", "DRIVE = 8")
	PORT SRAM1_CE = CONN_SRAM1_CE, UCF_NET_STRING=("LOC=AM23", "IOSTANDARD = LVTTL")

	PORT SRAM1_A0 = CONN_SRAM1_A0, UCF_NET_STRING=("LOC=AK25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A1 = CONN_SRAM1_A1, UCF_NET_STRING=("LOC=AK24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A2 = CONN_SRAM1_A2, UCF_NET_STRING=("LOC=AU25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A3 = CONN_SRAM1_A3, UCF_NET_STRING=("LOC=AR24", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A4 = CONN_SRAM1_A4, UCF_NET_STRING=("LOC=AN23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A5 = CONN_SRAM1_A5, UCF_NET_STRING=("LOC=AH22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A6 = CONN_SRAM1_A6, UCF_NET_STRING=("LOC=AL23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A7 = CONN_SRAM1_A7, UCF_NET_STRING=("LOC=AN22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A8 = CONN_SRAM1_A8, UCF_NET_STRING=("LOC=AT28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A9 = CONN_SRAM1_A9, UCF_NET_STRING=("LOC=AR28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A10 = CONN_SRAM1_A10, UCF_NET_STRING=("LOC=AT26", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A11 = CONN_SRAM1_A11, UCF_NET_STRING=("LOC=AL28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A12 = CONN_SRAM1_A12, UCF_NET_STRING=("LOC=AK29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A13 = CONN_SRAM1_A13, UCF_NET_STRING=("LOC=AR26", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A14 = CONN_SRAM1_A14, UCF_NET_STRING=("LOC=AH27", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A15 = CONN_SRAM1_A15, UCF_NET_STRING=("LOC=AU29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A16 = CONN_SRAM1_A16, UCF_NET_STRING=("LOC=AP29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A17 = CONN_SRAM1_A17, UCF_NET_STRING=("LOC=AJ23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_A18 = CONN_SRAM1_A18, UCF_NET_STRING=("LOC=AP28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")

	PORT SRAM1_D0 = CONN_SRAM1_D0, UCF_NET_STRING=("LOC=AT31", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D1 = CONN_SRAM1_D1, UCF_NET_STRING=("LOC=AT30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D2 = CONN_SRAM1_D2, UCF_NET_STRING=("LOC=AL30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D3 = CONN_SRAM1_D3, UCF_NET_STRING=("LOC=AJ28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D4 = CONN_SRAM1_D4, UCF_NET_STRING=("LOC=AK28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D5 = CONN_SRAM1_D5, UCF_NET_STRING=("LOC=AM30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D6 = CONN_SRAM1_D6, UCF_NET_STRING=("LOC=AR29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D7 = CONN_SRAM1_D7, UCF_NET_STRING=("LOC=AL29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D8 = CONN_SRAM1_D8, UCF_NET_STRING=("LOC=AL27", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D9 = CONN_SRAM1_D9, UCF_NET_STRING=("LOC=AM25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D10 = CONN_SRAM1_D10, UCF_NET_STRING=("LOC=AR31", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D11 = CONN_SRAM1_D11, UCF_NET_STRING=("LOC=AM29", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D12 = CONN_SRAM1_D12, UCF_NET_STRING=("LOC=AN30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D13 = CONN_SRAM1_D13, UCF_NET_STRING=("LOC=AL25", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D14 = CONN_SRAM1_D14, UCF_NET_STRING=("LOC=AM28", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D15 = CONN_SRAM1_D15, UCF_NET_STRING=("LOC=AU30", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D16 = CONN_SRAM1_D16, UCF_NET_STRING=("LOC=AR22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D17 = CONN_SRAM1_D17, UCF_NET_STRING=("LOC=AM22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D18 = CONN_SRAM1_D18, UCF_NET_STRING=("LOC=AT23", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D19 = CONN_SRAM1_D19, UCF_NET_STRING=("LOC=AU22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D20 = CONN_SRAM1_D20, UCF_NET_STRING=("LOC=AT22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D21 = CONN_SRAM1_D21, UCF_NET_STRING=("LOC=AL21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D22 = CONN_SRAM1_D22, UCF_NET_STRING=("LOC=AU21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D23 = CONN_SRAM1_D23, UCF_NET_STRING=("LOC=AP21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D24 = CONN_SRAM1_D24, UCF_NET_STRING=("LOC=AT21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D25 = CONN_SRAM1_D25, UCF_NET_STRING=("LOC=AN21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D26 = CONN_SRAM1_D26, UCF_NET_STRING=("LOC=AK22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D27 = CONN_SRAM1_D27, UCF_NET_STRING=("LOC=AP22", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D28 = CONN_SRAM1_D28, UCF_NET_STRING=("LOC=AR21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D29 = CONN_SRAM1_D29, UCF_NET_STRING=("LOC=AM20", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D30 = CONN_SRAM1_D30, UCF_NET_STRING=("LOC=AK21", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")
	PORT SRAM1_D31 = CONN_SRAM1_D31, UCF_NET_STRING=("LOC=AP20", "SLEW = FAST", "IOSTANDARD = LVTTL", "DRIVE = 12")

	#USER I/O Board in Slot 1
	#LCD SPI interface
	PORT user_ioboard_slot1_sdi = user_ioboard_slot1_sdi, UCF_NET_STRING=("LOC=W4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_scl = userio_board_slot1_scl, UCF_NET_STRING=("LOC=V3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_resetlcd = userio_board_slot1_resetlcd, UCF_NET_STRING=("LOC=V5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_cs = userio_board_slot1_cs, UCF_NET_STRING=("LOC=V8", "SLEW=SLOW", "IOSTANDARD=LVTTL")

	#Buzzer output
	PORT userio_board_slot1_buzzer = userio_board_slot1_buzzer, UCF_NET_STRING=("LOC=P3", "SLEW=SLOW", "IOSTANDARD=LVTTL")

	#Trackball I/O
	PORT userio_board_slot1_trackball_yscn = userio_board_slot1_trackball_yscn, UCF_NET_STRING=("LOC=T3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_sel1 = userio_board_slot1_trackball_sel1, UCF_NET_STRING=("LOC=U4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_xscn = userio_board_slot1_trackball_xscn, UCF_NET_STRING=("LOC=V4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_sel2 = userio_board_slot1_trackball_sel2, UCF_NET_STRING=("LOC=V6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_oyn = userio_board_slot1_trackball_oyn, UCF_NET_STRING=("LOC=T11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_oy = userio_board_slot1_trackball_oy, UCF_NET_STRING=("LOC=U9", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_oxn = userio_board_slot1_trackball_oxn, UCF_NET_STRING=("LOC=U10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_trackball_ox = userio_board_slot1_trackball_ox, UCF_NET_STRING=("LOC=V9", "SLEW=SLOW", "IOSTANDARD=LVTTL")

	#Eight LEDs
	PORT userio_board_slot1_leds_0 = userio_board_slot1_leds_0, UCF_NET_STRING=("LOC=P10", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_1 = userio_board_slot1_leds_1, UCF_NET_STRING=("LOC=P8", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_2 = userio_board_slot1_leds_2, UCF_NET_STRING=("LOC=P1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_3 = userio_board_slot1_leds_3, UCF_NET_STRING=("LOC=P2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_4 = userio_board_slot1_leds_4, UCF_NET_STRING=("LOC=N5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_5 = userio_board_slot1_leds_5, UCF_NET_STRING=("LOC=M3", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_6 = userio_board_slot1_leds_6, UCF_NET_STRING=("LOC=N6", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_leds_7 = userio_board_slot1_leds_7, UCF_NET_STRING=("LOC=L6", "SLEW=SLOW", "IOSTANDARD=LVTTL")

	#DIP switch
	PORT userio_board_slot1_dip_switch_0 = userio_board_slot1_dip_switch_0, UCF_NET_STRING=("LOC=K2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_dip_switch_1 = userio_board_slot1_dip_switch_1, UCF_NET_STRING=("LOC=K1", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_dip_switch_2 = userio_board_slot1_dip_switch_2, UCF_NET_STRING=("LOC=P4", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_dip_switch_3 = userio_board_slot1_dip_switch_3, UCF_NET_STRING=("LOC=N3", "SLEW=SLOW", "IOSTANDARD=LVTTL")

	#Six small push buttons
	PORT userio_board_slot1_buttons_small_0 = userio_board_slot1_buttons_small_0, UCF_NET_STRING=("LOC=M2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_buttons_small_1 = userio_board_slot1_buttons_small_1, UCF_NET_STRING=("LOC=R11", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_buttons_small_2 = userio_board_slot1_buttons_small_2, UCF_NET_STRING=("LOC=N2", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_buttons_small_3 = userio_board_slot1_buttons_small_3, UCF_NET_STRING=("LOC=M7", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_buttons_small_4 = userio_board_slot1_buttons_small_4, UCF_NET_STRING=("LOC=L5", "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_buttons_small_5 = userio_board_slot1_buttons_small_5, UCF_NET_STRING=("LOC=L4", "SLEW=SLOW", "IOSTANDARD=LVTTL")

	#Two big push buttons
	PORT userio_board_slot1_buttons_big_0 = userio_board_slot1_buttons_big_0, UCF_NET_STRING=("LOC=R1, "SLEW=SLOW", "IOSTANDARD=LVTTL")
	PORT userio_board_slot1_buttons_big_1 = userio_board_slot1_buttons_big_1, UCF_NET_STRING=("LOC=R2", "SLEW=SLOW", "IOSTANDARD=LVTTL")

END
