#  WARP Kits (FPGA/Clock/Radio Boards)
Net fpga_0_UserIO_LEDs_out_pin<0> LOC=N24  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<1> LOC=N20  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<2> LOC=L18  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<3> LOC=N18  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<4> LOC=M18  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<5> LOC=M25  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<6> LOC=N19  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_LEDs_out_pin<7> LOC=P19  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_IOEx_SDA_pin LOC=AL18  |  IOSTANDARD = LVTTL;
Net fpga_0_UserIO_IOEx_SCL_pin LOC=AK17  |  IOSTANDARD = LVTTL;
Net fpga_0_UserIO_PB_in_pin<0> LOC=N23  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_PB_in_pin<1> LOC=N22  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_PB_in_pin<2> LOC=M23  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_PB_in_pin<3> LOC=L23  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_DIPSW_in_pin<0> LOC=M17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_DIPSW_in_pin<1> LOC=R18  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_DIPSW_in_pin<2> LOC=P17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_UserIO_DIPSW_in_pin<3> LOC=M16  |  IOSTANDARD = LVCMOS25;
Net fpga_0_rs232_db9_RX_pin LOC=L24  |  IOSTANDARD = LVCMOS25;
Net fpga_0_rs232_db9_TX_pin LOC=K24  |  IOSTANDARD = LVCMOS25;
Net fpga_0_rs232_usb_RX_pin LOC=C23  |  IOSTANDARD = LVTTL;
Net fpga_0_rs232_usb_TX_pin LOC=AA23  |  IOSTANDARD = LVTTL;
Net fpga_0_TriMode_MAC_GMII_TemacPhy_RST_n_pin LOC = C17  |  TIG  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_MII_TX_CLK_0_pin LOC = G22  |  PERIOD = 40 ns  |  MAXSKEW= 1.0 ns  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<7> LOC = K16  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<6> LOC = H17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<5> LOC = J17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<4> LOC = J16  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<3> LOC = G15  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<2> LOC = K17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<1> LOC = E17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<0> LOC = D17  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin LOC = C18  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin LOC = K18  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_TX_CLK_0_pin LOC = F21  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<7> LOC = G21  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<6> LOC = E23  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<5> LOC = G23  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<4> LOC = J24  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<3> LOC = H22  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<2> LOC = E22  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<1> LOC = E21  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<0> LOC = K23  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin LOC = H23  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin LOC = F23  |  IOBDELAY=NONE  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_GMII_RX_CLK_0_pin LOC = J22  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_MDC_0_pin LOC = H15  |  IOSTANDARD = LVCMOS25;
Net fpga_0_TriMode_MAC_GMII_MDIO_0_pin LOC = L16  |  IOSTANDARD = LVCMOS25;
Net fpga_0_clk_board_config_sys_clk_pin LOC=AM21  |  IOSTANDARD = LVTTL;
Net fpga_0_clk_board_config_cfg_radio_dat_out_pin LOC=AN19  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_csb_out_pin LOC=AP19  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_en_out_pin LOC=AR19  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_radio_clk_out_pin LOC=AM20  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_dat_out_pin LOC=AR21  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_csb_out_pin LOC=AL21  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_en_out_pin LOC=AK21  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_clk_board_config_cfg_logic_clk_out_pin LOC=AN22  |  IOSTANDARD=LVTTL  |  SLEW = SLOW;
Net fpga_0_radio_bridge_slot_2_converter_clock_out_pin LOC=AD5  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_clk_pin LOC=AF5  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<0> LOC=AP4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<1> LOC=AR3  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<2> LOC=AT4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<3> LOC=AR4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<4> LOC=AT5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<5> LOC=AN3  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<6> LOC=AT3  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<7> LOC=AU5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<8> LOC=AM7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<9> LOC=AU6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<10> LOC=AP5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<11> LOC=AN5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<12> LOC=AT6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<13> LOC=AM6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<14> LOC=AL6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_I_pin<15> LOC=AL8  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<0> LOC=AF8  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<1> LOC=AF9  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<2> LOC=AH8  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<3> LOC=AG7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<4> LOC=AJ6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<5> LOC=AN4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<6> LOC=AG8  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<7> LOC=AM5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<8> LOC=AJ5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<9> LOC=AK6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<10> LOC=AH7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<11> LOC=AJ4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<12> LOC=AL4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<13> LOC=AB15  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<14> LOC=AC14  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_Q_pin<15> LOC=AK4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<0> LOC=V14  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<1> LOC=U15  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<2> LOC=W6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<3> LOC=AG18  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<4> LOC=V15  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<5> LOC=V5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<6> LOC=AA10  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<7> LOC=Y11  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<8> LOC=AA9  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<9> LOC=V7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<10> LOC=U6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<11> LOC=AB11  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<12> LOC=W4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_I_pin<13> LOC=V12  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<0> LOC=AB7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<1> LOC=AE7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<2> LOC=AC7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<3> LOC=AC5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<4> LOC=AE4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<5> LOC=AD4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<6> LOC=AD7  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<7> LOC=AD6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<8> LOC=W14  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<9> LOC=U5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<10> LOC=W5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<11> LOC=AA11  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<12> LOC=W9  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ADC_Q_pin<13> LOC=Y12  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<0> LOC=AA4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<1> LOC=AH5  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<2> LOC=Y4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<3> LOC=V17  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<4> LOC=AC3  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<5> LOC=Y6  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_B_pin<6> LOC=AH4  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<0> LOC=U3  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_ANTSW_pin<1> LOC=Y7  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<0> LOC=AA8  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<1> LOC=W10  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LED_pin<2> LOC=V4  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<0> LOC=Y13  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<1> LOC=AH3  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<2> LOC=W15  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DIPSW_pin<3> LOC=AA13  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<0> LOC=AD10  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<1> LOC=AD11  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<2> LOC=AE3  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<3> LOC=AC13  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<4> LOC=AF3  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<5> LOC=AM3  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<6> LOC=AG10  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<7> LOC=AF10  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<8> LOC=AL5  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_D_pin<9> LOC=AM8  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_2_radio_EEPROM_IO_pin LOC=AE6  |  IOSTANDARD=LVTTL  |  SLEW = SLOW  |  DRIVE = 8;
Net fpga_0_radio_bridge_slot_2_radio_spi_clk_pin LOC=AB12  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_data_pin LOC=AG3  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_spi_cs_pin LOC=AE8  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_SHDN_pin LOC=AB3  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_TxEn_pin LOC=W16  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RxEn_pin LOC=AB10  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RxHP_pin LOC=AC4  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_24PA_pin LOC=W7  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_5PA_pin LOC=AC8  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DCS_pin LOC=AA5  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_DFS_pin LOC=AF4  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNA_pin LOC=Y8  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_PWDNB_pin LOC=AA14  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_CLAMP_pin LOC=AB13  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_HIZ_pin LOC=AK3  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_SLEEP_pin LOC=AH9  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_LD_pin LOC=AD9  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRA_pin LOC=V13  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RX_ADC_OTRB_pin LOC=Y9  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_RSSI_ADC_OTR_pin LOC=AC12  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_PLL_LOCK_pin LOC=AL3  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_radio_DAC_RESET_pin LOC=AC10  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_data_pin LOC=AC9  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_cs_pin LOC=AK8  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_2_dac_spi_clk_pin LOC=AK7  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_converter_clock_out_pin LOC=AC29  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_clk_pin LOC=AD32  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<0> LOC=AB35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<1> LOC=AC34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<2> LOC=AA30  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<3> LOC=Y27  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<4> LOC=AB31  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<5> LOC=N37  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<6> LOC=AA31  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<7> LOC=R34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<8> LOC=AC32  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<9> LOC=Y32  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<10> LOC=AD35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<11> LOC=Y34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<12> LOC=P37  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<13> LOC=R36  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<14> LOC=T35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_I_pin<15> LOC=Y33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<0> LOC=V34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<1> LOC=AC35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<2> LOC=V33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<3> LOC=Y36  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<4> LOC=U37  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<5> LOC=AB36  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<6> LOC=U35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<7> LOC=Y37  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<8> LOC=W37  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<9> LOC=AA34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<10> LOC=W36  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<11> LOC=AA35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<12> LOC=W30  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<13> LOC=W32  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<14> LOC=V35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_Q_pin<15> LOC=W34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<0> LOC=AM33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<1> LOC=AF33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<2> LOC=AG31  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<3> LOC=AM22  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<4> LOC=AH30  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<5> LOC=AG32  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<6> LOC=AF31  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<7> LOC=AH34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<8> LOC=AK32  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<9> LOC=AF34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<10> LOC=AN34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<11> LOC=AJ36  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<12> LOC=AN33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_I_pin<13> LOC=AH35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<0> LOC=AA26  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<1> LOC=AE29  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<2> LOC=AA29  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<3> LOC=AD29  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<4> LOC=AB26  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<5> LOC=AB27  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<6> LOC=AA28  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<7> LOC=AC28  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<8> LOC=AL34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<9> LOC=AJ34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<10> LOC=AK33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<11> LOC=AK34  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<12> LOC=AJ35  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ADC_Q_pin<13> LOC=AG33  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<0> LOC=AG28  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<1> LOC=AC24  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<2> LOC=AD31  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<3> LOC=AA24  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<4> LOC=AG30  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<5> LOC=AB23  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_B_pin<6> LOC=AH29  |  IOSTANDARD = LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<0> LOC=AN37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_ANTSW_pin<1> LOC=AJ37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<0> LOC=AL35  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<1> LOC=AE33  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LED_pin<2> LOC=AM35  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<0> LOC=AG36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<1> LOC=AG37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<2> LOC=T34  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DIPSW_pin<3> LOC=AH37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<0> LOC=P35  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<1> LOC=AB28  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<2> LOC=M36  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<3> LOC=AF35  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<4> LOC=L36  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<5> LOC=M37  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<6> LOC=R37  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<7> LOC=P36  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<8> LOC=AE34  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_D_pin<9> LOC=Y31  |  IOSTANDARD=LVTTL  |  PULLDOWN;
Net fpga_0_radio_bridge_slot_3_radio_EEPROM_IO_pin LOC=AE32  |  IOSTANDARD=LVTTL  |  SLEW = SLOW  |  DRIVE = 8;
Net fpga_0_radio_bridge_slot_3_radio_spi_clk_pin LOC=AC37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_data_pin LOC=AD37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_spi_cs_pin LOC=AF36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_SHDN_pin LOC=AD27  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_TxEn_pin LOC=AE37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RxEn_pin LOC=Y26  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RxHP_pin LOC=AC25  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_24PA_pin LOC=AM36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_5PA_pin LOC=AN35  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DCS_pin LOC=AF28  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_DFS_pin LOC=AD34  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNA_pin LOC=AK36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_PWDNB_pin LOC=AE28  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_CLAMP_pin LOC=K36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_HIZ_pin LOC=W29  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_SLEEP_pin LOC=K37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_LD_pin LOC=AB37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRA_pin LOC=AM37  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RX_ADC_OTRB_pin LOC=AL36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_RSSI_ADC_OTR_pin LOC=U36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_PLL_LOCK_pin LOC=AG35  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_radio_DAC_RESET_pin LOC=AE36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_data_pin LOC=T36  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_cs_pin LOC=W35  |  IOSTANDARD=LVTTL;
Net fpga_0_radio_bridge_slot_3_dac_spi_clk_pin LOC=AA36  |  IOSTANDARD=LVTTL;
Net fpga_0_eeprom_controller_DQ0_pin LOC=AH22  |  IOSTANDARD = LVTTL  |  SLEW = SLOW  |  DRIVE = 8;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 40000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=AN20  |  IOSTANDARD = LVTTL;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=M21  |  IOSTANDARD = LVCMOS25;

###### TriMode_MAC_GMII
#### Additional TriMode_MAC_GMII constraints

NET "*tx_gmii_mii_clk_in_0*"    TNM_NET = "clk_phy_tx_clk0";
NET "*tx_gmii_mii_clk_out_0*"   TNM_NET = "clk_phy_tx_clk0";
TIMESPEC "TS_phy_tx_clk0"     = PERIOD "clk_phy_tx_clk0" 7700 ps HIGH 50 %;

NET "*gmii_rx_clk_0*"         TNM_NET = "clk_phy_rx_clk0";
NET "*gmii_rx_clk_delay_0*"   TNM_NET = "clk_phy_rx_clk0";
NET "*gmii_rx_clk_ibufg_0*"   TNM_NET = "clk_phy_rx_clk0";
TIMESPEC "TS_phy_rx_clk0"     = PERIOD "clk_phy_rx_clk0" 7700 ps HIGH 50 %;

NET "*tx_client_clk_in_0*"      TNM_NET = "clk_client_tx_clk0";
NET "*tx_client_clk_out_0*"     TNM_NET = "clk_client_tx_clk0";
TIMESPEC "TS_client_tx_clk0"            = PERIOD "clk_client_tx_clk0" 7700 ps HIGH 50 %;

NET "*rx_client_clk_in_0*"      TNM_NET = "clk_client_rx_clk0";
NET "*rx_client_clk_out_0*"     TNM_NET = "clk_client_rx_clk0";
TIMESPEC "TS_client_rx_clk0"            = PERIOD "clk_client_rx_clk0" 7700 ps HIGH 50 %;

NET "*mii_tx_clk_0*"            TNM_NET = "clk_mii_tx_clk0";
TIMESPEC "TS_mii_tx_clk0"               = PERIOD "clk_mii_tx_clk0" 25000 ps HIGH 50 %;


#################### EMAC 0 GMII Constraints ########################
INST "*mii0?RXD_TO_MAC*"    IOB = true;
INST "*mii0?RX_DV_TO_MAC"   IOB = true;
INST "*mii0?RX_ER_TO_MAC"   IOB = true;

INST "*gmii0/*gmii_rxd?_delay"    IOBDELAY_TYPE = FIXED;
INST "*gmii0/*gmii_rx_dv_delay"   IOBDELAY_TYPE = FIXED;
INST "*gmii0/*gmii_rx_er_delay"   IOBDELAY_TYPE = FIXED;
INST "*gmii0/*gmii_rxd?_delay"    IOBDELAY_VALUE = 0;
INST "*gmii0/*gmii_rx_dv_delay"   IOBDELAY_VALUE = 0;
INST "*gmii0/*gmii_rx_er_delay"   IOBDELAY_VALUE = 0;
INST "*gmii_rx_clk_0_delay"       IOBDELAY_TYPE = FIXED;
INST "*gmii_rx_clk_0_delay"       IOBDELAY_VALUE = 30;

INST "fpga_0_TriMode_MAC_GMII_GMII_TXD_0_pin<?>"     TNM = "sig_mii_tx_0";
INST "fpga_0_TriMode_MAC_GMII_GMII_TX_EN_0_pin"      TNM = "sig_mii_tx_0";
INST "fpga_0_TriMode_MAC_GMII_GMII_TX_ER_0_pin"      TNM = "sig_mii_tx_0";

INST "fpga_0_TriMode_MAC_GMII_GMII_RXD_0_pin<?>"     TNM = "sig_mii_rx_0";
INST "fpga_0_TriMode_MAC_GMII_GMII_RX_DV_0_pin"      TNM = "sig_mii_rx_0";
INST "fpga_0_TriMode_MAC_GMII_GMII_RX_ER_0_pin"      TNM = "sig_mii_rx_0";

# Need to TIG between the LocalLink clock and the rx_client and tx_client clocks
NET "*/LlinkTemac0_CLK*" TNM_NET = "LLCLK";
TIMESPEC "TS_LL_CLK_2_RX_CLIENT_CLK"  = FROM LLCLK TO clk_client_rx_clk0 8000 ps DATAPATHONLY;
TIMESPEC "TS_LL_CLK_2_TX_CLIENT_CLK"  = FROM LLCLK TO clk_client_tx_clk0 8000 ps DATAPATHONLY;
TIMESPEC "TS_RX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_rx_clk0 TO LLCLK 10000 ps DATAPATHONLY;
TIMESPEC "TS_TX_CLIENT_CLK_2_LL_CLK"  = FROM clk_client_tx_clk0 TO LLCLK 10000 ps DATAPATHONLY;



###### ppc405_0
NET "ppc405_0/C405RSTCHIPRESETREQ" TPTHRU = "ppc405_0_RST_GRP";
NET "ppc405_0/C405RSTCORERESETREQ" TPTHRU = "ppc405_0_RST_GRP";
NET "ppc405_0/C405RSTSYSRESETREQ" TPTHRU = "ppc405_0_RST_GRP";
TIMESPEC "TS_RST_ppc405_0" = FROM CPUS THRU ppc405_0_RST_GRP TO FFS TIG;
