
###################################################################
# Copyright (c) 2006 Rice University
# All Rights Reserved
# This code is covered by the Rice-WARP license
# See http://warp.rice.edu/license/ for details
###################################################################

BEGIN radio_bridge

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VERILOG
OPTION ARCH_SUPPORT_MAP = (virtex2p=PREFERRED, virtex4=PREFERRED, others=AVAILABLE)
OPTION USAGE_LEVEL = BASE_USER
OPTION DESC = WARP Radio Board Bridge Core
OPTION LONG_DESC = "Implements a simple bridge between user logic, the WAPP radio_controller and the WARP Raido Board. One bridge should be instantiated for each Radio Board present, even if the user design only uses a subset of Radio Boards."
OPTION IP_GROUP = USER
OPTION RUN_NGCBUILD = FALSE
OPTION STYLE = HDL

IO_INTERFACE IO_IF = ext_radio_board_ports, IO_TYPE = WARP_RADIOBRIDGE_V1
IO_INTERFACE IO_IF = user_ports, IO_TYPE = WARP_RADIOBRIDGE_V1

BUS_INTERFACE BUS = RC2RB_RAD, BUS_STD = WARP_RC2RB_V1, BUS_TYPE = TARGET

PARAMETER C_FAMILY = virtex2p, DT = STRING

## Ports
####################################################################################
## User Ports
## The user must connect sources/sinks to these ports in XPS in order to use
##  the radio board. The rest of the board's connections are made automatically
####################################################################################
PORT user_ADC_I = "", DIR = O, VEC = [0:13], IO_IF = user_ports, IO_IS = userADCI
PORT user_ADC_Q = "", DIR = O, VEC = [0:13], IO_IF = user_ports, IO_IS = userADCQ

PORT user_DAC_I = "", DIR = I, VEC = [0:15], IO_IF = user_ports, IO_IS = userDACI
PORT user_DAC_Q = "", DIR = I, VEC = [0:15], IO_IF = user_ports, IO_IS = userDACQ

PORT user_RxRF_gain = "", DIR = I, VEC = [0:1], IO_IF = user_ports, IO_IS = userRxRFG
PORT user_RxBB_gain = "", DIR = I, VEC = [0:4], IO_IF = user_ports, IO_IS = userRxBBG



PORT user_TxModelStart = "", DIR = O, IO_IF = user_ports, IO_IS = user_txMdlStart

PORT user_RSSI_ADC_clk = "", DIR = I, IO_IF = user_ports, IO_IS = user_RSSICLK

PORT user_RSSI_ADC_D = "", DIR = O, VEC = [0:9], IO_IF = user_ports, IO_IS = user_RSSID

PORT user_EEPROM_IO_T = "", DIR = I, IO_IF = user_ports, IO_IS = user_eepromIOT
PORT user_EEPROM_IO_O = "", DIR = I , IO_IF = user_ports, IO_IS = user_eepromIOO
PORT user_EEPROM_IO_I = "", DIR = O , IO_IF = user_ports, IO_IS = user_eepromIOI

PORT user_SHDN_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_SHDNext
PORT user_RxEn_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_RXENext
PORT user_TxEn_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_TXENext
PORT user_RxHP_external = "", DIR = I, IO_IF = user_ports, IO_IS = user_RXHPext

#This clock must match the sampling clock at the Radio Board
# Users must assign it to the proper net in XPS (no way to know here what that net will be called)
PORT converter_clock_in = "", DIR = I, SIGIS = CLK, CLK_FREQ = 40000000, IO_IF = user_ports, ASSIGNMENT = REQUIRE, IO_IS = user_converterClk
####################################################################################

####
# Radio Bridge <-> Radio Board ports
####
PORT converter_clock_out = "", DIR = O, SIGIS = CLK, IO_IF = ext_radio_board_ports, IO_IS = convClkOut

PORT radio_RSSI_ADC_clk = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_rssi_adc_clk

PORT radio_DAC_I = "", DIR = O, VEC = [15:0], IO_IS = radioDACI, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioDACI
PORT radio_DAC_Q = "", DIR = O, VEC = [15:0], IO_IS = radioDACQ, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioDACQ

PORT radio_ADC_I = "", DIR = I, VEC = [13:0], IO_IS = radioADCI, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioADCI
PORT radio_ADC_Q = "", DIR = I, VEC = [13:0], IO_IS = radioADCQ, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports, IO_IS = radioADCQ

PORT radio_B = "", DIR = O, VEC = [6:0], IO_IS = radioGain, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports

PORT radio_ANTSW = "", DIR = O, VEC = [1:0], IO_IS = b2r_ANTSW, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports
PORT radio_LED = "", DIR = O, VEC = [2:0], IO_IS = b2r_LED, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports
PORT radio_DIPSW = "", DIR = I, VEC = [3:0], IO_IS = b2r_DIPSW, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports
PORT radio_RSSI_ADC_D = "", DIR = I, VEC = [9:0], IO_IS = b2r_RSSI_ADC_D, ENDIAN = LITTLE, IO_IF = ext_radio_board_ports

PORT radio_EEPROM_IO = "", DIR = IO, THREE_STATE = FALSE, IOB_STATE = BUF, IO_IF = ext_radio_board_ports, IO_IS = radio_eepromIO

PORT radio_spi_clk = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SCLK
PORT radio_spi_data = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SDO
PORT radio_spi_cs = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SCS
PORT radio_SHDN = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_SHDN
PORT radio_TxEn = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_TXEN
PORT radio_RxEn = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RXEN
PORT radio_RxHP = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RXHP
PORT radio_24PA = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_24PA
PORT radio_5PA = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_5PA
PORT radio_RX_ADC_DCS = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCDCS
PORT radio_RX_ADC_DFS = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCDFS
PORT radio_RX_ADC_PWDNA = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCPWDNA
PORT radio_RX_ADC_PWDNB = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCPWDNB
PORT radio_RSSI_ADC_CLAMP = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIADCCLAMP
PORT radio_RSSI_ADC_HIZ = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIADCHIZ
PORT radio_RSSI_ADC_SLEEP = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIADCSLEEP
PORT radio_LD = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_LD
PORT radio_RX_ADC_OTRA = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCOTRA
PORT radio_RX_ADC_OTRB = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_ADCOTRB
PORT radio_RSSI_ADC_OTR = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_RSSIOTR
PORT radio_DAC_PLL_LOCK = "", DIR = I, IO_IF = ext_radio_board_ports, IO_IS = radio_DACLOCK
PORT radio_DAC_RESET = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = radio_DACRESET
PORT dac_spi_data = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = rc_dac_sdo
PORT dac_spi_cs = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = rc_dac_scs
PORT dac_spi_clk = "", DIR = O, IO_IF = ext_radio_board_ports, IO_IS = rc_dac_sclk

###
# Radio Controller <-> Radio Bridge ports
###
PORT controller_logic_clk = "controller_logic_clk", DIR = I, BUS = RC2RB_RAD
PORT controller_spi_clk = "controller_spi_clk", DIR = I, BUS = RC2RB_RAD
PORT controller_spi_data = "controller_spi_data", DIR = I, BUS = RC2RB_RAD

PORT controller_radio_cs = "controller_radio_cs", DIR = I, BUS = RC2RB_RAD
PORT controller_dac_cs = "controller_dac_cs", DIR = I, BUS = RC2RB_RAD
PORT controller_SHDN = "controller_SHDN", DIR = I, BUS = RC2RB_RAD
PORT controller_TxEn = "controller_TxEn", DIR = I, BUS = RC2RB_RAD
PORT controller_RxEn = "controller_RxEn", DIR = I, BUS = RC2RB_RAD
PORT controller_RxHP = "controller_RxHP", DIR = I, BUS = RC2RB_RAD
PORT controller_24PA = "controller_24PA", DIR = I, BUS = RC2RB_RAD
PORT controller_5PA = "controller_5PA", DIR = I, BUS = RC2RB_RAD
PORT controller_ANTSW = "controller_ANTSW", DIR = I, VEC = [0:1], BUS = RC2RB_RAD
PORT controller_LED = "controller_LED", DIR = I, VEC = [0:2], BUS = RC2RB_RAD
PORT controller_RX_ADC_DCS = "controller_RX_ADC_DCS", DIR = I, BUS = RC2RB_RAD
PORT controller_RX_ADC_DFS = "controller_RX_ADC_DFS", DIR = I, BUS = RC2RB_RAD
PORT controller_RX_ADC_OTRA = "controller_RX_ADC_OTRA", DIR = O, BUS = RC2RB_RAD
PORT controller_RX_ADC_OTRB = "controller_RX_ADC_OTRB", DIR = O, BUS = RC2RB_RAD
PORT controller_RX_ADC_PWDNA = "controller_RX_ADC_PWDNA", DIR = I, BUS = RC2RB_RAD
PORT controller_RX_ADC_PWDNB = "controller_RX_ADC_PWDNB", DIR = I, BUS = RC2RB_RAD
PORT controller_DIPSW = "controller_DIPSW", DIR = O, VEC = [0:3], BUS = RC2RB_RAD
PORT controller_RSSI_ADC_CLAMP = "controller_RSSI_ADC_CLAMP", DIR = I, BUS = RC2RB_RAD
PORT controller_RSSI_ADC_HIZ = "controller_RSSI_ADC_HIZ", DIR = I, BUS = RC2RB_RAD
PORT controller_RSSI_ADC_OTR = "controller_RSSI_ADC_OTR", DIR = O, BUS = RC2RB_RAD
PORT controller_RSSI_ADC_SLEEP = "controller_RSSI_ADC_SLEEP", DIR = I, BUS = RC2RB_RAD
PORT controller_RSSI_ADC_D = "controller_RSSI_ADC_D", DIR = O, VEC = [0:9], BUS = RC2RB_RAD
PORT controller_LD = "controller_LD", DIR = O, BUS = RC2RB_RAD
PORT controller_DAC_PLL_LOCK = "controller_DAC_PLL_LOCK", DIR = O, BUS = RC2RB_RAD
PORT controller_DAC_RESET = "controller_DAC_RESET", DIR = I, BUS = RC2RB_RAD
PORT controller_SHDN_external = "controller_SHDN_external", DIR = O, BUS = RC2RB_RAD
PORT controller_TxEn_external = "controller_TxEn_external", DIR = O, BUS = RC2RB_RAD
PORT controller_RxEn_external = "controller_RxEn_external", DIR = O, BUS = RC2RB_RAD
PORT controller_RxHP_external = "controller_RxHP_external", DIR = O, BUS = RC2RB_RAD
PORT controller_TxStart = "controller_TxStart", DIR = I, BUS = RC2RB_RAD
PORT user_Tx_gain = "controller_Tx_gain", DIR = I, VEC = [0:5], BUS = RC2RB_RAD
END
