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##
## Name     : radio_controller_axi
## Desc     : Microprocessor Peripheral Description
##          : Automatically generated by PsfUtility
##
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BEGIN radio_controller_axi

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:USER
OPTION ARCH_SUPPORT_MAP = (virtex6=DEVELOPMENT)
OPTION DESC = WARP v3 Radio Controller (AXI)
OPTION LONG_DESC="Implements SPI master and other logic for configuring the MAX2829 RF transceivers on WARP v3 and FMC-RF-2X245 module"

IO_INTERFACE IO_IF = HW_Ports_RFA, IO_TYPE = W3_RADIOCONTROLLER_V3
IO_INTERFACE IO_IF = HW_Ports_RFB, IO_TYPE = W3_RADIOCONTROLLER_V3
IO_INTERFACE IO_IF = HW_Ports_RFC, IO_TYPE = W3_RADIOCONTROLLER_V3
IO_INTERFACE IO_IF = HW_Ports_RFD, IO_TYPE = W3_RADIOCONTROLLER_V3

IO_INTERFACE IO_IF = USER_Ports_RFA, IO_TYPE = W3_RADIOCONTROLLER_V3
IO_INTERFACE IO_IF = USER_Ports_RFB, IO_TYPE = W3_RADIOCONTROLLER_V3
IO_INTERFACE IO_IF = USER_Ports_RFC, IO_TYPE = W3_RADIOCONTROLLER_V3
IO_INTERFACE IO_IF = USER_Ports_RFD, IO_TYPE = W3_RADIOCONTROLLER_V3

IO_INTERFACE IO_IF = USER_Ports_Misc, IO_TYPE = W3_RADIOCONTROLLER_V3

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = INTEGER, BUS = S_AXI, ASSIGNMENT = CONSTANT
PARAMETER C_S_AXI_MIN_SIZE = 0x000001ff, DT = std_logic_vector, BUS = S_AXI
PARAMETER C_USE_WSTRB = 0, DT = INTEGER
PARAMETER C_DPHASE_TIMEOUT = 0, DT = INTEGER
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x100, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = S_AXI
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = S_AXI
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_NUM_REG = 1, DT = INTEGER
PARAMETER C_NUM_MEM = 1, DT = INTEGER
PARAMETER C_SLV_AWIDTH = 32, DT = INTEGER
PARAMETER C_SLV_DWIDTH = 32, DT = INTEGER
PARAMETER C_S_AXI_PROTOCOL = AXI4LITE, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, DT = STRING, BUS = S_AXI

## Ports
PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI
PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI
PORT S_AXI_AWADDR = AWADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_AWVALID = AWVALID, DIR = I, BUS = S_AXI
PORT S_AXI_WDATA = WDATA, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WSTRB = WSTRB, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8)-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_WVALID = WVALID, DIR = I, BUS = S_AXI
PORT S_AXI_BREADY = BREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARADDR = ARADDR, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_ARVALID = ARVALID, DIR = I, BUS = S_AXI
PORT S_AXI_RREADY = RREADY, DIR = I, BUS = S_AXI
PORT S_AXI_ARREADY = ARREADY, DIR = O, BUS = S_AXI
PORT S_AXI_RDATA = RDATA, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0], ENDIAN = LITTLE, BUS = S_AXI
PORT S_AXI_RRESP = RRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_RVALID = RVALID, DIR = O, BUS = S_AXI
PORT S_AXI_WREADY = WREADY, DIR = O, BUS = S_AXI
PORT S_AXI_BRESP = BRESP, DIR = O, VEC = [1:0], BUS = S_AXI
PORT S_AXI_BVALID = BVALID, DIR = O, BUS = S_AXI
PORT S_AXI_AWREADY = AWREADY, DIR = O, BUS = S_AXI


PORT RFA_TxEn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=TxEn
PORT RFB_TxEn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=TxEn
PORT RFC_TxEn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=TxEn
PORT RFD_TxEn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=TxEn

PORT RFA_RxEn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RxEn
PORT RFB_RxEn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RxEn
PORT RFC_RxEn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RxEn
PORT RFD_RxEn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RxEn

PORT RFA_RxHP = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=RxHP
PORT RFB_RxHP = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=RxHP
PORT RFC_RxHP = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=RxHP
PORT RFD_RxHP = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=RxHP

PORT RFA_SHDN = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SHDN
PORT RFB_SHDN = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SHDN
PORT RFC_SHDN = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SHDN
PORT RFD_SHDN = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SHDN

PORT RFA_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_SCLK
PORT RFB_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_SCLK
PORT RFC_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_SCLK
PORT RFD_SPI_SCLK = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_SCLK

PORT RFA_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_MOSI
PORT RFB_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_MOSI
PORT RFC_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_MOSI
PORT RFD_SPI_MOSI = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_MOSI

PORT RFA_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=SPI_CSn
PORT RFB_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=SPI_CSn
PORT RFC_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=SPI_CSn
PORT RFD_SPI_CSn = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=SPI_CSn

PORT RFA_B = "", DIR = O, VEC = [6:0], IO_IF=HW_Ports_RFA, IO_IS=B
PORT RFB_B = "", DIR = O, VEC = [6:0], IO_IF=HW_Ports_RFB, IO_IS=B
PORT RFC_B = "", DIR = O, VEC = [6:0], IO_IF=HW_Ports_RFC, IO_IS=B
PORT RFD_B = "", DIR = O, VEC = [6:0], IO_IF=HW_Ports_RFD, IO_IS=B

PORT RFA_LD = "", DIR = I, IO_IF=HW_Ports_RFA, IO_IS=LD
PORT RFB_LD = "", DIR = I, IO_IF=HW_Ports_RFB, IO_IS=LD
PORT RFC_LD = "", DIR = I, IO_IF=HW_Ports_RFC, IO_IS=LD
PORT RFD_LD = "", DIR = I, IO_IF=HW_Ports_RFD, IO_IS=LD

PORT RFA_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=PAEn_24
PORT RFB_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=PAEn_24
PORT RFC_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=PAEn_24
PORT RFD_PAEn_24 = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=PAEn_24

PORT RFA_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFA, IO_IS=PAEn_5
PORT RFB_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFB, IO_IS=PAEn_5
PORT RFC_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFC, IO_IS=PAEn_5
PORT RFD_PAEn_5 = "", DIR = O, IO_IF=HW_Ports_RFD, IO_IS=PAEn_5

PORT RFA_AntSw = "", DIR = O, VEC = [1:0], IO_IF=HW_Ports_RFA, IO_IS=AntSw
PORT RFB_AntSw = "", DIR = O, VEC = [1:0], IO_IF=HW_Ports_RFB, IO_IS=AntSw
PORT RFC_AntSw = "", DIR = O, VEC = [1:0], IO_IF=HW_Ports_RFC, IO_IS=AntSw
PORT RFD_AntSw = "", DIR = O, VEC = [1:0], IO_IF=HW_Ports_RFD, IO_IS=AntSw

PORT usr_RFA_TxEn = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=TxEn
PORT usr_RFB_TxEn = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=TxEn
PORT usr_RFC_TxEn = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=TxEn
PORT usr_RFD_TxEn = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=TxEn

PORT usr_RFA_RxEn = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=RxEn
PORT usr_RFB_RxEn = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=RxEn
PORT usr_RFC_RxEn = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=RxEn
PORT usr_RFD_RxEn = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=RxEn

PORT usr_RFA_RxHP = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=RxHP
PORT usr_RFB_RxHP = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=RxHP
PORT usr_RFC_RxHP = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=RxHP
PORT usr_RFD_RxHP = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=RxHP

PORT usr_RFA_SHDN = "", DIR = I, IO_IF=User_Ports_RFA, IO_IS=SHDN
PORT usr_RFB_SHDN = "", DIR = I, IO_IF=User_Ports_RFB, IO_IS=SHDN
PORT usr_RFC_SHDN = "", DIR = I, IO_IF=User_Ports_RFC, IO_IS=SHDN
PORT usr_RFD_SHDN = "", DIR = I, IO_IF=User_Ports_RFD, IO_IS=SHDN

PORT usr_RFA_RxGainRF = "", DIR = I, VEC = [1:0], IO_IF=User_Ports_RFA, IO_IS=RxGainRF
PORT usr_RFB_RxGainRF = "", DIR = I, VEC = [1:0], IO_IF=User_Ports_RFB, IO_IS=RxGainRF
PORT usr_RFC_RxGainRF = "", DIR = I, VEC = [1:0], IO_IF=User_Ports_RFC, IO_IS=RxGainRF
PORT usr_RFD_RxGainRF = "", DIR = I, VEC = [1:0], IO_IF=User_Ports_RFD, IO_IS=RxGainRF

PORT usr_RFA_RxGainBB = "", DIR = I, VEC = [4:0], IO_IF=User_Ports_RFA, IO_IS=RxGainBB
PORT usr_RFB_RxGainBB = "", DIR = I, VEC = [4:0], IO_IF=User_Ports_RFB, IO_IS=RxGainBB
PORT usr_RFC_RxGainBB = "", DIR = I, VEC = [4:0], IO_IF=User_Ports_RFC, IO_IS=RxGainBB
PORT usr_RFD_RxGainBB = "", DIR = I, VEC = [4:0], IO_IF=User_Ports_RFD, IO_IS=RxGainBB

PORT usr_RFA_TxGain = "", DIR = I, VEC = [5:0], IO_IF=User_Ports_RFA, IO_IS=TxGain
PORT usr_RFB_TxGain = "", DIR = I, VEC = [5:0], IO_IF=User_Ports_RFB, IO_IS=TxGain
PORT usr_RFC_TxGain = "", DIR = I, VEC = [5:0], IO_IF=User_Ports_RFC, IO_IS=TxGain
PORT usr_RFD_TxGain = "", DIR = I, VEC = [5:0], IO_IF=User_Ports_RFD, IO_IS=TxGain

PORT usr_RFA_PHYStart = "", DIR = O, IO_IF=User_Ports_RFA, IO_IS=PHYStart
PORT usr_RFB_PHYStart = "", DIR = O, IO_IF=User_Ports_RFB, IO_IS=PHYStart
PORT usr_RFC_PHYStart = "", DIR = O, IO_IF=User_Ports_RFC, IO_IS=PHYStart
PORT usr_RFD_PHYStart = "", DIR = O, IO_IF=User_Ports_RFD, IO_IS=PHYStart

PORT usr_SPI_ctrlSrc = "", DIR = I, IO_IF=User_Ports_Misc, IO_IS=SPI_ctrlSrc
PORT usr_SPI_go = "", DIR = I, IO_IF=User_Ports_Misc, IO_IS=SPI_go
PORT usr_SPI_active = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=SPI_active
PORT usr_SPI_rfsel = "", DIR = I, VEC = [3:0], IO_IF=User_Ports_Misc, IO_IS=SPI_rfsel
PORT usr_SPI_regaddr = "", DIR = I, VEC = [3:0], IO_IF=User_Ports_Misc, IO_IS=SPI_regaddr
PORT usr_SPI_regdata = "", DIR = I, VEC = [13:0], IO_IF=User_Ports_Misc, IO_IS=SPI_regdata

PORT usr_any_PHYStart = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=any_PHYStart

PORT usr_RFA_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_Tx
PORT usr_RFA_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFA_statLED_Rx
PORT usr_RFB_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_Tx
PORT usr_RFB_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFB_statLED_Rx
PORT usr_RFC_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_Tx
PORT usr_RFC_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFC_statLED_Rx
PORT usr_RFD_statLED_Tx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_Tx
PORT usr_RFD_statLED_Rx = "", DIR = O, IO_IF=User_Ports_Misc, IO_IS=usr_RFD_statLED_Rx

END
